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-rw-r--r--arch/arm/dts/at91-sam9x60_curiosity.dts21
-rw-r--r--arch/arm/dts/at91-sama5d27_wlsom1_ek.dts25
-rw-r--r--arch/arm/dts/at91-sama5d2_icp.dts22
-rw-r--r--arch/arm/dts/at91-sama7g5ek-u-boot.dtsi108
-rw-r--r--arch/arm/dts/at91-sama7g5ek.dts23
-rw-r--r--arch/arm/dts/sam9x60.dtsi85
-rw-r--r--arch/arm/dts/sam9x60ek.dts124
-rw-r--r--arch/arm/dts/sama5d2.dtsi1
-rw-r--r--arch/arm/dts/sama7g5.dtsi27
-rw-r--r--arch/arm/mach-at91/armv7/sama7g5_devices.c26
-rw-r--r--arch/arm/mach-at91/include/mach/sama7-sfr.h59
-rw-r--r--arch/arm/mach-at91/include/mach/sama7g5.h28
12 files changed, 524 insertions, 25 deletions
diff --git a/arch/arm/dts/at91-sam9x60_curiosity.dts b/arch/arm/dts/at91-sam9x60_curiosity.dts
index 7c5b6ae2b8..d6ae3d648d 100644
--- a/arch/arm/dts/at91-sam9x60_curiosity.dts
+++ b/arch/arm/dts/at91-sam9x60_curiosity.dts
@@ -49,6 +49,13 @@
atmel,pins =
<AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
+
+ usb1 {
+ pinctrl_usb_default: usb_default {
+ atmel,pins = <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
+ AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ };
};
};
};
@@ -89,3 +96,17 @@
phy-mode = "rmii";
status = "okay";
};
+
+&usb1 {
+ num-ports = <3>;
+ atmel,vbus-gpio = <0
+ &pioD 15 GPIO_ACTIVE_HIGH
+ &pioD 18 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_default>;
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/at91-sama5d27_wlsom1_ek.dts b/arch/arm/dts/at91-sama5d27_wlsom1_ek.dts
index eec183d5de..6d4b35ea96 100644
--- a/arch/arm/dts/at91-sama5d27_wlsom1_ek.dts
+++ b/arch/arm/dts/at91-sama5d27_wlsom1_ek.dts
@@ -143,7 +143,32 @@
pinmux = <PIN_PC9__GPIO>;
bias-pull-up;
};
+
+ pinctrl_usb_default: usb_default {
+ pinmux = <PIN_PA10__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_usba_vbus: usba_vbus {
+ pinmux = <PIN_PA16__GPIO>;
+ bias-disable;
+ };
};
};
};
};
+
+&usb1 {
+ num-ports = <3>;
+ atmel,vbus-gpio = <0
+ &pioA PIN_PA10 GPIO_ACTIVE_HIGH
+ 0
+ >;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_default>;
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/at91-sama5d2_icp.dts b/arch/arm/dts/at91-sama5d2_icp.dts
index 2dffae9c5c..4f796c6c94 100644
--- a/arch/arm/dts/at91-sama5d2_icp.dts
+++ b/arch/arm/dts/at91-sama5d2_icp.dts
@@ -154,7 +154,29 @@
<PIN_PA13__SDMMC0_CD>;
bias-disable;
};
+
+ pinctrl_usb_default: usb_default {
+ pinmux = <PIN_PC17__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_usba_vbus: usba_vbus {
+ pinmux = <PIN_PD23__GPIO>;
+ bias-disable;
+ };
};
};
};
};
+
+&usb1 {
+ num-ports = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_default>;
+ status = "okay";
+};
+
+&usb2 {
+ phy_type = "hsic";
+ status = "okay";
+};
diff --git a/arch/arm/dts/at91-sama7g5ek-u-boot.dtsi b/arch/arm/dts/at91-sama7g5ek-u-boot.dtsi
index d294ddb54a..a54cfaccbf 100644
--- a/arch/arm/dts/at91-sama7g5ek-u-boot.dtsi
+++ b/arch/arm/dts/at91-sama7g5ek-u-boot.dtsi
@@ -10,13 +10,88 @@
*
*/
+#include "sama7g5-pinfunc.h"
+#include <dt-bindings/reset/sama7g5-reset.h>
+#include <dt-bindings/clock/at91.h>
+
/ {
chosen {
u-boot,dm-pre-reloc;
};
+ utmi {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb_phy0: phy@0 {
+ compatible = "microchip,sama7g5-usb-phy";
+ sfr-phandle = <&sfr>;
+ reg = <0>;
+ clocks = <&utmi_clk USB_UTMI1>;
+ clock-names = "utmi_clk";
+ status = "disabled";
+ #phy-cells = <0>;
+ };
+
+ usb_phy1: phy@1 {
+ compatible = "microchip,sama7g5-usb-phy";
+ sfr-phandle = <&sfr>;
+ reg = <1>;
+ clocks = <&utmi_clk USB_UTMI2>;
+ clock-names = "utmi_clk";
+ status = "disabled";
+ #phy-cells = <0>;
+ };
+
+ usb_phy2: phy@2 {
+ compatible = "microchip,sama7g5-usb-phy";
+ sfr-phandle = <&sfr>;
+ reg = <2>;
+ clocks = <&utmi_clk USB_UTMI3>;
+ clock-names = "utmi_clk";
+ status = "disabled";
+ #phy-cells = <0>;
+ };
+ };
+
+ utmi_clk: utmi-clk {
+ compatible = "microchip,sama7g5-utmi-clk";
+ sfr-phandle = <&sfr>;
+ #clock-cells = <1>;
+ clocks = <&pmc PMC_TYPE_CORE 27>;
+ clock-names = "utmi_clk";
+ resets = <&reset_controller SAMA7G5_RESET_USB_PHY1>,
+ <&reset_controller SAMA7G5_RESET_USB_PHY2>,
+ <&reset_controller SAMA7G5_RESET_USB_PHY3>;
+ reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
+ };
+
soc {
u-boot,dm-pre-reloc;
+
+ usb2: usb@400000 {
+ compatible = "microchip,sama7g5-ohci", "usb-ohci";
+ reg = <0x00400000 0x100000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 106>, <&utmi_clk USB_UTMI1>, <&usb_clk>;
+ clock-names = "ohci_clk", "hclk", "uhpck";
+ status = "disabled";
+ };
+
+ usb3: usb@500000 {
+ compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
+ reg = <0x00500000 0x100000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&usb_clk>, <&pmc PMC_TYPE_PERIPHERAL 106>;
+ clock-names = "usb_clk", "ehci_clk";
+ status = "disabled";
+ };
+
+ sfr: sfr@e1624000 {
+ compatible = "microchip,sama7g5-sfr", "syscon";
+ reg = <0xe1624000 0x4000>;
+ };
};
};
@@ -38,6 +113,11 @@
&pioA {
u-boot,dm-pre-reloc;
+
+ pinctrl_usb_default: usb_default {
+ pinmux = <PIN_PC6__GPIO>;
+ bias-disable;
+ };
};
&pit64b0 {
@@ -60,3 +140,31 @@
u-boot,dm-pre-reloc;
};
+&usb2 {
+ num-ports = <3>;
+ atmel,vbus-gpio = <0
+ 0
+ &pioA PIN_PC6 GPIO_ACTIVE_HIGH
+ >;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_default>;
+ phys = <&usb_phy2>;
+ phy-names = "usb";
+ status = "okay";
+};
+
+&usb3 {
+ status = "okay";
+};
+
+&usb_phy0 {
+ status = "okay";
+};
+
+&usb_phy1 {
+ status = "okay";
+};
+
+&usb_phy2 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/at91-sama7g5ek.dts b/arch/arm/dts/at91-sama7g5ek.dts
index aed84f15a1..9b247fcaf6 100644
--- a/arch/arm/dts/at91-sama7g5ek.dts
+++ b/arch/arm/dts/at91-sama7g5ek.dts
@@ -45,13 +45,13 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_key_gpio_default>;
- bp1 {
+ button {
label = "PB_USER";
gpios = <&pioA PIN_PA12 GPIO_ACTIVE_LOW>;
linux,code = <KEY_PROG1>;
@@ -244,8 +244,8 @@
regulators {
vdd_3v3: VDD_IO {
regulator-name = "VDD_IO";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <3700000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-always-on;
@@ -264,8 +264,8 @@
vddioddr: VDD_DDR {
regulator-name = "VDD_DDR";
- regulator-min-microvolt = <1300000>;
- regulator-max-microvolt = <1450000>;
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-always-on;
@@ -285,8 +285,8 @@
vddcore: VDD_CORE {
regulator-name = "VDD_CORE";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1850000>;
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1150000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-always-on;
@@ -306,7 +306,7 @@
vddcpu: VDD_OTHER {
regulator-name = "VDD_OTHER";
regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1850000>;
+ regulator-max-microvolt = <1250000>;
regulator-initial-mode = <2>;
regulator-allowed-modes = <2>, <4>;
regulator-ramp-delay = <3125>;
@@ -326,8 +326,8 @@
vldo1: LDO1 {
regulator-name = "LDO1";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <3700000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-state-standby {
@@ -707,7 +707,6 @@
ck_cd_rstn_vddsel {
pinmux = <PIN_PA0__SDMMC0_CK>,
<PIN_PA2__SDMMC0_RSTN>,
- <PIN_PA14__SDMMC0_CD>,
<PIN_PA11__SDMMC0_DS>;
slew-rate = <0>;
bias-pull-up;
diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi
index a5c429eb3a..2b93d08938 100644
--- a/arch/arm/dts/sam9x60.dtsi
+++ b/arch/arm/dts/sam9x60.dtsi
@@ -69,6 +69,50 @@
#size-cells = <1>;
ranges;
+ usb1: usb@600000 {
+ compatible = "atmel,at91rm9200-ohci", "usb-ohci";
+ reg = <0x00600000 0x100000>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 21>;
+ clock-names = "ohci_clk", "hclk", "uhpck";
+ status = "disabled";
+ };
+
+ usb2: usb@700000 {
+ compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
+ reg = <0x00700000 0x100000>;
+ clocks = <&pmc PMC_TYPE_CORE 8>, <&pmc PMC_TYPE_PERIPHERAL 22>;
+ clock-names = "usb_clk", "ehci_clk";
+ assigned-clocks = <&pmc PMC_TYPE_CORE 8>;
+ assigned-clock-rates = <480000000>;
+ status = "disabled";
+ };
+
+ ebi: ebi@10000000 {
+ compatible = "microchip,sam9x60-ebi";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ atmel,smc = <&smc>;
+ microchip,sfr = <&sfr>;
+ reg = <0x10000000 0x60000000>;
+ ranges = <0x0 0x0 0x10000000 0x10000000
+ 0x1 0x0 0x20000000 0x10000000
+ 0x2 0x0 0x30000000 0x10000000
+ 0x3 0x0 0x40000000 0x10000000
+ 0x4 0x0 0x50000000 0x10000000
+ 0x5 0x0 0x60000000 0x10000000>;
+ clocks = <&pmc PMC_TYPE_CORE 11>;
+ status = "disabled";
+
+ nand_controller: nand-controller {
+ compatible = "microchip,sam9x60-nand-controller";
+ ecc-engine = <&pmecc>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+ };
+ };
+
sdhci0: sdhci-host@80000000 {
compatible = "microchip,sam9x60-sdhci";
reg = <0x80000000 0x300>;
@@ -82,6 +126,19 @@
pinctrl-0 = <&pinctrl_sdhci0>;
};
+ sdhci1: sdhci-host@90000000 {
+ compatible = "microchip,sam9x60-sdhci";
+ reg = <0x90000000 0x300>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>;
+ clock-names = "hclock", "multclk";
+ assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
+ assigned-clock-rates = <100000000>;
+ assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* ID_PLL_A_DIV */
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci1>;
+ };
+
apb {
compatible = "simple-bus";
#address-cells = <1>;
@@ -119,6 +176,11 @@
status = "disabled";
};
+ sfr: sfr@f8050000 {
+ compatible = "microchip,sam9x60-sfr", "syscon";
+ reg = <0xf8050000 0x100>;
+ };
+
dbgu: serial@fffff200 {
compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
reg = <0xfffff200 0x200>;
@@ -180,6 +242,29 @@
(AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>; /* PA20 DAT3 periph A with pullup */
};
};
+
+ sdhci1 {
+ pinctrl_sdhci1: sdhci1 {
+ atmel,pins =
+ <AT91_PIOA 13 AT91_PERIPH_B (AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA13 CK periph B */
+ AT91_PIOA 12 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA12 CMD periph B with pullup */
+ AT91_PIOA 11 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA11 DAT0 periph B with pullup */
+ AT91_PIOA 2 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA2 DAT1 periph B with pullup */
+ AT91_PIOA 3 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI) /* PA3 DAT2 periph B with pullup */
+ AT91_PIOA 4 AT91_PERIPH_B (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI)>; /* PA4 DAT3 periph B with pullup */
+ };
+ };
+ };
+
+ pmecc: ecc-engine@ffffe000 {
+ compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc";
+ reg = <0xffffe000 0x300>,
+ <0xffffe600 0x100>;
+ };
+
+ smc: smc@ffffea00 {
+ compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon";
+ reg = <0xffffea00 0x100>;
};
pioA: gpio@fffff400 {
diff --git a/arch/arm/dts/sam9x60ek.dts b/arch/arm/dts/sam9x60ek.dts
index eb44868a3e..45e2f4cc40 100644
--- a/arch/arm/dts/sam9x60ek.dts
+++ b/arch/arm/dts/sam9x60ek.dts
@@ -80,6 +80,44 @@
};
pinctrl {
+ nand {
+ pinctrl_nand_oe_we: nand-oe-we-0 {
+ atmel,pins =
+ <AT91_PIOD 0 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 1 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+ };
+
+ pinctrl_nand_rb: nand-rb-0 {
+ atmel,pins =
+ <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+ };
+
+ pinctrl_nand_cs: nand-cs-0 {
+ atmel,pins =
+ <AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
+ };
+ };
+
+ ebi {
+ pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
+ atmel,pins =
+ <AT91_PIOD 6 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 7 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 8 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 9 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 10 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 11 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 12 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 13 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+ };
+
+ pinctrl_ebi_addr_nand: ebi-addr-0 {
+ atmel,pins =
+ <AT91_PIOD 2 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)
+ AT91_PIOD 3 AT91_PERIPH_A (AT91_PINCTRL_NONE | AT91_PINCTRL_SLEWRATE_DIS)>;
+ };
+ };
+
pinctrl_qspi: qspi {
atmel,pins =
<AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE
@@ -101,6 +139,78 @@
<AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
+ usb1 {
+ pinctrl_usb_default: usb_default {
+ atmel,pins = <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
+ AT91_PIOD 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ };
+
+ };
+ };
+ };
+};
+
+&ebi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>;
+ status = "okay";
+
+ nand_controller: nand-controller {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand_oe_we &pinctrl_nand_cs &pinctrl_nand_rb>;
+ status = "okay";
+
+ nand@3 {
+ reg = <0x3 0x0 0x800000>;
+ rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
+ cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <512>;
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ at91bootstrap@0 {
+ label = "at91bootstrap";
+ reg = <0x0 0x40000>;
+ };
+
+ uboot@40000 {
+ label = "u-boot";
+ reg = <0x40000 0xc0000>;
+ };
+
+ ubootenvred@100000 {
+ label = "U-Boot Env Redundant";
+ reg = <0x100000 0x40000>;
+ };
+
+ ubootenv@140000 {
+ label = "U-Boot Env";
+ reg = <0x140000 0x40000>;
+ };
+
+ dtb@180000 {
+ label = "device tree";
+ reg = <0x180000 0x80000>;
+ };
+
+ kernel@200000 {
+ label = "kernel";
+ reg = <0x200000 0x600000>;
+ };
+
+ rootfs@800000 {
+ label = "rootfs";
+ reg = <0x800000 0x1f800000>;
+ };
};
};
};
@@ -110,3 +220,17 @@
phy-mode = "rmii";
status = "okay";
};
+
+&usb1 {
+ num-ports = <3>;
+ atmel,vbus-gpio = <0
+ &pioD 15 GPIO_ACTIVE_HIGH
+ &pioD 16 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_default>;
+ status = "okay";
+};
+
+&usb2 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/sama5d2.dtsi b/arch/arm/dts/sama5d2.dtsi
index 790b746ed1..187c2ff2fb 100644
--- a/arch/arm/dts/sama5d2.dtsi
+++ b/arch/arm/dts/sama5d2.dtsi
@@ -84,7 +84,6 @@
reg = <0xf0014000 0x160>;
#address-cells = <1>;
#size-cells = <0>;
- #interrupt-cells = <1>;
u-boot,dm-pre-reloc;
main: mainck {
diff --git a/arch/arm/dts/sama7g5.dtsi b/arch/arm/dts/sama7g5.dtsi
index d38090d7dd..6388a60e53 100644
--- a/arch/arm/dts/sama7g5.dtsi
+++ b/arch/arm/dts/sama7g5.dtsi
@@ -15,6 +15,7 @@
#include <dt-bindings/clk/at91.h>
#include <dt-bindings/dma/at91.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/mfd/at91-usart.h>
/ {
model = "Microchip SAMA7G5 family SoC";
@@ -195,11 +196,11 @@
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
};
pmc: pmc@e0018000 {
@@ -211,6 +212,13 @@
clock-names = "td_slck", "md_slck", "main_xtal", "main_rc";
};
+ reset_controller: reset-controller@e001d000 {
+ compatible = "microchip,sama7g5-rstc";
+ reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>;
+ #reset-cells = <1>;
+ clocks = <&clk32k 0>;
+ };
+
shdwc: shdwc@e001d010 {
compatible = "microchip,sama7g5-shdwc", "syscon";
reg = <0xe001d010 0x10>;
@@ -229,13 +237,6 @@
clocks = <&clk32k 0>;
};
- reset_controller: rstc@e001d000 {
- compatible = "microchip,sama7g5-rstc", "microchip,sam9x60-rstc";
- reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>;
- #reset-cells = <1>;
- clocks = <&clk32k 0>;
- };
-
clk32k: clock-controller@e001d050 {
compatible = "microchip,sama7g5-sckc", "microchip,sam9x60-sckc";
reg = <0xe001d050 0x4>;
@@ -620,6 +621,7 @@
uart0: serial@200 {
compatible = "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
clock-names = "usart";
@@ -668,6 +670,7 @@
uart3: serial@200 {
compatible = "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
clock-names = "usart";
@@ -711,6 +714,7 @@
uart4: serial@200 {
compatible = "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 42>;
clock-names = "usart";
@@ -736,6 +740,7 @@
uart7: serial@200 {
compatible = "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
+ atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
clock-names = "usart";
@@ -884,9 +889,9 @@
#address-cells = <1>;
#size-cells = <0>;
atmel,fifo-size = <32>;
- dmas = <&dma0 AT91_XDMAC_DT_PERID(27)>,
- <&dma0 AT91_XDMAC_DT_PERID(28)>;
- dma-names = "rx", "tx";
+ dmas = <&dma0 AT91_XDMAC_DT_PERID(28)>,
+ <&dma0 AT91_XDMAC_DT_PERID(27)>;
+ dma-names = "tx", "rx";
status = "disabled";
};
};
diff --git a/arch/arm/mach-at91/armv7/sama7g5_devices.c b/arch/arm/mach-at91/armv7/sama7g5_devices.c
index 0b702c7fb7..6f2c1fc914 100644
--- a/arch/arm/mach-at91/armv7/sama7g5_devices.c
+++ b/arch/arm/mach-at91/armv7/sama7g5_devices.c
@@ -4,7 +4,31 @@
* Eugen Hristev <eugen.hristev@microchip.com>
*/
+#include <asm/arch/sama7g5.h>
+
char *get_cpu_name(void)
{
- return "SAMA7G5";
+ unsigned int extension_id = get_extension_chip_id();
+
+ if (cpu_is_sama7g5())
+ switch (extension_id) {
+ case ARCH_EXID_SAMA7G51:
+ return "SAMA7G51";
+ case ARCH_EXID_SAMA7G52:
+ return "SAMA7G52";
+ case ARCH_EXID_SAMA7G53:
+ return "SAMA7G53";
+ case ARCH_EXID_SAMA7G54:
+ return "SAMA7G54";
+ case ARCH_EXID_SAMA7G54_D1G:
+ return "SAMA7G54 1Gb DDR3L SiP";
+ case ARCH_EXID_SAMA7G54_D2G:
+ return "SAMA7G54 2Gb DDR3L SiP";
+ case ARCH_EXID_SAMA7G54_D4G:
+ return "SAMA7G54 4Gb DDR3L SiP";
+ default:
+ return "Unknown CPU type";
+ }
+ else
+ return "Unknown CPU type";
}
diff --git a/arch/arm/mach-at91/include/mach/sama7-sfr.h b/arch/arm/mach-at91/include/mach/sama7-sfr.h
new file mode 100644
index 0000000000..a987ff5465
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/sama7-sfr.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Microchip SFR (Special Function Registers) registers for SAMA7 family.
+ *
+ * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Cristian Birsan <cristian.birsan@microchip.com>
+ */
+
+#ifndef _LINUX_MFD_SYSCON_AT91_SAMA7_SFR_H
+#define _LINUX_MFD_SYSCON_AT91_SAMA7_SFR_H
+
+#define SAMA7_SFR_OHCIICR 0x00 /* OHCI INT Configuration Register */
+#define SAMA7_SFR_OHCIISR 0x04 /* OHCI INT Status Register */
+/* 0x08 ~ 0xe3: Reserved */
+#define SAMA7_SFR_WPMR 0xe4 /* Write Protection Mode Register */
+#define SAMA7_SFR_WPSR 0xe4 /* Write Protection Status Register */
+/* 0xec ~ 0x200b: Reserved */
+#define SAMA7_SFR_DEBUG 0x200c /* Debug Register */
+
+/* 0x2010 ~ 0x2027: Reserved */
+#define SAMA7_SFR_EHCIOHCI 0x2020 /* EHCI OHCI Clock Configuration Reg */
+
+#define SAMA7_SFR_HSS_AXI_QOS 0x2028 /* HSS AXI QOS Register */
+#define SAMA7_SFR_UDDRC 0x202c /* UDDRC Register */
+#define SAMA7_SFR_CAN_SRAM_SEL 0x2030 /* CAN SRAM Select. Register */
+/* 0x2034 ~ 0x203f: Reserved */
+
+#define SAMA7_SFR_UTMI0 0x2040
+#define SAMA7_SFR_UTMI0R(x) (SAMA7_SFR_UTMI0 + 4 * (x))
+
+#define SAMA7_SFR_UTMI0R0 0x2040 /* UTMI0 Configuration Register */
+#define SAMA7_SFR_UTMI0R1 0x2044 /* UTMI1 Configuration Register */
+#define SAMA7_SFR_UTMI0R2 0x2048 /* UTMI2 Configuration Register */
+
+/* Field definitions */
+#define SAMA7_SFR_OHCIICR_ARIE BIT(0)
+#define SAMA7_SFR_OHCIICR_APPSTART BIT(1)
+#define SAMA7_SFR_OHCIICR_USB_SUSP(x) BIT(8 + (x))
+#define SAMA7_SFR_OHCIICR_USB_SUSPEND GENMASK(10, 8)
+
+#define SAMA7_SFR_OHCIISR_RIS(x) BIT(x)
+
+#define SAMA7_SFR_WPMR_WPEN BIT(0)
+#define SAMA7_SFR_WPMR_KEY 0x53465200 /* SFR in ASCII*/
+#define SAMA7_SFR_WPMR_WPKEY_MASK GENMASK(31, 8)
+
+#define SAMA7_SFR_WPSR_WPSRC_MASK GENMASK(23, 8)
+#define SAMA7_SFR_WPSR_WPVS_MASK BIT(0)
+
+#define SAMA7_SFR_CAN_SRAM_UPPER(x) BIT(x)
+
+#define SAMA7_SFR_UTMI_RX_VBUS BIT(25) /* VBUS Valid bit */
+#define SAMA7_SFR_UTMI_RX_TX_PREEM_AMP_TUNE_1X BIT(23) /* TXPREEMPAMPTUNE 1x */
+#define SAMA7_SFR_UTMI_COMMONON BIT(3) /* PLL Common ON bit */
+
+#define SAMA7_SFR_EHCIOHCI_PHYCLK BIT(1) /* Alternate PHY Clk */
+
+#endif /* _LINUX_MFD_SYSCON_AT91_SAMA7_SFR_H */
diff --git a/arch/arm/mach-at91/include/mach/sama7g5.h b/arch/arm/mach-at91/include/mach/sama7g5.h
index ae43e8700b..621a26f6eb 100644
--- a/arch/arm/mach-at91/include/mach/sama7g5.h
+++ b/arch/arm/mach-at91/include/mach/sama7g5.h
@@ -67,7 +67,35 @@
#define ATMEL_BASE_PIT64BC ATMEL_BASE_PIT64B0
+/* SAMA7G5 series chip id definitions */
+#define ARCH_ID_SAMA7G5 0x80162100
+#define ARCH_EXID_SAMA7G51 0x00000003
+#define ARCH_EXID_SAMA7G52 0x00000002
+#define ARCH_EXID_SAMA7G53 0x00000001
+#define ARCH_EXID_SAMA7G54 0x00000000
+#define ARCH_EXID_SAMA7G54_D1G 0x00000018
+#define ARCH_EXID_SAMA7G54_D2G 0x00000020
+#define ARCH_EXID_SAMA7G54_D4G 0x00000028
+
+#define cpu_is_sama7g5() (get_chip_id() == ARCH_ID_SAMA7G5)
+#define cpu_is_sama7g51() (cpu_is_sama7g5() && \
+ (get_extension_chip_id() == ARCH_EXID_SAMA7G51))
+#define cpu_is_sama7g52() (cpu_is_sama7g5() && \
+ (get_extension_chip_id() == ARCH_EXID_SAMA7G52))
+#define cpu_is_sama7g53() (cpu_is_sama7g5() && \
+ (get_extension_chip_id() == ARCH_EXID_SAMA7G53))
+#define cpu_is_sama7g54() (cpu_is_sama7g5() && \
+ (get_extension_chip_id() == ARCH_EXID_SAMA7G54))
+#define cpu_is_sama7g54d1g() (cpu_is_sama7g5() && \
+ (get_extension_chip_id() == ARCH_EXID_SAMA7G54_D1G))
+#define cpu_is_sama7g54d2g() (cpu_is_sama7g5() && \
+ (get_extension_chip_id() == ARCH_EXID_SAMA7G54_D2G))
+#define cpu_is_sama7g54d4g() (cpu_is_sama7g5() && \
+ (get_extension_chip_id() == ARCH_EXID_SAMA7G54_D4G))
+
#ifndef __ASSEMBLY__
+unsigned int get_chip_id(void);
+unsigned int get_extension_chip_id(void);
char *get_cpu_name(void);
#endif
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-28 17:56:51 +0000