diff options
Diffstat (limited to 'arch')
50 files changed, 8411 insertions, 2630 deletions
diff --git a/arch/arm/dts/tegra20-paz00.dts b/arch/arm/dts/tegra20-paz00.dts index 5d8f21059f..5cf604e865 100644 --- a/arch/arm/dts/tegra20-paz00.dts +++ b/arch/arm/dts/tegra20-paz00.dts @@ -522,8 +522,8 @@ power-supply = <&vdd_bl_reg>; pwms = <&pwm 0 5000000>; - brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>; - default-brightness-level = <10>; + brightness-levels = <1 35 70 105 140 175 210 255>; + default-brightness-level = <2>; backlight-boot-off; }; diff --git a/arch/arm/dts/tegra30-asus-grouper-common.dtsi b/arch/arm/dts/tegra30-asus-grouper-common.dtsi index c9277388c9..e8a3511a9f 100644 --- a/arch/arm/dts/tegra30-asus-grouper-common.dtsi +++ b/arch/arm/dts/tegra30-asus-grouper-common.dtsi @@ -44,6 +44,718 @@ }; }; + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + clk_32k_out_pa0 { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat3_pb4", + "sdmmc3_dat2_pb5", + "sdmmc3_dat1_pb6", + "sdmmc3_dat0_pb7", + "sdmmc3_dat4_pd1", + "sdmmc3_dat6_pd3", + "sdmmc3_dat7_pd4"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_a17_pb0 { + nvidia,pins = "gmi_a17_pb0", + "gmi_a18_pb1"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_pwr0_pb2 { + nvidia,pins = "lcd_pwr0_pb2", + "lcd_pwr1_pc1", + "lcd_m1_pw1"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + lcd_pclk_pb3 { + nvidia,pins = "lcd_pclk_pb3", + "lcd_d0_pe0", + "lcd_d1_pe1", + "lcd_d2_pe2", + "lcd_d3_pe3", + "lcd_d4_pe4", + "lcd_d5_pe5", + "lcd_d6_pe6", + "lcd_d7_pe7", + "lcd_d8_pf0", + "lcd_d9_pf1", + "lcd_d10_pf2", + "lcd_d11_pf3", + "lcd_d12_pf4", + "lcd_d13_pf5", + "lcd_d14_pf6", + "lcd_d15_pf7", + "lcd_de_pj1", + "lcd_hsync_pj3", + "lcd_vsync_pj4", + "lcd_d16_pm0", + "lcd_d17_pm1", + "lcd_d18_pm2", + "lcd_d19_pm3", + "lcd_d20_pm4", + "lcd_d21_pm5", + "lcd_d22_pm6", + "lcd_d23_pm7", + "lcd_cs0_n_pn4", + "lcd_sdout_pn5", + "lcd_dc0_pn6", + "lcd_cs1_n_pw0", + "lcd_sdin_pz2", + "lcd_sck_pz4"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2", + "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3", + "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gen1_i2c_scl_pc4 { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7", + "gmi_wait_pi7", + "gmi_cs4_n_pk2", + "gmi_cs3_n_pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad12_ph4 { + nvidia,pins = "gmi_ad12_ph4", + "gmi_cs0_n_pj0", + "gmi_cs1_n_pj2", + "gmi_cs2_n_pk3"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3_dat5_pd0 { + nvidia,pins = "sdmmc3_dat5_pd0"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad0_pg0 { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad1_pg1", + "gmi_ad14_ph6", + "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad2_pg2 { + nvidia,pins = "gmi_ad2_pg2", + "gmi_ad3_pg3", + "gmi_ad6_pg6", + "gmi_ad7_pg7"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad4_pg4 { + nvidia,pins = "gmi_ad4_pg4", + "gmi_ad5_pg5"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_ad8_ph0 { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "pwm0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad9_ph1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad10_ph2 { + nvidia,pins = "gmi_ad10_ph2"; + nvidia,function = "pwm2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad11_ph3 { + nvidia,pins = "gmi_ad11_ph3"; + nvidia,function = "pwm3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad13_ph5 { + nvidia,pins = "gmi_ad13_ph5", + "gmi_wr_n_pi0", + "gmi_oe_n_pi1", + "gmi_adv_n_pk0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad15_ph7 { + nvidia,pins = "gmi_ad15_ph7"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_dqs_pi2 { + nvidia,pins = "gmi_dqs_pi2", + "pu2", + "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_rst_n_pi4 { + nvidia,pins = "gmi_rst_n_pi4"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_iordy_pi5 { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_cs7_n_pi6 { + nvidia,pins = "gmi_cs7_n_pi6", + "gmi_clk_pk1"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_a16_pj7 { + nvidia,pins = "gmi_a16_pj7", + "gmi_a19_pk7"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spdif_out_pk5 { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spdif_in_pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap1_fs_pn0 { + nvidia,pins = "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_dout_pn2", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ulpi_data3_po4 { + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap4_fs_pp4 { + nvidia,pins = "dap4_fs_pp4", + "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0", + "kb_col1_pq1", + "kb_row1_pr1"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_col2_pq2 { + nvidia,pins = "kb_col2_pq2", + "kb_col3_pq3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_col4_pq4 { + nvidia,pins = "kb_col4_pq4", + "kb_col5_pq5", + "kb_col7_pq7", + "kb_row2_pr2", + "kb_row4_pr4", + "kb_row5_pr5", + "kb_row14_ps6"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row6_pr6 { + nvidia,pins = "kb_row6_pr6", + "kb_row8_ps0", + "kb_row9_ps1", + "kb_row10_ps2"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row11_ps3 { + nvidia,pins = "kb_row11_ps3", + "kb_row12_ps4"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pu0 { + nvidia,pins = "pu0", + "pu6"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + jtag_rtck_pu7 { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pv0 { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + crt_hsync_pv6 { + nvidia,pins = "crt_hsync_pv6", + "crt_vsync_pv7"; + nvidia,function = "crt"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spi2_cs1_n_pw2 { + nvidia,pins = "spi2_cs1_n_pw2", + "spi2_miso_px1", + "spi2_sck_px2"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + clk1_out_pw4 { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + clk2_out_pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi2_cs0_n_px3 { + nvidia,pins = "spi2_cs0_n_px3"; + nvidia,function = "spi6"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi1_mosi_px4 { + nvidia,pins = "spi1_mosi_px4", + "spi1_cs0_n_px6"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_dir_py1"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + sdmmc1_dat3_py4 { + nvidia,pins = "sdmmc1_dat3_py4", + "sdmmc1_dat2_py5", + "sdmmc1_dat1_py6", + "sdmmc1_dat0_py7", + "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_wr_n_pz3 { + nvidia,pins = "lcd_wr_n_pz3"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sys_clk_req_pz5 { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + pbb0 { + nvidia,pins = "pbb0", + "pcc1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pbb7 { + nvidia,pins = "pbb7", + "pcc2"; + nvidia,function = "i2s4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + cam_mclk_pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_rst_n_pcc3 { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "dap"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pex_l2_rst_n_pcc6 { + nvidia,pins = "pex_l2_rst_n_pcc6", + "pex_l2_clkreq_n_pcc7"; + nvidia,function = "pcie"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pex_wake_n_pdd3 { + nvidia,pins = "pex_wake_n_pdd3", + "pex_l2_prsnt_n_pdd7"; + nvidia,function = "pcie"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + clk1_req_pee2 { + nvidia,pins = "clk1_req_pee2"; + nvidia,function = "dap"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + owr { + nvidia,pins = "owr"; + nvidia,function = "owr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + drive_dap1 { + nvidia,pins = "drive_dap1", + "drive_dap2", + "drive_dbg", + "drive_at5", + "drive_gme", + "drive_ddc", + "drive_ao1", + "drive_uart3"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + drive_sdio1 { + nvidia,pins = "drive_sdio1", + "drive_sdio3"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,pull-down-strength = <46>; + nvidia,pull-up-strength = <42>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>; + }; + drive_gma { + nvidia,pins = "drive_gma", + "drive_gmb", + "drive_gmc", + "drive_gmd"; + nvidia,pull-down-strength = <9>; + nvidia,pull-up-strength = <9>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + }; + }; + }; + uarta: serial@70006000 { status = "okay"; }; diff --git a/arch/arm/dts/tegra30-asus-nexus7-grouper-E1565.dts b/arch/arm/dts/tegra30-asus-nexus7-grouper-E1565.dts index bfc675ca92..1714e083e9 100644 --- a/arch/arm/dts/tegra30-asus-nexus7-grouper-E1565.dts +++ b/arch/arm/dts/tegra30-asus-nexus7-grouper-E1565.dts @@ -7,6 +7,119 @@ model = "ASUS Google Nexus 7 (Project Nakasi / ME370T) E1565"; compatible = "asus,grouper", "nvidia,tegra30"; + pinmux@70000868 { + state_default: pinmux { + lcd_dc1_pd2 { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spi2_cs2_n_pw3 { + nvidia,pins = "spi2_cs2_n_pw3"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi1_sck_px5 { + nvidia,pins = "spi1_sck_px5"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi1_miso_px7 { + nvidia,pins = "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi2_mosi_px0 { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row15_ps7 { + nvidia,pins = "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row13_ps5 { + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7", + "gmi_wait_pi7", + "gmi_cs4_n_pk2", + "gmi_cs3_n_pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_cs6_n_pi3 { + nvidia,pins = "gmi_cs6_n_pi3"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + }; + }; + i2c@7000d000 { pmic: max77663@3c { compatible = "maxim,max77663"; diff --git a/arch/arm/dts/tegra30-asus-nexus7-grouper-PM269.dts b/arch/arm/dts/tegra30-asus-nexus7-grouper-PM269.dts index cf03011bc1..e7765a4a6a 100644 --- a/arch/arm/dts/tegra30-asus-nexus7-grouper-PM269.dts +++ b/arch/arm/dts/tegra30-asus-nexus7-grouper-PM269.dts @@ -7,6 +7,119 @@ model = "ASUS Google Nexus 7 (Project Nakasi / ME370T) PM269"; compatible = "asus,grouper", "nvidia,tegra30"; + pinmux@70000868 { + state_default: pinmux { + lcd_dc1_pd2 { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spi2_cs2_n_pw3 { + nvidia,pins = "spi2_cs2_n_pw3"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi1_sck_px5 { + nvidia,pins = "spi1_sck_px5"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi1_miso_px7 { + nvidia,pins = "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi2_mosi_px0 { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row15_ps7 { + nvidia,pins = "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row13_ps5 { + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7", + "gmi_wait_pi7", + "gmi_cs4_n_pk2", + "gmi_cs3_n_pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_cs6_n_pi3 { + nvidia,pins = "gmi_cs6_n_pi3"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + }; + }; + i2c@7000d000 { /* Texas Instruments TPS659110 PMIC */ pmic: tps65911@2d { diff --git a/arch/arm/dts/tegra30-asus-nexus7-tilapia-E1565.dts b/arch/arm/dts/tegra30-asus-nexus7-tilapia-E1565.dts index ef8b2b5049..3f0dff8fe6 100644 --- a/arch/arm/dts/tegra30-asus-nexus7-tilapia-E1565.dts +++ b/arch/arm/dts/tegra30-asus-nexus7-tilapia-E1565.dts @@ -7,6 +7,155 @@ model = "ASUS Google Nexus 7 (Project Bach / ME370TG) E1565"; compatible = "asus,tilapia", "nvidia,tegra30"; + pinmux@70000868 { + state_default: pinmux { + lcd_dc1_pd2 { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spi2_cs2_n_pw3 { + nvidia,pins = "spi2_cs2_n_pw3"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spi1_sck_px5 { + nvidia,pins = "spi1_sck_px5"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi1_miso_px7 { + nvidia,pins = "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spi2_mosi_px0 { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ulpi_stp_py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row15_ps7 { + nvidia,pins = "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap3_sclk_pp3 { + nvidia,pins = "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_row3_pr3 { + nvidia,pins = "kb_row3_pr3", + "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row13_ps5 { + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7", + "gmi_wait_pi7", + "gmi_cs4_n_pk2", + "gmi_cs3_n_pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_cs6_n_pi3 { + nvidia,pins = "gmi_cs6_n_pi3"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + }; + }; + i2c@7000d000 { pmic: max77663@3c { compatible = "maxim,max77663"; diff --git a/arch/arm/dts/tegra30-asus-p1801-t.dts b/arch/arm/dts/tegra30-asus-p1801-t.dts index 19de984d5f..350443d55e 100644 --- a/arch/arm/dts/tegra30-asus-p1801-t.dts +++ b/arch/arm/dts/tegra30-asus-p1801-t.dts @@ -60,6 +60,988 @@ }; }; + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* SDMMC1 pinmux */ + sdmmc1_clk { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1_cmd { + nvidia,pins = "sdmmc1_dat3_py4", + "sdmmc1_dat2_py5", + "sdmmc1_dat1_py6", + "sdmmc1_dat0_py7", + "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1_cd { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1_wp { + nvidia,pins = "vi_d11_pt3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* SDMMC2 pinmux */ + vi_d1_pd5 { + nvidia,pins = "vi_d1_pd5", + "vi_d2_pl0", + "vi_d3_pl1", + "vi_d5_pl3", + "vi_d7_pl5"; + nvidia,function = "sdmmc2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + vi_d8_pl6 { + nvidia,pins = "vi_d8_pl6", + "vi_d9_pl7"; + nvidia,function = "sdmmc2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + + /* SDMMC3 pinmux */ + sdmmc3_clk { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3_cmd { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "sdmmc3_dat4_pd1", + "sdmmc3_dat5_pd0", + "sdmmc3_dat6_pd3", + "sdmmc3_dat7_pd4"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* SDMMC4 pinmux */ + sdmmc4_clk { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_cmd { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_rst_n { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + cam_mclk { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + drive_sdmmc4 { + nvidia,pins = "drive_gma", + "drive_gmb", + "drive_gmc", + "drive_gmd"; + nvidia,pull-down-strength = <9>; + nvidia,pull-up-strength = <9>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + }; + + /* I2C pinmux */ + gen1_i2c { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + gen2_i2c { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + cam_i2c { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + ddc_i2c { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + pwr_i2c { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + hotplug_i2c { + nvidia,pins = "pu4"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* HDMI pinmux */ + hdmi_cec { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + hdmi_hpd { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* UART-A */ + ulpi_data0_po1 { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ulpi_data1_po2 { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi_data5_po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0", + "ulpi_data2_po3", + "ulpi_data3_po4", + "ulpi_data4_po5", + "ulpi_data6_po7"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* UART-B */ + uartb_txd_rts { + nvidia,pins = "uart2_txd_pc2", + "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + uartb_rxd_cts { + nvidia,pins = "uart2_rxd_pc3", + "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* UART-C */ + uartc_rxd_cts { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uartc_txd_rts { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* UART-D */ + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_dir_py1", + "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* I2S pinmux */ + dap_i2s0 { + nvidia,pins = "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_dout_pn2", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap_i2s1 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap3_fs { + nvidia,pins = "dap3_fs_pp0", + "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap3_dout { + nvidia,pins = "dap3_dout_pp2", + "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap_i2s3 { + nvidia,pins = "dap4_fs_pp4", + "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* sensors pinmux */ + nct_irq { + nvidia,pins = "pcc2"; + nvidia,function = "i2s4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Asus EC pinmux */ + ec_irqs { + nvidia,pins = "kb_row10_ps2", + "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ec_reqs { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* memory type bootstrap */ + mem_boostraps { + nvidia,pins = "gmi_ad4_pg4", + "gmi_ad5_pg5"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PCI-e pinmux */ + pex_l2_rst_n { + nvidia,pins = "pex_l2_rst_n_pcc6", + "pex_l0_rst_n_pdd1", + "pex_l1_rst_n_pdd5"; + nvidia,function = "pcie"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pex_l2_clkreq_n { + nvidia,pins = "pex_l2_clkreq_n_pcc7", + "pex_l0_prsnt_n_pdd0", + "pex_l0_clkreq_n_pdd2", + "pex_wake_n_pdd3", + "pex_l1_prsnt_n_pdd4", + "pex_l1_clkreq_n_pdd6", + "pex_l2_prsnt_n_pdd7"; + nvidia,function = "pcie"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* SPI pinmux */ + spi1_mosi_px4 { + nvidia,pins = "spi1_mosi_px4", + "spi1_sck_px5", + "spi1_cs0_n_px6", + "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi2_cs1_n_pw2 { + nvidia,pins = "spi2_cs1_n_pw2"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi2_sck_px2 { + nvidia,pins = "spi2_sck_px2"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_a17_pb0 { + nvidia,pins = "gmi_a17_pb0", + "gmi_a16_pj7"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_a18_pb1 { + nvidia,pins = "gmi_a18_pb1"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_a19_pk7 { + nvidia,pins = "gmi_a19_pk7"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Display A pinmux */ + lcd_pwr0_pb2 { + nvidia,pins = "lcd_pwr0_pb2", + "lcd_pclk_pb3", + "lcd_pwr1_pc1", + "lcd_d0_pe0", + "lcd_d1_pe1", + "lcd_d2_pe2", + "lcd_d3_pe3", + "lcd_d4_pe4", + "lcd_d5_pe5", + "lcd_d6_pe6", + "lcd_d7_pe7", + "lcd_d8_pf0", + "lcd_d9_pf1", + "lcd_d10_pf2", + "lcd_d11_pf3", + "lcd_d12_pf4", + "lcd_d13_pf5", + "lcd_d14_pf6", + "lcd_d15_pf7", + "lcd_de_pj1", + "lcd_hsync_pj3", + "lcd_vsync_pj4", + "lcd_d16_pm0", + "lcd_d17_pm1", + "lcd_d18_pm2", + "lcd_d19_pm3", + "lcd_d20_pm4", + "lcd_d21_pm5", + "lcd_d22_pm6", + "lcd_d23_pm7", + "lcd_cs1_n_pw0", + "lcd_dc0_pn6", + "lcd_sck_pz4", + "lcd_sdin_pz2"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_cs0_n_pn4 { + nvidia,pins = "lcd_cs0_n_pn4", + "lcd_sdout_pn5", + "lcd_wr_n_pz3"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + blink { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* KBC keys */ + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb_col1_pq1 { + nvidia,pins = "kb_row1_pr1", + "kb_row3_pr3", + "kb_row9_ps1", + "kb_row11_ps3", + "kb_row14_ps6", + "kb_col6_pq6"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_col4_pq4 { + nvidia,pins = "kb_col4_pq4", + "kb_col5_pq5", + "kb_col7_pq7", + "kb_row2_pr2", + "kb_row4_pr4", + "kb_row5_pr5", + "kb_row12_ps4", + "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7", + "gmi_wait_pi7", + "gmi_cs3_n_pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_cs0_n_pj0 { + nvidia,pins = "gmi_cs0_n_pj0", + "gmi_cs1_n_pj2", + "gmi_cs2_n_pk3"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + vi_pclk_pt0 { + nvidia,pins = "vi_pclk_pt0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + + /* GPIO keys pinmux */ + power_key { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + vol_keys { + nvidia,pins = "kb_col2_pq2", + "kb_col3_pq3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Bluetooth */ + bt_shutdown { + nvidia,pins = "pu0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + bt_dev_wake { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + bt_host_wake { + nvidia,pins = "pu6"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pcc1 { + nvidia,pins = "pcc1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pv2 { + nvidia,pins = "pv2"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pv3 { + nvidia,pins = "pv3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + vi_vsync_pd6 { + nvidia,pins = "vi_vsync_pd6", + "vi_hsync_pd7"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + vi_d10_pt2 { + nvidia,pins = "vi_d10_pt2", + "vi_d0_pt4", "pbb0"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + gmi_ad0_pg0 { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad1_pg1", + "gmi_ad2_pg2", + "gmi_ad3_pg3", + "gmi_ad6_pg6", + "gmi_ad7_pg7", + "gmi_wr_n_pi0", + "gmi_oe_n_pi1", + "gmi_dqs_pi2", + "gmi_adv_n_pk0", + "gmi_clk_pk1"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad13_ph5 { + nvidia,pins = "gmi_ad13_ph5"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_ad10_ph2 { + nvidia,pins = "gmi_ad10_ph2", + "gmi_ad11_ph3", + "gmi_ad14_ph6"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad12_ph4 { + nvidia,pins = "gmi_ad12_ph4", + "gmi_rst_n_pi4"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + /* USB2 VBUS control */ + usb2_vbus_control { + nvidia,pins = "gmi_ad15_ph7"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + /* PWM pinmux */ + pwm_0 { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "pwm0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pwm_1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pwm_2 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* S/PDIF pinmux */ + spdif_out { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spdif_in { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + vi_d4_pl2 { + nvidia,pins = "vi_d4_pl2"; + nvidia,function = "vi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + vi_d6_pl4 { + nvidia,pins = "vi_d6_pl4"; + nvidia,function = "vi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + vi_mclk_pt1 { + nvidia,pins = "vi_mclk_pt1"; + nvidia,function = "vi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + jtag_rtck { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + crt_hsync_pv6 { + nvidia,pins = "crt_hsync_pv6", + "crt_vsync_pv7"; + nvidia,function = "crt"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + clk1_out { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + clk2_out { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + clk3_out { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + sys_clk_req { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5", + "clk1_req_pee2"; + nvidia,function = "dap"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + owr { + nvidia,pins = "owr"; + nvidia,function = "owr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* P1801-T specific pinmux */ + lcd_pwr2 { + nvidia,pins = "lcd_pwr2_pc6", + "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_m1 { + nvidia,pins = "lcd_m1_pw1"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + key_mode { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + splashtop { + nvidia,pins = "gmi_cs6_n_pi3"; + nvidia,function = "nand_alt"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + w8_detect { + nvidia,pins = "gmi_cs7_n_pi6"; + nvidia,function = "nand_alt"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi2_mosi_px0 { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi6"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + tp_vendor { + nvidia,pins = "kb_row6_pr6", + "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + tp_power { + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* GPIO power/drive control */ + drive_dap1 { + nvidia,pins = "drive_dap1", + "drive_dap2", + "drive_dbg", + "drive_at5", + "drive_gme", + "drive_ddc", + "drive_ao1", + "drive_uart3"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + drive_sdio1 { + nvidia,pins = "drive_sdio1", + "drive_sdio3"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,pull-down-strength = <46>; + nvidia,pull-up-strength = <42>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>; + }; + }; + }; + uarta: serial@70006000 { status = "okay"; }; diff --git a/arch/arm/dts/tegra30-asus-tf201.dts b/arch/arm/dts/tegra30-asus-tf201.dts index 59e19f9766..12dd909b5f 100644 --- a/arch/arm/dts/tegra30-asus-tf201.dts +++ b/arch/arm/dts/tegra30-asus-tf201.dts @@ -7,6 +7,51 @@ model = "ASUS Transformer Prime TF201"; compatible = "asus,tf201", "nvidia,tegra30"; + pinmux@70000868 { + state_default: pinmux { + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6", + "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gmi_cs4_n_pk2 { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + }; + }; + usb-phy@7d008000 { /delete-property/ nvidia,xcvr-setup-use-fuses; nvidia,xcvr-setup = <5>; /* Based on TF201 fuse value - 48 */ diff --git a/arch/arm/dts/tegra30-asus-tf300t.dts b/arch/arm/dts/tegra30-asus-tf300t.dts index db08488420..b30afa3022 100644 --- a/arch/arm/dts/tegra30-asus-tf300t.dts +++ b/arch/arm/dts/tegra30-asus-tf300t.dts @@ -15,4 +15,49 @@ output-low; }; }; + + pinmux@70000868 { + state_default: pinmux { + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6", + "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gmi_cs4_n_pk2 { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + }; + }; }; diff --git a/arch/arm/dts/tegra30-asus-tf300tg.dts b/arch/arm/dts/tegra30-asus-tf300tg.dts index 6f42182c99..83921c664c 100644 --- a/arch/arm/dts/tegra30-asus-tf300tg.dts +++ b/arch/arm/dts/tegra30-asus-tf300tg.dts @@ -6,4 +6,132 @@ / { model = "ASUS Transformer Pad 3G TF300TG"; compatible = "asus,tf300tg", "nvidia,tegra30"; + + pinmux@70000868 { + state_default: pinmux { + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gmi_cs4_n_pk2 { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6", + "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + spi2_cs2_n_pw3 { + nvidia,pins = "spi2_cs2_n_pw3"; + nvidia,function = "spi2"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + spi1_sck_px5 { + nvidia,pins = "spi1_sck_px5"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + spi2_mosi_px0 { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi2"; + }; + + spi1_miso_px7 { + nvidia,pins = "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + ulpi_stp_py3 { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + }; + }; }; diff --git a/arch/arm/dts/tegra30-asus-tf300tl.dts b/arch/arm/dts/tegra30-asus-tf300tl.dts index 242f79170c..13b96fd0b0 100644 --- a/arch/arm/dts/tegra30-asus-tf300tl.dts +++ b/arch/arm/dts/tegra30-asus-tf300tl.dts @@ -6,4 +6,167 @@ / { model = "ASUS Transformer Pad LTE TF300TL"; compatible = "asus,tf300tl", "nvidia,tegra30"; + + pinmux@70000868 { + state_default: pinmux { + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6", + "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + gmi_cs4_n_pk2 { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* TF300TL specific pinmux reconfiguration */ + + ulpi_data5_po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + dap3_din_pp1 { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + crt_hsync_pv6 { + nvidia,pins = "crt_hsync_pv6"; + nvidia,function = "crt"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + crt_vsync_pv7 { + nvidia,pins = "crt_vsync_pv7"; + nvidia,function = "crt"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + dap1_fs_pn0 { + nvidia,pins = "dap1_fs_pn0", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + dap1_din_pn1 { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + dap1_dout_pn2 { + nvidia,pins = "dap1_dout_pn2"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + clk1_req_pee2 { + nvidia,pins = "clk1_req_pee2"; + nvidia,function = "dap"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + spi2_mosi_px0 { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi2"; + }; + + spi1_sck_px5 { + nvidia,pins = "spi1_sck_px5"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + spi1_miso_px7 { + nvidia,pins = "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + spi2_cs2_n_pw3 { + nvidia,pins = "spi2_cs2_n_pw3"; + nvidia,function = "spi2"; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + }; + }; }; diff --git a/arch/arm/dts/tegra30-asus-tf600t.dts b/arch/arm/dts/tegra30-asus-tf600t.dts index 3f11d33bc4..f49e7341fe 100644 --- a/arch/arm/dts/tegra30-asus-tf600t.dts +++ b/arch/arm/dts/tegra30-asus-tf600t.dts @@ -53,6 +53,895 @@ }; }; + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* SDMMC1 pinmux */ + sdmmc1_clk { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1_cmd { + nvidia,pins = "sdmmc1_dat3_py4", + "sdmmc1_dat2_py5", + "sdmmc1_dat1_py6", + "sdmmc1_dat0_py7", + "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1_cd { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1_wp { + nvidia,pins = "vi_d11_pt3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* SDMMC2 pinmux */ + vi_d1_pd5 { + nvidia,pins = "vi_d1_pd5", + "vi_d2_pl0", + "vi_d3_pl1", + "vi_d5_pl3", + "vi_d7_pl5"; + nvidia,function = "sdmmc2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + vi_d8_pl6 { + nvidia,pins = "vi_d8_pl6", + "vi_d9_pl7"; + nvidia,function = "sdmmc2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + + /* SDMMC3 pinmux */ + sdmmc3_clk { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3_cmd { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "sdmmc3_dat4_pd1", + "sdmmc3_dat5_pd0", + "sdmmc3_dat6_pd3", + "sdmmc3_dat7_pd4"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* SDMMC4 pinmux */ + sdmmc4_clk { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_cmd { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_rst_n { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + cam_mclk { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* I2C pinmux */ + gen1_i2c { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + gen2_i2c { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + cam_i2c { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + ddc_i2c { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + pwr_i2c { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + hotplug_i2c { + nvidia,pins = "pu4"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* HDMI pinmux */ + hdmi_cec { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + hdmi_hpd { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* UART-A */ + ulpi_data0_po1 { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ulpi_data1_po2 { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi_data5_po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0", + "ulpi_data2_po3", + "ulpi_data3_po4", + "ulpi_data4_po5", + "ulpi_data6_po7"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* UART-B */ + uartb_txd_rts { + nvidia,pins = "uart2_txd_pc2", + "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + uartb_rxd_cts { + nvidia,pins = "uart2_rxd_pc3", + "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* UART-C */ + uartc_rxd_cts { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uartc_txd_rts { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* UART-D */ + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_dir_py1", + "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* I2S pinmux */ + dap_i2s0 { + nvidia,pins = "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_dout_pn2", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap_i2s1 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap3_fs { + nvidia,pins = "dap3_fs_pp0"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap3_din { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap3_dout { + nvidia,pins = "dap3_dout_pp2", + "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap_i2s3 { + nvidia,pins = "dap4_fs_pp4", + "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + i2s4 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Sensors pinmux */ + nct_irq { + nvidia,pins = "pcc2"; + nvidia,function = "i2s4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + hall { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Asus EC pinmux */ + ec_irqs { + nvidia,pins = "kb_row10_ps2", + "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ec_reqs { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Memory type bootstrap */ + mem_boostraps { + nvidia,pins = "gmi_ad4_pg4", + "gmi_ad5_pg5"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PCI-e pinmux */ + pex_l2_rst_n { + nvidia,pins = "pex_l2_rst_n_pcc6", + "pex_l0_rst_n_pdd1", + "pex_l1_rst_n_pdd5"; + nvidia,function = "pcie"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pex_l2_clkreq_n { + nvidia,pins = "pex_l2_clkreq_n_pcc7", + "pex_l0_prsnt_n_pdd0", + "pex_l0_clkreq_n_pdd2", + "pex_wake_n_pdd3", + "pex_l1_prsnt_n_pdd4", + "pex_l1_clkreq_n_pdd6", + "pex_l2_prsnt_n_pdd7"; + nvidia,function = "pcie"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Display A pinmux */ + lcd_pwr0_pb2 { + nvidia,pins = "lcd_pwr0_pb2", + "lcd_pclk_pb3", + "lcd_pwr1_pc1", + "lcd_d0_pe0", + "lcd_d1_pe1", + "lcd_d2_pe2", + "lcd_d3_pe3", + "lcd_d4_pe4", + "lcd_d5_pe5", + "lcd_d6_pe6", + "lcd_d7_pe7", + "lcd_d8_pf0", + "lcd_d9_pf1", + "lcd_d10_pf2", + "lcd_d11_pf3", + "lcd_d12_pf4", + "lcd_d13_pf5", + "lcd_d14_pf6", + "lcd_d15_pf7", + "lcd_de_pj1", + "lcd_hsync_pj3", + "lcd_vsync_pj4", + "lcd_d16_pm0", + "lcd_d17_pm1", + "lcd_d18_pm2", + "lcd_d19_pm3", + "lcd_d20_pm4", + "lcd_d21_pm5", + "lcd_d22_pm6", + "lcd_d23_pm7", + "lcd_cs1_n_pw0", + "lcd_m1_pw1", + "lcd_dc0_pn6", + "lcd_sck_pz4", + "lcd_sdin_pz2"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_cs0_n_pn4 { + nvidia,pins = "lcd_sdout_pn5", + "lcd_wr_n_pz3", + "lcd_pwr2_pc6", + "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + blink { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* KBC keys */ + kb_col0 { + nvidia,pins = "kb_col0_pq0", + "kb_row1_pr1", + "kb_row3_pr3", + "kb_row6_pr6", + "kb_row8_ps0", + "kb_row9_ps1", + "kb_row11_ps3", + "kb_row14_ps6", + "kb_col6_pq6"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_col5 { + nvidia,pins = "kb_col5_pq5", + "kb_col7_pq7", + "kb_row2_pr2", + "kb_row4_pr4", + "kb_row5_pr5", + "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gmi_cs0_n_pj0 { + nvidia,pins = "gmi_wp_n_pc7", + "gmi_wait_pi7", + "gmi_cs0_n_pj0", + "gmi_cs1_n_pj2", + "gmi_cs2_n_pk3", + "gmi_cs3_n_pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + vi_pclk_pt0 { + nvidia,pins = "vi_pclk_pt0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + + /* GPIO keys pinmux */ + power_key { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + vol_keys { + nvidia,pins = "kb_col3_pq3", + "kb_col4_pq4"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Bluetooth */ + bt_shutdown { + nvidia,pins = "pu0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + bt_dev_wake { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + bt_host_wake { + nvidia,pins = "pu6"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pcc1 { + nvidia,pins = "pcc1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pv2 { + nvidia,pins = "pv2"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pv3 { + nvidia,pins = "pv3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + vi_vsync_pd6 { + nvidia,pins = "vi_vsync_pd6", + "vi_hsync_pd7"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + vi_d10_pt2 { + nvidia,pins = "vi_d10_pt2", + "vi_d0_pt4", "pbb0"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + gmi_ad0_pg0 { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad1_pg1", + "gmi_ad2_pg2", + "gmi_ad3_pg3", + "gmi_ad6_pg6", + "gmi_ad7_pg7", + "gmi_wr_n_pi0", + "gmi_oe_n_pi1", + "gmi_dqs_pi2", + "gmi_adv_n_pk0", + "gmi_clk_pk1"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad13_ph5 { + nvidia,pins = "gmi_ad13_ph5"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_ad10_ph2 { + nvidia,pins = "gmi_ad10_ph2", + "gmi_ad11_ph3", + "gmi_ad14_ph6"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad12_ph4 { + nvidia,pins = "gmi_ad12_ph4", + "gmi_rst_n_pi4", + "gmi_cs7_n_pi6"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Vibrator control */ + vibrator { + nvidia,pins = "gmi_ad11_ph3"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* PWM pinmux */ + pwm_0 { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "pwm0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pwm_1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pwm_2 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gmi_cs_n { + nvidia,pins = "gmi_cs4_n_pk2", + "gmi_cs6_n_pi3"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Spdif pinmux */ + spdif_out { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spdif_in { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + vi_d4_pl2 { + nvidia,pins = "vi_d4_pl2"; + nvidia,function = "vi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + vi_d6_pl4 { + nvidia,pins = "vi_d6_pl4"; + nvidia,function = "vi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,lock = <0>; + nvidia,ioreset = <0>; + }; + vi_mclk_pt1 { + nvidia,pins = "vi_mclk_pt1"; + nvidia,function = "vi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + jtag { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + crt_sync { + nvidia,pins = "crt_hsync_pv6", + "crt_vsync_pv7"; + nvidia,function = "crt"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + clk1_out { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + clk2_out { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + clk3_out { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + sys_clk_req { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5", + "clk1_req_pee2"; + nvidia,function = "dap"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + owr { + nvidia,pins = "owr"; + nvidia,function = "owr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* GPIO power/drive control */ + drive_dap1 { + nvidia,pins = "drive_dap1", + "drive_dap2", + "drive_dbg", + "drive_at5", + "drive_gme", + "drive_ddc", + "drive_ao1", + "drive_uart3"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + drive_sdio1 { + nvidia,pins = "drive_sdio1", + "drive_sdio3"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,pull-down-strength = <46>; + nvidia,pull-up-strength = <42>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>; + }; + drive_sdmmc4 { + nvidia,pins = "drive_gma", + "drive_gmb", + "drive_gmc", + "drive_gmd"; + nvidia,pull-down-strength = <9>; + nvidia,pull-up-strength = <9>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + }; + }; + }; + uarta: serial@70006000 { status = "okay"; }; diff --git a/arch/arm/dts/tegra30-asus-tf700t.dts b/arch/arm/dts/tegra30-asus-tf700t.dts index d530527c9f..cc03f5a7ec 100644 --- a/arch/arm/dts/tegra30-asus-tf700t.dts +++ b/arch/arm/dts/tegra30-asus-tf700t.dts @@ -9,5 +9,58 @@ /delete-node/ host1x@50000000; + pinmux@70000868 { + state_default: pinmux { + lcd_pwr2_pc6 { + nvidia,pins = "lcd_pwr2_pc6", + "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + spi2_mosi_px0 { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + kb_row7_pr7 { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + gmi_cs4_n_pk2 { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + }; + }; + /delete-node/ panel; }; diff --git a/arch/arm/dts/tegra30-asus-transformer.dtsi b/arch/arm/dts/tegra30-asus-transformer.dtsi index c4649eee79..e6cc6e7105 100644 --- a/arch/arm/dts/tegra30-asus-transformer.dtsi +++ b/arch/arm/dts/tegra30-asus-transformer.dtsi @@ -37,6 +37,990 @@ }; }; + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* SDMMC1 pinmux */ + sdmmc1_clk { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + sdmmc1_cmd { + nvidia,pins = "sdmmc1_dat3_py4", + "sdmmc1_dat2_py5", + "sdmmc1_dat1_py6", + "sdmmc1_dat0_py7", + "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + sdmmc1_cd { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + sdmmc1_wp { + nvidia,pins = "vi_d11_pt3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* SDMMC2 pinmux */ + vi_d1_pd5 { + nvidia,pins = "vi_d1_pd5", + "vi_d2_pl0", + "vi_d3_pl1", + "vi_d5_pl3", + "vi_d7_pl5"; + nvidia,function = "sdmmc2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + vi_d8_pl6 { + nvidia,pins = "vi_d8_pl6", + "vi_d9_pl7"; + nvidia,function = "sdmmc2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + nvidia,io-reset = <0>; + }; + + /* SDMMC3 pinmux */ + sdmmc3_clk { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + sdmmc3_cmd { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "sdmmc3_dat4_pd1", + "sdmmc3_dat5_pd0", + "sdmmc3_dat6_pd3", + "sdmmc3_dat7_pd4"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* SDMMC4 pinmux */ + sdmmc4_clk { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + sdmmc4_cmd { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + sdmmc4_rst_n { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + cam_mclk { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + drive_sdmmc4 { + nvidia,pins = "drive_gma", + "drive_gmb", + "drive_gmc", + "drive_gmd"; + nvidia,pull-down-strength = <9>; + nvidia,pull-up-strength = <9>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + }; + + /* I2C pinmux */ + gen1_i2c { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + + gen2_i2c { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + + cam_i2c { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + + ddc_i2c { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + + pwr_i2c { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + + hotplug_i2c { + nvidia,pins = "pu4"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* HDMI pinmux */ + hdmi_cec { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + hdmi_hpd { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* UART-A */ + ulpi_data0_po1 { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + ulpi_data1_po2 { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + ulpi_data5_po6 { + nvidia,pins = "ulpi_data5_po6"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0", + "ulpi_data2_po3", + "ulpi_data3_po4", + "ulpi_data4_po5", + "ulpi_data6_po7"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* UART-B */ + uartb_txd_rts { + nvidia,pins = "uart2_txd_pc2", + "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + uartb_rxd_cts { + nvidia,pins = "uart2_rxd_pc3", + "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* UART-C */ + uartc_rxd_cts { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + uartc_txd_rts { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* UART-D */ + ulpi_nxt_py2 { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_dir_py1", + "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* I2S pinmux */ + dap_i2s0 { + nvidia,pins = "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_dout_pn2", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + dap_i2s1 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + dap3_fs { + nvidia,pins = "dap3_fs_pp0", + "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + dap3_dout { + nvidia,pins = "dap3_dout_pp2", + "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + dap_i2s3 { + nvidia,pins = "dap4_fs_pp4", + "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Sensors pinmux */ + nct_irq { + nvidia,pins = "pcc2"; + nvidia,function = "i2s4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Asus EC pinmux */ + ec_irqs { + nvidia,pins = "kb_row10_ps2", + "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + ec_reqs { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Memory type bootstrap */ + mem_boostraps { + nvidia,pins = "gmi_ad4_pg4", + "gmi_ad5_pg5"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PCI-e pinmux */ + pex_l2_rst_n { + nvidia,pins = "pex_l2_rst_n_pcc6", + "pex_l0_rst_n_pdd1", + "pex_l1_rst_n_pdd5"; + nvidia,function = "pcie"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + pex_l2_clkreq_n { + nvidia,pins = "pex_l2_clkreq_n_pcc7", + "pex_l0_prsnt_n_pdd0", + "pex_l0_clkreq_n_pdd2", + "pex_wake_n_pdd3", + "pex_l1_prsnt_n_pdd4", + "pex_l1_clkreq_n_pdd6", + "pex_l2_prsnt_n_pdd7"; + nvidia,function = "pcie"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* SPI pinmux */ + spi1_mosi_px4 { + nvidia,pins = "spi1_mosi_px4", + "spi1_sck_px5", + "spi1_cs0_n_px6", + "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + hp_detect { + nvidia,pins = "spi2_cs1_n_pw2"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + mic_detect { + nvidia,pins = "spi2_sck_px2"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gmi_a17_pb0 { + nvidia,pins = "gmi_a17_pb0", + "gmi_a16_pj7"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + gmi_a18_pb1 { + nvidia,pins = "gmi_a18_pb1"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gmi_a19_pk7 { + nvidia,pins = "gmi_a19_pk7"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Display A pinmux */ + lcd_pwr0_pb2 { + nvidia,pins = "lcd_pwr0_pb2", + "lcd_pclk_pb3", + "lcd_pwr1_pc1", + "lcd_d0_pe0", + "lcd_d1_pe1", + "lcd_d2_pe2", + "lcd_d3_pe3", + "lcd_d4_pe4", + "lcd_d5_pe5", + "lcd_d6_pe6", + "lcd_d7_pe7", + "lcd_d8_pf0", + "lcd_d9_pf1", + "lcd_d10_pf2", + "lcd_d11_pf3", + "lcd_d12_pf4", + "lcd_d13_pf5", + "lcd_d14_pf6", + "lcd_d15_pf7", + "lcd_de_pj1", + "lcd_hsync_pj3", + "lcd_vsync_pj4", + "lcd_d16_pm0", + "lcd_d17_pm1", + "lcd_d18_pm2", + "lcd_d19_pm3", + "lcd_d20_pm4", + "lcd_d21_pm5", + "lcd_d22_pm6", + "lcd_d23_pm7", + "lcd_cs1_n_pw0", + "lcd_m1_pw1", + "lcd_dc0_pn6", + "lcd_sck_pz4", + "lcd_sdin_pz2"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + lcd_cs0_n_pn4 { + nvidia,pins = "lcd_cs0_n_pn4", + "lcd_sdout_pn5", + "lcd_wr_n_pz3"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + blink { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* KBC keys */ + kb_col0_pq0 { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + kb_col1_pq1 { + nvidia,pins = "kb_row1_pr1", + "kb_row3_pr3", + "kb_row6_pr6", + "kb_row8_ps0", + "kb_row9_ps1", + "kb_row11_ps3", + "kb_row14_ps6", + "kb_col6_pq6"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + kb_col4_pq4 { + nvidia,pins = "kb_col4_pq4", + "kb_col5_pq5", + "kb_col7_pq7", + "kb_row2_pr2", + "kb_row4_pr4", + "kb_row5_pr5", + "kb_row12_ps4", + "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7", + "gmi_wait_pi7", + "gmi_cs3_n_pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + gmi_cs0_n_pj0 { + nvidia,pins = "gmi_cs0_n_pj0", + "gmi_cs1_n_pj2", + "gmi_cs2_n_pk3"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + vi_pclk_pt0 { + nvidia,pins = "vi_pclk_pt0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + nvidia,io-reset = <0>; + }; + + /* GPIO keys pinmux */ + power_key { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + vol_keys { + nvidia,pins = "kb_col2_pq2", + "kb_col3_pq3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Bluetooth */ + bt_shutdown { + nvidia,pins = "pu0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + bt_dev_wake { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + bt_host_wake { + nvidia,pins = "pu6"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + pcc1 { + nvidia,pins = "pcc1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pv2 { + nvidia,pins = "pv2"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + pv3 { + nvidia,pins = "pv3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + vi_vsync_pd6 { + nvidia,pins = "vi_vsync_pd6", + "vi_hsync_pd7"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + nvidia,io-reset = <0>; + }; + + vi_d10_pt2 { + nvidia,pins = "vi_d10_pt2", + "vi_d0_pt4", "pbb0"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + gmi_ad0_pg0 { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad1_pg1", + "gmi_ad2_pg2", + "gmi_ad3_pg3", + "gmi_ad6_pg6", + "gmi_ad7_pg7", + "gmi_wr_n_pi0", + "gmi_oe_n_pi1", + "gmi_dqs_pi2", + "gmi_adv_n_pk0", + "gmi_clk_pk1"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + gmi_ad13_ph5 { + nvidia,pins = "gmi_ad13_ph5"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gmi_ad10_ph2 { + nvidia,pins = "gmi_ad10_ph2", + "gmi_ad11_ph3", + "gmi_ad14_ph6"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + gmi_ad12_ph4 { + nvidia,pins = "gmi_ad12_ph4", + "gmi_rst_n_pi4", + "gmi_cs7_n_pi6"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Vibrator control */ + vibrator { + nvidia,pins = "gmi_ad15_ph7"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* PWM pimnmux */ + pwm_0 { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "pwm0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pwm_1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pwm_2 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gmi_cs6_n_pi3 { + nvidia,pins = "gmi_cs6_n_pi3"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* Spdif pinmux */ + spdif_out { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + spdif_in { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + vi_d4_pl2 { + nvidia,pins = "vi_d4_pl2"; + nvidia,function = "vi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + vi_d6_pl4 { + nvidia,pins = "vi_d6_pl4"; + nvidia,function = "vi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,lock = <0>; + nvidia,io-reset = <0>; + }; + + vi_mclk_pt1 { + nvidia,pins = "vi_mclk_pt1"; + nvidia,function = "vi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + jtag_rtck { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + crt_hsync_pv6 { + nvidia,pins = "crt_hsync_pv6", + "crt_vsync_pv7"; + nvidia,function = "crt"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + clk1_out { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + clk2_out { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + clk3_out { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + sys_clk_req { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5", + "clk1_req_pee2"; + nvidia,function = "dap"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + owr { + nvidia,pins = "owr"; + nvidia,function = "owr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* GPIO power/drive control */ + drive_dap1 { + nvidia,pins = "drive_dap1", + "drive_dap2", + "drive_dbg", + "drive_at5", + "drive_gme", + "drive_ddc", + "drive_ao1", + "drive_uart3"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + + drive_sdio1 { + nvidia,pins = "drive_sdio1", + "drive_sdio3"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,pull-down-strength = <46>; + nvidia,pull-up-strength = <42>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>; + }; + }; + }; + uarta: serial@70006000 { status = "okay"; }; diff --git a/arch/arm/dts/tegra30-htc-endeavoru.dts b/arch/arm/dts/tegra30-htc-endeavoru.dts index 21cd0f9207..dbff795bd8 100644 --- a/arch/arm/dts/tegra30-htc-endeavoru.dts +++ b/arch/arm/dts/tegra30-htc-endeavoru.dts @@ -52,6 +52,1153 @@ }; }; + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* PORT A */ + clk_32k_out { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + bt_uart_cts { + nvidia,pins = "uart3_cts_n_pa1"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + aud_aic3008_i2s { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + wifi_sdio_clock { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + wifi_sdio_command { + nvidia,pins = "sdmmc3_cmd_pa7"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT B */ + mdm_imc_uart { + nvidia,pins = "gmi_a17_pb0", + "gmi_a18_pb1"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + aud_3v3_en { + nvidia,pins = "lcd_pwr0_pb2", + "lcd_pclk_pb3"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + wifi_sdio_data { + nvidia,pins = "sdmmc3_dat3_pb4", + "sdmmc3_dat2_pb5", + "sdmmc3_dat1_pb6", + "sdmmc3_dat0_pb7"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT C */ + bt_uart_rts { + nvidia,pins = "uart3_rts_n_pc0"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + mdm_ap2bb_rst_pwrdwn { + nvidia,pins = "lcd_pwr1_pc1"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + cam_spi_clk_do { + nvidia,pins = "uart2_txd_pc2", + "uart2_rxd_pc3"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + per_sensor_i2c { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + mdm_ap2bb_slave_wakeup { + nvidia,pins = "lcd_pwr2_pc6"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + mhl_int { + nvidia,pins = "gmi_wp_n_pc7"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT D */ + sdmmc3_data { + nvidia,pins = "sdmmc3_dat5_pd0", + "sdmmc3_dat4_pd1"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + aud_1v8_en { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3_dat6_pd3 { + nvidia,pins = "sdmmc3_dat6_pd3", + "sdmmc3_dat7_pd4"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT E */ + mhl_usb_sel { + nvidia,pins = "lcd_d0_pe0"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + lcd_d1_pe1 { + nvidia,pins = "lcd_d1_pe1"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + peh_cap_int { + nvidia,pins = "lcd_d2_pe2"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + mhl_1v2_en { + nvidia,pins = "lcd_d3_pe3", + "lcd_d4_pe4"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dsp_lcm_1v8_en { + nvidia,pins = "lcd_d5_pe5"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + mhl_rst { + nvidia,pins = "lcd_d6_pe6"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + peh_vibrator_on { + nvidia,pins = "lcd_d7_pe7"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT F */ + cam_vcm_2v85_pwr { + nvidia,pins = "lcd_d8_pf0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_d9_d13 { + nvidia,pins = "lcd_d9_pf1", + "lcd_d10_pf2", + "lcd_d11_pf3", + "lcd_d12_pf4", + "lcd_d13_pf5"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + cam_cam2_core_1v8_en { + nvidia,pins = "lcd_d14_pf6"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sys_pmu_msecure { + nvidia,pins = "lcd_d15_pf7"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* PORT G */ + bootstraps { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad1_pg1", + "gmi_ad2_pg2", + "gmi_ad3_pg3", + "gmi_ad4_pg4", + "gmi_ad5_pg5", + "gmi_ad6_pg6", + "gmi_ad7_pg7"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT H */ + haptic_pwm { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "pwm0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi_ad9 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_ad10 { + nvidia,pins = "gmi_ad10_ph2"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dsp_tp_rst { + nvidia,pins = "gmi_ad11_ph3", + "gmi_ad12_ph4", + "gmi_ad13_ph5", + "gmi_ad14_ph6"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_ad15 { + nvidia,pins = "gmi_ad15_ph7"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT I */ + gmi_wr_n { + nvidia,pins = "gmi_wr_n_pi0", + "gmi_oe_n_pi1", + "gmi_dqs_pi2", + "gmi_cs6_n_pi3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_rst_n_pi4 { + nvidia,pins = "gmi_rst_n_pi4"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sim_detect { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + peh_gyr_int { + nvidia,pins = "gmi_cs7_n_pi6", + "gmi_wait_pi7"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT J */ + mdm_bb2ap_host_wakeup { + nvidia,pins = "gmi_cs0_n_pj0"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dsp_lcm_de { + nvidia,pins = "lcd_de_pj1"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + peh_comp_int { + nvidia,pins = "gmi_cs1_n_pj2"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_hsync { + nvidia,pins = "lcd_hsync_pj3"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + mdm_ap_usb_uart_oe { + nvidia,pins = "lcd_vsync_pj4"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + mcam_spi_di_cs0 { + nvidia,pins = "uart2_cts_n_pj5", + "uart2_rts_n_pj6"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + mdm_tx { + nvidia,pins = "gmi_a16_pj7"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* PORT K */ + gmi_adv_n { + nvidia,pins = "gmi_adv_n_pk0", + "gmi_clk_pk1", + "gmi_cs2_n_pk3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_cs4_n { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi_cs3_n { + nvidia,pins = "gmi_cs3_n_pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spdif_out { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + spdif_in { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + mdm_rts { + nvidia,pins = "gmi_a19_pk7"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* PORT L */ + port_l { + nvidia,pins = "vi_d2_pl0", + "vi_d3_pl1", + "vi_d4_pl2", + "vi_d5_pl3", + "vi_d6_pl4", + "vi_d7_pl5", + "vi_d8_pl6", + "vi_d9_pl7"; + nvidia,function = "sdmmc2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT M */ + dsp_lcd_id { + nvidia,pins = "lcd_d16_pm0", + "lcd_d17_pm1"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + front_cam_rst { + nvidia,pins = "lcd_d18_pm2"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + mdm_v_dcin_modem_en { + nvidia,pins = "lcd_d19_pm3", + "lcd_d20_pm4"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + nfc_pins { + nvidia,pins = "lcd_d21_pm5", + "lcd_d22_pm6"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + cam_vaa_2v85_en { + nvidia,pins = "lcd_d23_pm7"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT N */ + mdm_ap2bb_rst_host_pwr { + nvidia,pins = "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + mdm_bb_fatal_int { + nvidia,pins = "dap1_dout_pn2"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_cs0_n { + nvidia,pins = "lcd_cs0_n_pn4"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_sdout { + nvidia,pins = "lcd_sdout_pn5"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dsp_lcd_rst { + nvidia,pins = "lcd_dc0_pn6"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + mhl_hpd { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT O */ + ap_usb_uart_sel { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + bsp_ap_debug_tx { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + bsp_ap_debug_rx { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi_data2 { + nvidia,pins = "ulpi_data2_po3"; + nvidia,function = "spi3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + con_wifi_irq { + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "hsi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + per_gsensor_int { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi_data5_data6 { + nvidia,pins = "ulpi_data5_po6", + "ulpi_data6_po7"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT P */ + aud_ap_pcm { + nvidia,pins = "dap3_fs_pp0", + "dap3_din_pp1", + "dap3_dout_pp2", + "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + aud_btpcm { + nvidia,pins = "dap4_fs_pp4", + "dap4_din_pp5"; + nvidia,function = "i2s3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + aud_ext { + nvidia,pins = "dap4_dout_pp6", + "dap4_sclk_pp7"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* PORT Q */ + port_q { + nvidia,pins = "kb_col0_pq0", + "kb_col1_pq1", + "kb_col2_pq2", + "kb_col3_pq3", + "kb_col4_pq4", + "kb_col5_pq5", + "kb_col6_pq6", + "kb_col7_pq7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT R */ + raw_intr0 { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + per_torch_en { + nvidia,pins = "kb_row1_pr1"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gyro_pwr { + nvidia,pins = "kb_row2_pr2"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + haptic_en { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row4_row5 { + nvidia,pins = "kb_row4_pr4", + "kb_row5_pr5"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + cam_id { + nvidia,pins = "kb_row6_pr6", + "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT S */ + dsp_vol_up { + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + con_usb_id_1 { + nvidia,pins = "kb_row9_ps1", + "kb_row10_ps2"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + port_s { + nvidia,pins = "kb_row11_ps3", + "kb_row12_ps4", + "kb_row13_ps5", + "kb_row14_ps6", + "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT T */ + dsp_tw_i2c { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + per_emmc_cmd { + nvidia,pins = "sdmmc4_cmd_pt7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT U */ + con_bt_en { + nvidia,pins = "pu0", "pu1", "pu2", + "pu3", "pu4"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + per_capsensor_int_cpu { + nvidia,pins = "pu5"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dsp_ap_kpdpwr { + nvidia,pins = "pu6"; + nvidia,function = "pwm3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + jtag_rtck { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT V */ + mdm_bb2ap_suspend_req { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dsp_tp_att { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + con_wifi_en { + nvidia,pins = "pv2", "pv3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + mhl_ddc { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + crt_hsync { + nvidia,pins = "crt_hsync_pv6"; + nvidia,function = "crt"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + crt_vsync { + nvidia,pins = "crt_vsync_pv7"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* PORT W */ + pwr_chg_stat { + nvidia,pins = "lcd_cs1_n_pw0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dsp_bl_pwm_cpu { + nvidia,pins = "lcd_m1_pw1"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + aud_hp_det { + nvidia,pins = "spi2_cs1_n_pw2"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dsp_vol_down { + nvidia,pins = "spi2_cs2_n_pw3"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + aud_mclk { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + aud_aic3008_rst { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + con_bt_tx { + nvidia,pins = "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + con_bt_rx { + nvidia,pins = "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT X */ + aud_spi_do { + nvidia,pins = "spi2_mosi_px0", + "spi2_sck_px2", + "spi2_cs0_n_px3"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + aud_spi_di { + nvidia,pins = "spi2_miso_px1"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi1_mosi { + nvidia,pins = "spi1_mosi_px4"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pwr_chg_int { + nvidia,pins = "spi1_sck_px5"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + spi1_cs0_n { + nvidia,pins = "spi1_cs0_n_px6"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + audio_mclk_en { + nvidia,pins = "spi1_miso_px7"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* PORT Y */ + led_drv_en_trig { + nvidia,pins = "ulpi_clk_py0", + "ulpi_dir_py1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + mhl_3v3_en { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + peh_v_srio_1v8_en { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + aud_remo_tx { + nvidia,pins = "sdmmc1_dat3_py4"; + nvidia,function = "uarte"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + aud_remo_rx { + nvidia,pins = "sdmmc1_dat2_py5"; + nvidia,function = "uarte"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + nfc_irq { + nvidia,pins = "sdmmc1_dat1_py6"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + testpoint1 { + nvidia,pins = "sdmmc1_dat0_py7"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT Z */ + aud_remo_oe { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + testpoint2 { + nvidia,pins = "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + mdm_usb_uart_oe { + nvidia,pins = "lcd_sdin_pz2"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_wr_n { + nvidia,pins = "lcd_wr_n_pz3"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_sck { + nvidia,pins = "lcd_sck_pz4"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + sys_clk_req { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + sys_pwr_i2c { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + + /* PORT AA */ + bsp_emmc { + nvidia,pins = "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT BB */ + cam1_rst { + nvidia,pins = "pbb0"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + cam_i2c { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + per_flash_en { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + cam_vddio_1v8_en { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + cam1_vcm_pd { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + aud_remo_pres { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + front_cam_standby { + nvidia,pins = "pbb7"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PORT CC */ + cam_mclk { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + cam_sel { + nvidia,pins = "pcc1"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pwr_themp_alert_int { + nvidia,pins = "pcc2"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + bsp_emmc_resout { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + bsp_emmc_clk { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + aud_dock_out_en { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* PORT DD */ + /* PORT EE */ + clk3_out { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + raw_intr1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + clk1_req { + nvidia,pins = "clk1_req_pee2"; + nvidia,function = "dap"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + hdmi_cec { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + owr { + nvidia,pins = "owr"; + nvidia,function = "owr"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + }; + }; + uarta: serial@70006000 { status = "okay"; }; diff --git a/arch/arm/dts/tegra30-lg-p880.dts b/arch/arm/dts/tegra30-lg-p880.dts index 81d364310d..1d5ca1459b 100644 --- a/arch/arm/dts/tegra30-lg-p880.dts +++ b/arch/arm/dts/tegra30-lg-p880.dts @@ -11,6 +11,96 @@ mmc1 = &sdmmc3; /* uSD slot */ }; + pinmux@70000868 { + state_default: pinmux { + /* WLAN SDIO pinmux */ + host_wlan_wake { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* GNSS UART-B pinmux */ + uartb_rxd { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uartb_txd { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gps_reset { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* MicroSD pinmux */ + sdmmc3_clk { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3_data { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + microsd_detect { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* GPIO keys pinmux */ + volume_up { + nvidia,pins = "ulpi_data6_po7"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Sensors pinmux */ + current_alert_irq { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* AUDIO pinmux */ + sub_mic_ldo { + nvidia,pins = "gmi_cs7_n_pi6"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + }; + }; + sdmmc3: sdhci@78000400 { status = "okay"; bus-width = <4>; diff --git a/arch/arm/dts/tegra30-lg-p895.dts b/arch/arm/dts/tegra30-lg-p895.dts index 074205d5a9..43bb373a16 100644 --- a/arch/arm/dts/tegra30-lg-p895.dts +++ b/arch/arm/dts/tegra30-lg-p895.dts @@ -15,6 +15,99 @@ }; }; + pinmux@70000868 { + state_default: pinmux { + /* GNSS UART-B pinmux */ + uartb_cts_rxd { + nvidia,pins = "uart2_cts_n_pj5", + "uart2_rxd_pc3"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uartb_rts_txd { + nvidia,pins = "uart2_rts_n_pj6", + "uart2_txd_pc2"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gps_reset { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* GPIO keys pinmux */ + volume_up { + nvidia,pins = "gmi_cs7_n_pi6"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + memo_key { + nvidia,pins = "sdmmc3_dat1_pb6"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Sensors pinmux */ + current_alert_irq { + nvidia,pins = "spi1_cs0_n_px6"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Panel pinmux */ + panel_vdd { + nvidia,pins = "pbb0"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* AUDIO pinmux */ + sub_mic_ldo { + nvidia,pins = "gmi_dqs_pi2"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* Modem pinmux */ + usim_detect { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* GPIO power/drive control */ + drive_sdmmc4 { + nvidia,pins = "drive_gma", + "drive_gmb", + "drive_gmc", + "drive_gmd"; + nvidia,pull-down-strength = <9>; + nvidia,pull-up-strength = <9>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + }; + }; + }; + panel: panel { compatible = "hitachi,tx13d100vm0eaa"; diff --git a/arch/arm/dts/tegra30-lg-x3.dtsi b/arch/arm/dts/tegra30-lg-x3.dtsi index 01936b872e..30d6dcb654 100644 --- a/arch/arm/dts/tegra30-lg-x3.dtsi +++ b/arch/arm/dts/tegra30-lg-x3.dtsi @@ -37,6 +37,851 @@ }; }; + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* WLAN SDIO pinmux */ + sdmmc1_clk { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1_cmd { + nvidia,pins = "sdmmc1_cmd_pz1", + "sdmmc1_dat3_py4", + "sdmmc1_dat2_py5", + "sdmmc1_dat1_py6", + "sdmmc1_dat0_py7"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + wlan_reset { + nvidia,pins = "pv3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + wlan_host_wake { + nvidia,pins = "pu6"; + nvidia,function = "pwm3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* GNSS UART-B pinmux */ + gps_pwr_en { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gps_ldo_en { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gps_clk_ref { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* Bluetooth UART-C pinmux */ + uartc_cts_rxd { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uartc_rts_txd { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + bt_reset { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "dap"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + bt_dev_wake { + nvidia,pins = "kb_row11_ps3"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + bt_host_wake { + nvidia,pins = "kb_row12_ps4"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + bt_pcm_dap4 { + nvidia,pins = "dap4_fs_pp4", + "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* EMMC pinmux */ + sdmmc4_clk { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_data { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4_reset { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* I2C pinmux */ + gen1_i2c { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + }; + + gen2_i2c { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + }; + + cam_i2c { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + }; + + ddc_i2c { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + }; + + pwr_i2c { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + }; + + mhl_i2c { + nvidia,pins = "kb_col6_pq6", + "kb_col7_pq7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* GPIO keys pinmux */ + power_key { + nvidia,pins = "gmi_wp_n_pc7"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + volume_down { + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "spi3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Sensors pinmux */ + sen_vdd { + nvidia,pins = "spi1_miso_px7"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + proxi_vdd { + nvidia,pins = "spi2_miso_px1"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + sen_vio { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + nct_irq { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + bat_irq { + nvidia,pins = "kb_row8_ps0"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + charger_irq { + nvidia,pins = "gmi_cs1_n_pj2"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + mpu_irq { + nvidia,pins = "gmi_ad12_ph4"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + compass_irq { + nvidia,pins = "gmi_ad13_ph5"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + light_irq { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* LED pinmux */ + backlight_en { + nvidia,pins = "lcd_dc0_pn6"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + flash_led_en { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + keypad_led { + nvidia,pins = "kb_row2_pr2", + "kb_row3_pr3"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* NFC pinmux */ + nfc_irq { + nvidia,pins = "spi2_cs1_n_pw2"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + nfc_ven { + nvidia,pins = "spi1_sck_px5"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + nfc_firm { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* DC pinmux */ + lcd_pwr { + nvidia,pins = "lcd_pwr0_pb2", + "lcd_pwr1_pc1"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + lcd_wr_n { + nvidia,pins = "lcd_wr_n_pz3"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_id { + nvidia,pins = "lcd_m1_pw1"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + lcd_pclk { + nvidia,pins = "lcd_pclk_pb3", + "lcd_de_pj1", + "lcd_hsync_pj3", + "lcd_vsync_pj4"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + lcd_rgb_blue { + nvidia,pins = "lcd_d0_pe0", + "lcd_d1_pe1", + "lcd_d2_pe2", + "lcd_d3_pe3", + "lcd_d4_pe4", + "lcd_d5_pe5", + "lcd_d18_pm2", + "lcd_d19_pm3"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_rgb_green { + nvidia,pins = "lcd_d6_pe6", + "lcd_d7_pe7", + "lcd_d8_pf0", + "lcd_d9_pf1", + "lcd_d10_pf2", + "lcd_d11_pf3", + "lcd_d20_pm4", + "lcd_d21_pm5"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_rgb_red { + nvidia,pins = "lcd_d12_pf4", + "lcd_d13_pf5", + "lcd_d14_pf6", + "lcd_d15_pf7", + "lcd_d16_pm0", + "lcd_d17_pm1", + "lcd_d22_pm6", + "lcd_d23_pm7"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Bridge pinmux */ + bridge_reset { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "spi3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + rgb_ic_en { + nvidia,pins = "gmi_a18_pb1"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + bridge_clk { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + rgb_bridge { + nvidia,pins = "lcd_sdin_pz2", + "lcd_sdout_pn5", + "lcd_cs0_n_pn4", + "lcd_sck_pz4"; + nvidia,function = "spi5"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Panel pinmux */ + panel_reset { + nvidia,pins = "lcd_cs1_n_pw0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + panel_vio { + nvidia,pins = "ulpi_clk_py0"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* Touchscreen pinmux */ + touch_vdd { + nvidia,pins = "kb_col1_pq1"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + touch_vio { + nvidia,pins = "spi1_mosi_px4"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + touch_int_n { + nvidia,pins = "kb_col3_pq3"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + touch_rst_n { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "spi3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + touch_maker_id { + nvidia,pins = "kb_col2_pq2"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* MHL pinmux */ + mhl_vio { + nvidia,pins = "pv2"; + nvidia,function = "owr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + mhl_rst_n { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + mhl_int { + nvidia,pins = "crt_vsync_pv7"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + mhl_sel { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + hdmi_hpd { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* AUDIO pinmux */ + hp_detect { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + hp_hook { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ear_mic_en { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + audio_irq { + nvidia,pins = "spi2_cs2_n_pw3"; + nvidia,function = "spi3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + audio_mclk { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap_i2s0 { + nvidia,pins = "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_dout_pn2", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap_i2s1 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* MUIC pinmux */ + muic_irq { + nvidia,pins = "gmi_cs0_n_pj0"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + muic_dp2t { + nvidia,pins = "pcc2"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + muic_usif { + nvidia,pins = "ulpi_stp_py3"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ifx_usb_vbus_en { + nvidia,pins = "kb_row4_pr4"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pcb_rev { + nvidia,pins = "gmi_wait_pi7", + "gmi_rst_n_pi4"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + jtag_rtck { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* Camera pinmux */ + cam_mclk { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + cam_pmic_en { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + front_cam_rst { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + front_cam_vio { + nvidia,pins = "ulpi_nxt_py2"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + rear_cam_rst { + nvidia,pins = "gmi_cs3_n_pk4"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + rear_cam_eprom_pr { + nvidia,pins = "gmi_cs2_n_pk3"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + rear_cam_vcm_pwdn { + nvidia,pins = "kb_row1_pr1"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Haptic pinmux */ + haptic_en { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + haptic_osc { + nvidia,pins = "gmi_ad11_ph3"; + nvidia,function = "pwm3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* Modem pinmux */ + cp2ap_ack1_host_active { + nvidia,pins = "pu5"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + cp2ap_ack2_host_wakeup { + nvidia,pins = "pv0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ap2cp_ack2_suspend_req { + nvidia,pins = "kb_row14_ps6"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ap2cp_ack1_slave_wakeup { + nvidia,pins = "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + cp_kkp { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + cp_crash_irq { + nvidia,pins = "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + ap2cp_uarta_tx_ipc { + nvidia,pins = "pu0"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ap2cp_uarta_rx_ipc { + nvidia,pins = "pu1"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + fota_ap_cts_cp_rts { + nvidia,pins = "pu2"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + fota_ap_rts_cp_cts { + nvidia,pins = "pu3"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + modem_enable { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "hsi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + modem_reset { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + dap_i2s2 { + nvidia,pins = "dap3_fs_pp0", + "dap3_din_pp1", + "dap3_dout_pp2", + "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* GPIO power/drive control */ + drive_i2c { + nvidia,pins = "drive_dbg", + "drive_at5", + "drive_gme", + "drive_ddc", + "drive_ao1"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + + drive_uart3 { + nvidia,pins = "drive_uart3"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + + drive_gmi { + nvidia,pins = "drive_at3"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + }; + }; + uartd: serial@70006300 { status = "okay"; }; diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h index 2359e142fb..04910d594e 100644 --- a/arch/arm/include/asm/arch-tegra/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra/clk_rst.h @@ -174,8 +174,7 @@ struct clk_rst_ctlr { uint crc_audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4_0, 0x4B0 */ uint crc_audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4B4 */ - uint crc_plld2_base; /* _PLLD2_BASE_0, 0x4B8 */ - uint crc_plld2_misc; /* _PLLD2_MISC_0, 0x4BC */ + struct clk_pll_simple plld2; /* _PLLD2_BASE_0, 0x4B8 */ uint crc_utmip_pll_cfg3; /* _UTMIP_PLL_CFG3_0, 0x4C0 */ uint crc_pllrefe_base; /* _PLLREFE_BASE_0, 0x4C4 */ uint crc_pllrefe_misc; /* _PLLREFE_MISC_0, 0x4C8 */ diff --git a/arch/arm/include/asm/arch-tegra114/clock-tables.h b/arch/arm/include/asm/arch-tegra114/clock-tables.h index 9b95b339e2..95fadd0c59 100644 --- a/arch/arm/include/asm/arch-tegra114/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra114/clock-tables.h @@ -23,6 +23,7 @@ enum clock_id { CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, CLOCK_ID_EPCI, CLOCK_ID_SFROM32KHZ, + CLOCK_ID_DISPLAY2, /* These are the base clocks (inputs to the Tegra SOC) */ CLOCK_ID_32KHZ, @@ -30,7 +31,6 @@ enum clock_id { CLOCK_ID_CLK_M, CLOCK_ID_COUNT, /* number of PLLs */ - CLOCK_ID_DISPLAY2, /* placeholder */ CLOCK_ID_NONE = -1, }; diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h b/arch/arm/include/asm/arch-tegra114/pinmux.h index 414b22e201..63b3684931 100644 --- a/arch/arm/include/asm/arch-tegra114/pinmux.h +++ b/arch/arm/include/asm/arch-tegra114/pinmux.h @@ -312,6 +312,309 @@ enum pmux_func { PMUX_FUNC_COUNT, }; +static const char * const tegra_pinctrl_to_pingrp[] = { + [PMUX_PINGRP_ULPI_DATA0_PO1] = "ulpi_data0_po1", + [PMUX_PINGRP_ULPI_DATA1_PO2] = "ulpi_data1_po2", + [PMUX_PINGRP_ULPI_DATA2_PO3] = "ulpi_data2_po3", + [PMUX_PINGRP_ULPI_DATA3_PO4] = "ulpi_data3_po4", + [PMUX_PINGRP_ULPI_DATA4_PO5] = "ulpi_data4_po5", + [PMUX_PINGRP_ULPI_DATA5_PO6] = "ulpi_data5_po6", + [PMUX_PINGRP_ULPI_DATA6_PO7] = "ulpi_data6_po7", + [PMUX_PINGRP_ULPI_DATA7_PO0] = "ulpi_data7_po0", + [PMUX_PINGRP_ULPI_CLK_PY0] = "ulpi_clk_py0", + [PMUX_PINGRP_ULPI_DIR_PY1] = "ulpi_dir_py1", + [PMUX_PINGRP_ULPI_NXT_PY2] = "ulpi_nxt_py2", + [PMUX_PINGRP_ULPI_STP_PY3] = "ulpi_stp_py3", + [PMUX_PINGRP_DAP3_FS_PP0] = "dap3_fs_pp0", + [PMUX_PINGRP_DAP3_DIN_PP1] = "dap3_din_pp1", + [PMUX_PINGRP_DAP3_DOUT_PP2] = "dap3_dout_pp2", + [PMUX_PINGRP_DAP3_SCLK_PP3] = "dap3_sclk_pp3", + [PMUX_PINGRP_PV0] = "pv0", + [PMUX_PINGRP_PV1] = "pv1", + [PMUX_PINGRP_SDMMC1_CLK_PZ0] = "sdmmc1_clk_pz0", + [PMUX_PINGRP_SDMMC1_CMD_PZ1] = "sdmmc1_cmd_pz1", + [PMUX_PINGRP_SDMMC1_DAT3_PY4] = "sdmmc1_dat3_py4", + [PMUX_PINGRP_SDMMC1_DAT2_PY5] = "sdmmc1_dat2_py5", + [PMUX_PINGRP_SDMMC1_DAT1_PY6] = "sdmmc1_dat1_py6", + [PMUX_PINGRP_SDMMC1_DAT0_PY7] = "sdmmc1_dat0_py7", + [PMUX_PINGRP_CLK2_OUT_PW5] = "clk2_out_pw5", + [PMUX_PINGRP_CLK2_REQ_PCC5] = "clk2_req_pcc5", + [PMUX_PINGRP_HDMI_INT_PN7] = "hdmi_int_pn7", + [PMUX_PINGRP_DDC_SCL_PV4] = "ddc_scl_pv4", + [PMUX_PINGRP_DDC_SDA_PV5] = "ddc_sda_pv5", + [PMUX_PINGRP_UART2_RXD_PC3] = "uart2_rxd_pc3", + [PMUX_PINGRP_UART2_TXD_PC2] = "uart2_txd_pc2", + [PMUX_PINGRP_UART2_RTS_N_PJ6] = "uart2_rts_n_pj6", + [PMUX_PINGRP_UART2_CTS_N_PJ5] = "uart2_cts_n_pj5", + [PMUX_PINGRP_UART3_TXD_PW6] = "uart3_txd_pw6", + [PMUX_PINGRP_UART3_RXD_PW7] = "uart3_rxd_pw7", + [PMUX_PINGRP_UART3_CTS_N_PA1] = "uart3_cts_n_pa1", + [PMUX_PINGRP_UART3_RTS_N_PC0] = "uart3_rts_n_pc0", + [PMUX_PINGRP_PU0] = "pu0", + [PMUX_PINGRP_PU1] = "pu1", + [PMUX_PINGRP_PU2] = "pu2", + [PMUX_PINGRP_PU3] = "pu3", + [PMUX_PINGRP_PU4] = "pu4", + [PMUX_PINGRP_PU5] = "pu5", + [PMUX_PINGRP_PU6] = "pu6", + [PMUX_PINGRP_GEN1_I2C_SDA_PC5] = "gen1_i2c_sda_pc5", + [PMUX_PINGRP_GEN1_I2C_SCL_PC4] = "gen1_i2c_scl_pc4", + [PMUX_PINGRP_DAP4_FS_PP4] = "dap4_fs_pp4", + [PMUX_PINGRP_DAP4_DIN_PP5] = "dap4_din_pp5", + [PMUX_PINGRP_DAP4_DOUT_PP6] = "dap4_dout_pp6", + [PMUX_PINGRP_DAP4_SCLK_PP7] = "dap4_sclk_pp7", + [PMUX_PINGRP_CLK3_OUT_PEE0] = "clk3_out_pee0", + [PMUX_PINGRP_CLK3_REQ_PEE1] = "clk3_req_pee1", + [PMUX_PINGRP_GMI_WP_N_PC7] = "gmi_wp_n_pc7", + [PMUX_PINGRP_GMI_IORDY_PI5] = "gmi_iordy_pi5", + [PMUX_PINGRP_GMI_WAIT_PI7] = "gmi_wait_pi7", + [PMUX_PINGRP_GMI_ADV_N_PK0] = "gmi_adv_n_pk0", + [PMUX_PINGRP_GMI_CLK_PK1] = "gmi_clk_pk1", + [PMUX_PINGRP_GMI_CS0_N_PJ0] = "gmi_cs0_n_pj0", + [PMUX_PINGRP_GMI_CS1_N_PJ2] = "gmi_cs1_n_pj2", + [PMUX_PINGRP_GMI_CS2_N_PK3] = "gmi_cs2_n_pk3", + [PMUX_PINGRP_GMI_CS3_N_PK4] = "gmi_cs3_n_pk4", + [PMUX_PINGRP_GMI_CS4_N_PK2] = "gmi_cs4_n_pk2", + [PMUX_PINGRP_GMI_CS6_N_PI3] = "gmi_cs6_n_pi3", + [PMUX_PINGRP_GMI_CS7_N_PI6] = "gmi_cs7_n_pi6", + [PMUX_PINGRP_GMI_AD0_PG0] = "gmi_ad0_pg0", + [PMUX_PINGRP_GMI_AD1_PG1] = "gmi_ad1_pg1", + [PMUX_PINGRP_GMI_AD2_PG2] = "gmi_ad2_pg2", + [PMUX_PINGRP_GMI_AD3_PG3] = "gmi_ad3_pg3", + [PMUX_PINGRP_GMI_AD4_PG4] = "gmi_ad4_pg4", + [PMUX_PINGRP_GMI_AD5_PG5] = "gmi_ad5_pg5", + [PMUX_PINGRP_GMI_AD6_PG6] = "gmi_ad6_pg6", + [PMUX_PINGRP_GMI_AD7_PG7] = "gmi_ad7_pg7", + [PMUX_PINGRP_GMI_AD8_PH0] = "gmi_ad8_ph0", + [PMUX_PINGRP_GMI_AD9_PH1] = "gmi_ad9_ph1", + [PMUX_PINGRP_GMI_AD10_PH2] = "gmi_ad10_ph2", + [PMUX_PINGRP_GMI_AD11_PH3] = "gmi_ad11_ph3", + [PMUX_PINGRP_GMI_AD12_PH4] = "gmi_ad12_ph4", + [PMUX_PINGRP_GMI_AD13_PH5] = "gmi_ad13_ph5", + [PMUX_PINGRP_GMI_AD14_PH6] = "gmi_ad14_ph6", + [PMUX_PINGRP_GMI_AD15_PH7] = "gmi_ad15_ph7", + [PMUX_PINGRP_GMI_A16_PJ7] = "gmi_a16_pj7", + [PMUX_PINGRP_GMI_A17_PB0] = "gmi_a17_pb0", + [PMUX_PINGRP_GMI_A18_PB1] = "gmi_a18_pb1", + [PMUX_PINGRP_GMI_A19_PK7] = "gmi_a19_pk7", + [PMUX_PINGRP_GMI_WR_N_PI0] = "gmi_wr_n_pi0", + [PMUX_PINGRP_GMI_OE_N_PI1] = "gmi_oe_n_pi1", + [PMUX_PINGRP_GMI_DQS_P_PJ3] = "gmi_dqs_p_pj3", + [PMUX_PINGRP_GMI_RST_N_PI4] = "gmi_rst_n_pi4", + [PMUX_PINGRP_GEN2_I2C_SCL_PT5] = "gen2_i2c_scl_pt5", + [PMUX_PINGRP_GEN2_I2C_SDA_PT6] = "gen2_i2c_sda_pt6", + [PMUX_PINGRP_SDMMC4_CLK_PCC4] = "sdmmc4_clk_pcc4", + [PMUX_PINGRP_SDMMC4_CMD_PT7] = "sdmmc4_cmd_pt7", + [PMUX_PINGRP_SDMMC4_DAT0_PAA0] = "sdmmc4_dat0_paa0", + [PMUX_PINGRP_SDMMC4_DAT1_PAA1] = "sdmmc4_dat1_paa1", + [PMUX_PINGRP_SDMMC4_DAT2_PAA2] = "sdmmc4_dat2_paa2", + [PMUX_PINGRP_SDMMC4_DAT3_PAA3] = "sdmmc4_dat3_paa3", + [PMUX_PINGRP_SDMMC4_DAT4_PAA4] = "sdmmc4_dat4_paa4", + [PMUX_PINGRP_SDMMC4_DAT5_PAA5] = "sdmmc4_dat5_paa5", + [PMUX_PINGRP_SDMMC4_DAT6_PAA6] = "sdmmc4_dat6_paa6", + [PMUX_PINGRP_SDMMC4_DAT7_PAA7] = "sdmmc4_dat7_paa7", + [PMUX_PINGRP_CAM_MCLK_PCC0] = "cam_mclk_pcc0", + [PMUX_PINGRP_PCC1] = "pcc1", + [PMUX_PINGRP_PBB0] = "pbb0", + [PMUX_PINGRP_CAM_I2C_SCL_PBB1] = "cam_i2c_scl_pbb1", + [PMUX_PINGRP_CAM_I2C_SDA_PBB2] = "cam_i2c_sda_pbb2", + [PMUX_PINGRP_PBB3] = "pbb3", + [PMUX_PINGRP_PBB4] = "pbb4", + [PMUX_PINGRP_PBB5] = "pbb5", + [PMUX_PINGRP_PBB6] = "pbb6", + [PMUX_PINGRP_PBB7] = "pbb7", + [PMUX_PINGRP_PCC2] = "pcc2", + [PMUX_PINGRP_JTAG_RTCK] = "jtag_rtck", + [PMUX_PINGRP_PWR_I2C_SCL_PZ6] = "pwr_i2c_scl_pz6", + [PMUX_PINGRP_PWR_I2C_SDA_PZ7] = "pwr_i2c_sda_pz7", + [PMUX_PINGRP_KB_ROW0_PR0] = "kb_row0_pr0", + [PMUX_PINGRP_KB_ROW1_PR1] = "kb_row1_pr1", + [PMUX_PINGRP_KB_ROW2_PR2] = "kb_row2_pr2", + [PMUX_PINGRP_KB_ROW3_PR3] = "kb_row3_pr3", + [PMUX_PINGRP_KB_ROW4_PR4] = "kb_row4_pr4", + [PMUX_PINGRP_KB_ROW5_PR5] = "kb_row5_pr5", + [PMUX_PINGRP_KB_ROW6_PR6] = "kb_row6_pr6", + [PMUX_PINGRP_KB_ROW7_PR7] = "kb_row7_pr7", + [PMUX_PINGRP_KB_ROW8_PS0] = "kb_row8_ps0", + [PMUX_PINGRP_KB_ROW9_PS1] = "kb_row9_ps1", + [PMUX_PINGRP_KB_ROW10_PS2] = "kb_row10_ps2", + [PMUX_PINGRP_KB_COL0_PQ0] = "kb_col0_pq0", + [PMUX_PINGRP_KB_COL1_PQ1] = "kb_col1_pq1", + [PMUX_PINGRP_KB_COL2_PQ2] = "kb_col2_pq2", + [PMUX_PINGRP_KB_COL3_PQ3] = "kb_col3_pq3", + [PMUX_PINGRP_KB_COL4_PQ4] = "kb_col4_pq4", + [PMUX_PINGRP_KB_COL5_PQ5] = "kb_col5_pq5", + [PMUX_PINGRP_KB_COL6_PQ6] = "kb_col6_pq6", + [PMUX_PINGRP_KB_COL7_PQ7] = "kb_col7_pq7", + [PMUX_PINGRP_CLK_32K_OUT_PA0] = "clk_32k_out_pa0", + [PMUX_PINGRP_SYS_CLK_REQ_PZ5] = "sys_clk_req_pz5", + [PMUX_PINGRP_CORE_PWR_REQ] = "core_pwr_req", + [PMUX_PINGRP_CPU_PWR_REQ] = "cpu_pwr_req", + [PMUX_PINGRP_PWR_INT_N] = "pwr_int_n", + [PMUX_PINGRP_CLK_32K_IN] = "clk_32k_in", + [PMUX_PINGRP_OWR] = "owr", + [PMUX_PINGRP_DAP1_FS_PN0] = "dap1_fs_pn0", + [PMUX_PINGRP_DAP1_DIN_PN1] = "dap1_din_pn1", + [PMUX_PINGRP_DAP1_DOUT_PN2] = "dap1_dout_pn2", + [PMUX_PINGRP_DAP1_SCLK_PN3] = "dap1_sclk_pn3", + [PMUX_PINGRP_CLK1_REQ_PEE2] = "clk1_req_pee2", + [PMUX_PINGRP_CLK1_OUT_PW4] = "clk1_out_pw4", + [PMUX_PINGRP_SPDIF_IN_PK6] = "spdif_in_pk6", + [PMUX_PINGRP_SPDIF_OUT_PK5] = "spdif_out_pk5", + [PMUX_PINGRP_DAP2_FS_PA2] = "dap2_fs_pa2", + [PMUX_PINGRP_DAP2_DIN_PA4] = "dap2_din_pa4", + [PMUX_PINGRP_DAP2_DOUT_PA5] = "dap2_dout_pa5", + [PMUX_PINGRP_DAP2_SCLK_PA3] = "dap2_sclk_pa3", + [PMUX_PINGRP_DVFS_PWM_PX0] = "dvfs_pwm_px0", + [PMUX_PINGRP_GPIO_X1_AUD_PX1] = "gpio_x1_aud_px1", + [PMUX_PINGRP_GPIO_X3_AUD_PX3] = "gpio_x3_aud_px3", + [PMUX_PINGRP_DVFS_CLK_PX2] = "dvfs_clk_px2", + [PMUX_PINGRP_GPIO_X4_AUD_PX4] = "gpio_x4_aud_px4", + [PMUX_PINGRP_GPIO_X5_AUD_PX5] = "gpio_x5_aud_px5", + [PMUX_PINGRP_GPIO_X6_AUD_PX6] = "gpio_x6_aud_px6", + [PMUX_PINGRP_GPIO_X7_AUD_PX7] = "gpio_x7_aud_px7", + [PMUX_PINGRP_SDMMC3_CLK_PA6] = "sdmmc3_clk_pa6", + [PMUX_PINGRP_SDMMC3_CMD_PA7] = "sdmmc3_cmd_pa7", + [PMUX_PINGRP_SDMMC3_DAT0_PB7] = "sdmmc3_dat0_pb7", + [PMUX_PINGRP_SDMMC3_DAT1_PB6] = "sdmmc3_dat1_pb6", + [PMUX_PINGRP_SDMMC3_DAT2_PB5] = "sdmmc3_dat2_pb5", + [PMUX_PINGRP_SDMMC3_DAT3_PB4] = "sdmmc3_dat3_pb4", + [PMUX_PINGRP_HDMI_CEC_PEE3] = "hdmi_cec_pee3", + [PMUX_PINGRP_SDMMC1_WP_N_PV3] = "sdmmc1_wp_n_pv3", + [PMUX_PINGRP_SDMMC3_CD_N_PV2] = "sdmmc3_cd_n_pv2", + [PMUX_PINGRP_GPIO_W2_AUD_PW2] = "gpio_w2_aud_pw2", + [PMUX_PINGRP_GPIO_W3_AUD_PW3] = "gpio_w3_aud_pw3", + [PMUX_PINGRP_USB_VBUS_EN0_PN4] = "usb_vbus_en0_pn4", + [PMUX_PINGRP_USB_VBUS_EN1_PN5] = "usb_vbus_en1_pn5", + [PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5] = "sdmmc3_clk_lb_in_pee5", + [PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4] = "sdmmc3_clk_lb_out_pee4", + [PMUX_PINGRP_GMI_CLK_LB] = "gmi_clk_lb", + [PMUX_PINGRP_RESET_OUT_N] = "reset_out_n", +}; + +static const char * const tegra_pinctrl_to_drvgrp[] = { + [PMUX_DRVGRP_AO1] = "drive_ao1", + [PMUX_DRVGRP_AO2] = "drive_ao2", + [PMUX_DRVGRP_AT1] = "drive_at1", + [PMUX_DRVGRP_AT2] = "drive_at2", + [PMUX_DRVGRP_AT3] = "drive_at3", + [PMUX_DRVGRP_AT4] = "drive_at4", + [PMUX_DRVGRP_AT5] = "drive_at5", + [PMUX_DRVGRP_CDEV1] = "drive_cdev1", + [PMUX_DRVGRP_CDEV2] = "drive_cdev2", + [PMUX_DRVGRP_DAP1] = "drive_dap1", + [PMUX_DRVGRP_DAP2] = "drive_dap2", + [PMUX_DRVGRP_DAP3] = "drive_dap3", + [PMUX_DRVGRP_DAP4] = "drive_dap4", + [PMUX_DRVGRP_DBG] = "drive_dbg", + [PMUX_DRVGRP_SDIO3] = "drive_sdio3", + [PMUX_DRVGRP_SPI] = "drive_spi", + [PMUX_DRVGRP_UAA] = "drive_uaa", + [PMUX_DRVGRP_UAB] = "drive_uab", + [PMUX_DRVGRP_UART2] = "drive_uart2", + [PMUX_DRVGRP_UART3] = "drive_uart3", + [PMUX_DRVGRP_SDIO1] = "drive_sdio1", + [PMUX_DRVGRP_DDC] = "drive_ddc", + [PMUX_DRVGRP_GMA] = "drive_gma", + [PMUX_DRVGRP_GME] = "drive_gme", + [PMUX_DRVGRP_GMF] = "drive_gmf", + [PMUX_DRVGRP_GMG] = "drive_gmg", + [PMUX_DRVGRP_GMH] = "drive_gmh", + [PMUX_DRVGRP_OWR] = "drive_owr", + [PMUX_DRVGRP_UDA] = "drive_uda", + [PMUX_DRVGRP_DEV3] = "drive_dev3", + [PMUX_DRVGRP_CEC] = "drive_cec", + [PMUX_DRVGRP_AT6] = "drive_at6", + [PMUX_DRVGRP_DAP5] = "drive_dap5", + [PMUX_DRVGRP_USB_VBUS_EN] = "drive_usb_vbus_en", + [PMUX_DRVGRP_AO3] = "drive_ao3", + [PMUX_DRVGRP_HV0] = "drive_hv0", + [PMUX_DRVGRP_SDIO4] = "drive_sdio4", + [PMUX_DRVGRP_AO0] = "drive_ao0", +}; + +static const char * const tegra_pinctrl_to_func[] = { + [PMUX_FUNC_DEFAULT] = "default", + [PMUX_FUNC_BLINK] = "blink", + [PMUX_FUNC_CEC] = "cec", + [PMUX_FUNC_CLDVFS] = "cldvfs", + [PMUX_FUNC_CLK] = "clk", + [PMUX_FUNC_CLK12] = "clk12", + [PMUX_FUNC_CPU] = "cpu", + [PMUX_FUNC_DAP] = "dap", + [PMUX_FUNC_DAP1] = "dap1", + [PMUX_FUNC_DAP2] = "dap2", + [PMUX_FUNC_DEV3] = "dev3", + [PMUX_FUNC_DISPLAYA] = "displaya", + [PMUX_FUNC_DISPLAYA_ALT] = "displaya_alt", + [PMUX_FUNC_DISPLAYB] = "displayb", + [PMUX_FUNC_DTV] = "dtv", + [PMUX_FUNC_EMC_DLL] = "emc_dll", + [PMUX_FUNC_EXTPERIPH1] = "extperiph1", + [PMUX_FUNC_EXTPERIPH2] = "extperiph2", + [PMUX_FUNC_EXTPERIPH3] = "extperiph3", + [PMUX_FUNC_GMI] = "gmi", + [PMUX_FUNC_GMI_ALT] = "gmi_alt", + [PMUX_FUNC_HDA] = "hda", + [PMUX_FUNC_HSI] = "hsi", + [PMUX_FUNC_I2C1] = "i2c1", + [PMUX_FUNC_I2C2] = "i2c2", + [PMUX_FUNC_I2C3] = "i2c3", + [PMUX_FUNC_I2C4] = "i2c4", + [PMUX_FUNC_I2CPWR] = "i2cpwr", + [PMUX_FUNC_I2S0] = "i2s0", + [PMUX_FUNC_I2S1] = "i2s1", + [PMUX_FUNC_I2S2] = "i2s2", + [PMUX_FUNC_I2S3] = "i2s3", + [PMUX_FUNC_I2S4] = "i2s4", + [PMUX_FUNC_IRDA] = "irda", + [PMUX_FUNC_KBC] = "kbc", + [PMUX_FUNC_NAND] = "nand", + [PMUX_FUNC_NAND_ALT] = "nand_alt", + [PMUX_FUNC_OWR] = "owr", + [PMUX_FUNC_PMI] = "pmi", + [PMUX_FUNC_PWM0] = "pwm0", + [PMUX_FUNC_PWM1] = "pwm1", + [PMUX_FUNC_PWM2] = "pwm2", + [PMUX_FUNC_PWM3] = "pwm3", + [PMUX_FUNC_PWRON] = "pwron", + [PMUX_FUNC_RESET_OUT_N] = "reset_out_n", + [PMUX_FUNC_RTCK] = "rtck", + [PMUX_FUNC_SDMMC1] = "sdmmc1", + [PMUX_FUNC_SDMMC2] = "sdmmc2", + [PMUX_FUNC_SDMMC3] = "sdmmc3", + [PMUX_FUNC_SDMMC4] = "sdmmc4", + [PMUX_FUNC_SOC] = "soc", + [PMUX_FUNC_SPDIF] = "spdif", + [PMUX_FUNC_SPI1] = "spi1", + [PMUX_FUNC_SPI2] = "spi2", + [PMUX_FUNC_SPI3] = "spi3", + [PMUX_FUNC_SPI4] = "spi4", + [PMUX_FUNC_SPI5] = "spi5", + [PMUX_FUNC_SPI6] = "spi6", + [PMUX_FUNC_SYSCLK] = "sysclk", + [PMUX_FUNC_TRACE] = "trace", + [PMUX_FUNC_UARTA] = "uarta", + [PMUX_FUNC_UARTB] = "uartb", + [PMUX_FUNC_UARTC] = "uartc", + [PMUX_FUNC_UARTD] = "uartd", + [PMUX_FUNC_ULPI] = "ulpi", + [PMUX_FUNC_USB] = "usb", + [PMUX_FUNC_VGP1] = "vgp1", + [PMUX_FUNC_VGP2] = "vgp2", + [PMUX_FUNC_VGP3] = "vgp3", + [PMUX_FUNC_VGP4] = "vgp4", + [PMUX_FUNC_VGP5] = "vgp5", + [PMUX_FUNC_VGP6] = "vgp6", + [PMUX_FUNC_VI] = "vi", + [PMUX_FUNC_VI_ALT1] = "vi_alt1", + [PMUX_FUNC_VI_ALT3] = "vi_alt3", + [PMUX_FUNC_RSVD1] = "rsvd1", + [PMUX_FUNC_RSVD2] = "rsvd2", + [PMUX_FUNC_RSVD3] = "rsvd3", + [PMUX_FUNC_RSVD4] = "rsvd4", +}; + #define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868 #define TEGRA_PMX_SOC_HAS_IO_CLAMPING #define TEGRA_PMX_SOC_HAS_DRVGRPS diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h index 4c593aae7c..3aba17d21e 100644 --- a/arch/arm/include/asm/arch-tegra124/pinmux.h +++ b/arch/arm/include/asm/arch-tegra124/pinmux.h @@ -341,6 +341,333 @@ enum pmux_func { PMUX_FUNC_COUNT, }; +static const char * const tegra_pinctrl_to_pingrp[] = { + [PMUX_PINGRP_ULPI_DATA0_PO1] = "ulpi_data0_po1", + [PMUX_PINGRP_ULPI_DATA1_PO2] = "ulpi_data1_po2", + [PMUX_PINGRP_ULPI_DATA2_PO3] = "ulpi_data2_po3", + [PMUX_PINGRP_ULPI_DATA3_PO4] = "ulpi_data3_po4", + [PMUX_PINGRP_ULPI_DATA4_PO5] = "ulpi_data4_po5", + [PMUX_PINGRP_ULPI_DATA5_PO6] = "ulpi_data5_po6", + [PMUX_PINGRP_ULPI_DATA6_PO7] = "ulpi_data6_po7", + [PMUX_PINGRP_ULPI_DATA7_PO0] = "ulpi_data7_po0", + [PMUX_PINGRP_ULPI_CLK_PY0] = "ulpi_clk_py0", + [PMUX_PINGRP_ULPI_DIR_PY1] = "ulpi_dir_py1", + [PMUX_PINGRP_ULPI_NXT_PY2] = "ulpi_nxt_py2", + [PMUX_PINGRP_ULPI_STP_PY3] = "ulpi_stp_py3", + [PMUX_PINGRP_DAP3_FS_PP0] = "dap3_fs_pp0", + [PMUX_PINGRP_DAP3_DIN_PP1] = "dap3_din_pp1", + [PMUX_PINGRP_DAP3_DOUT_PP2] = "dap3_dout_pp2", + [PMUX_PINGRP_DAP3_SCLK_PP3] = "dap3_sclk_pp3", + [PMUX_PINGRP_PV0] = "pv0", + [PMUX_PINGRP_PV1] = "pv1", + [PMUX_PINGRP_SDMMC1_CLK_PZ0] = "sdmmc1_clk_pz0", + [PMUX_PINGRP_SDMMC1_CMD_PZ1] = "sdmmc1_cmd_pz1", + [PMUX_PINGRP_SDMMC1_DAT3_PY4] = "sdmmc1_dat3_py4", + [PMUX_PINGRP_SDMMC1_DAT2_PY5] = "sdmmc1_dat2_py5", + [PMUX_PINGRP_SDMMC1_DAT1_PY6] = "sdmmc1_dat1_py6", + [PMUX_PINGRP_SDMMC1_DAT0_PY7] = "sdmmc1_dat0_py7", + [PMUX_PINGRP_CLK2_OUT_PW5] = "clk2_out_pw5", + [PMUX_PINGRP_CLK2_REQ_PCC5] = "clk2_req_pcc5", + [PMUX_PINGRP_HDMI_INT_PN7] = "hdmi_int_pn7", + [PMUX_PINGRP_DDC_SCL_PV4] = "ddc_scl_pv4", + [PMUX_PINGRP_DDC_SDA_PV5] = "ddc_sda_pv5", + [PMUX_PINGRP_UART2_RXD_PC3] = "uart2_rxd_pc3", + [PMUX_PINGRP_UART2_TXD_PC2] = "uart2_txd_pc2", + [PMUX_PINGRP_UART2_RTS_N_PJ6] = "uart2_rts_n_pj6", + [PMUX_PINGRP_UART2_CTS_N_PJ5] = "uart2_cts_n_pj5", + [PMUX_PINGRP_UART3_TXD_PW6] = "uart3_txd_pw6", + [PMUX_PINGRP_UART3_RXD_PW7] = "uart3_rxd_pw7", + [PMUX_PINGRP_UART3_CTS_N_PA1] = "uart3_cts_n_pa1", + [PMUX_PINGRP_UART3_RTS_N_PC0] = "uart3_rts_n_pc0", + [PMUX_PINGRP_PU0] = "pu0", + [PMUX_PINGRP_PU1] = "pu1", + [PMUX_PINGRP_PU2] = "pu2", + [PMUX_PINGRP_PU3] = "pu3", + [PMUX_PINGRP_PU4] = "pu4", + [PMUX_PINGRP_PU5] = "pu5", + [PMUX_PINGRP_PU6] = "pu6", + [PMUX_PINGRP_GEN1_I2C_SDA_PC5] = "gen1_i2c_sda_pc5", + [PMUX_PINGRP_GEN1_I2C_SCL_PC4] = "gen1_i2c_scl_pc4", + [PMUX_PINGRP_DAP4_FS_PP4] = "dap4_fs_pp4", + [PMUX_PINGRP_DAP4_DIN_PP5] = "dap4_din_pp5", + [PMUX_PINGRP_DAP4_DOUT_PP6] = "dap4_dout_pp6", + [PMUX_PINGRP_DAP4_SCLK_PP7] = "dap4_sclk_pp7", + [PMUX_PINGRP_CLK3_OUT_PEE0] = "clk3_out_pee0", + [PMUX_PINGRP_CLK3_REQ_PEE1] = "clk3_req_pee1", + [PMUX_PINGRP_PC7] = "pc7", + [PMUX_PINGRP_PI5] = "pi5", + [PMUX_PINGRP_PI7] = "pi7", + [PMUX_PINGRP_PK0] = "pk0", + [PMUX_PINGRP_PK1] = "pk1", + [PMUX_PINGRP_PJ0] = "pj0", + [PMUX_PINGRP_PJ2] = "pj2", + [PMUX_PINGRP_PK3] = "pk3", + [PMUX_PINGRP_PK4] = "pk4", + [PMUX_PINGRP_PK2] = "pk2", + [PMUX_PINGRP_PI3] = "pi3", + [PMUX_PINGRP_PI6] = "pi6", + [PMUX_PINGRP_PG0] = "pg0", + [PMUX_PINGRP_PG1] = "pg1", + [PMUX_PINGRP_PG2] = "pg2", + [PMUX_PINGRP_PG3] = "pg3", + [PMUX_PINGRP_PG4] = "pg4", + [PMUX_PINGRP_PG5] = "pg5", + [PMUX_PINGRP_PG6] = "pg6", + [PMUX_PINGRP_PG7] = "pg7", + [PMUX_PINGRP_PH0] = "ph0", + [PMUX_PINGRP_PH1] = "ph1", + [PMUX_PINGRP_PH2] = "ph2", + [PMUX_PINGRP_PH3] = "ph3", + [PMUX_PINGRP_PH4] = "ph4", + [PMUX_PINGRP_PH5] = "ph5", + [PMUX_PINGRP_PH6] = "ph6", + [PMUX_PINGRP_PH7] = "ph7", + [PMUX_PINGRP_PJ7] = "pj7", + [PMUX_PINGRP_PB0] = "pb0", + [PMUX_PINGRP_PB1] = "pb1", + [PMUX_PINGRP_PK7] = "pk7", + [PMUX_PINGRP_PI0] = "pi0", + [PMUX_PINGRP_PI1] = "pi1", + [PMUX_PINGRP_PI2] = "pi2", + [PMUX_PINGRP_PI4] = "pi4", + [PMUX_PINGRP_GEN2_I2C_SCL_PT5] = "gen2_i2c_scl_pt5", + [PMUX_PINGRP_GEN2_I2C_SDA_PT6] = "gen2_i2c_sda_pt6", + [PMUX_PINGRP_SDMMC4_CLK_PCC4] = "sdmmc4_clk_pcc4", + [PMUX_PINGRP_SDMMC4_CMD_PT7] = "sdmmc4_cmd_pt7", + [PMUX_PINGRP_SDMMC4_DAT0_PAA0] = "sdmmc4_dat0_paa0", + [PMUX_PINGRP_SDMMC4_DAT1_PAA1] = "sdmmc4_dat1_paa1", + [PMUX_PINGRP_SDMMC4_DAT2_PAA2] = "sdmmc4_dat2_paa2", + [PMUX_PINGRP_SDMMC4_DAT3_PAA3] = "sdmmc4_dat3_paa3", + [PMUX_PINGRP_SDMMC4_DAT4_PAA4] = "sdmmc4_dat4_paa4", + [PMUX_PINGRP_SDMMC4_DAT5_PAA5] = "sdmmc4_dat5_paa5", + [PMUX_PINGRP_SDMMC4_DAT6_PAA6] = "sdmmc4_dat6_paa6", + [PMUX_PINGRP_SDMMC4_DAT7_PAA7] = "sdmmc4_dat7_paa7", + [PMUX_PINGRP_CAM_MCLK_PCC0] = "cam_mclk_pcc0", + [PMUX_PINGRP_PCC1] = "pcc1", + [PMUX_PINGRP_PBB0] = "pbb0", + [PMUX_PINGRP_CAM_I2C_SCL_PBB1] = "cam_i2c_scl_pbb1", + [PMUX_PINGRP_CAM_I2C_SDA_PBB2] = "cam_i2c_sda_pbb2", + [PMUX_PINGRP_PBB3] = "pbb3", + [PMUX_PINGRP_PBB4] = "pbb4", + [PMUX_PINGRP_PBB5] = "pbb5", + [PMUX_PINGRP_PBB6] = "pbb6", + [PMUX_PINGRP_PBB7] = "pbb7", + [PMUX_PINGRP_PCC2] = "pcc2", + [PMUX_PINGRP_JTAG_RTCK] = "jtag_rtck", + [PMUX_PINGRP_PWR_I2C_SCL_PZ6] = "pwr_i2c_scl_pz6", + [PMUX_PINGRP_PWR_I2C_SDA_PZ7] = "pwr_i2c_sda_pz7", + [PMUX_PINGRP_KB_ROW0_PR0] = "kb_row0_pr0", + [PMUX_PINGRP_KB_ROW1_PR1] = "kb_row1_pr1", + [PMUX_PINGRP_KB_ROW2_PR2] = "kb_row2_pr2", + [PMUX_PINGRP_KB_ROW3_PR3] = "kb_row3_pr3", + [PMUX_PINGRP_KB_ROW4_PR4] = "kb_row4_pr4", + [PMUX_PINGRP_KB_ROW5_PR5] = "kb_row5_pr5", + [PMUX_PINGRP_KB_ROW6_PR6] = "kb_row6_pr6", + [PMUX_PINGRP_KB_ROW7_PR7] = "kb_row7_pr7", + [PMUX_PINGRP_KB_ROW8_PS0] = "kb_row8_ps0", + [PMUX_PINGRP_KB_ROW9_PS1] = "kb_row9_ps1", + [PMUX_PINGRP_KB_ROW10_PS2] = "kb_row10_ps2", + [PMUX_PINGRP_KB_ROW11_PS3] = "kb_row11_ps3", + [PMUX_PINGRP_KB_ROW12_PS4] = "kb_row12_ps4", + [PMUX_PINGRP_KB_ROW13_PS5] = "kb_row13_ps5", + [PMUX_PINGRP_KB_ROW14_PS6] = "kb_row14_ps6", + [PMUX_PINGRP_KB_ROW15_PS7] = "kb_row15_ps7", + [PMUX_PINGRP_KB_COL0_PQ0] = "kb_col0_pq0", + [PMUX_PINGRP_KB_COL1_PQ1] = "kb_col1_pq1", + [PMUX_PINGRP_KB_COL2_PQ2] = "kb_col2_pq2", + [PMUX_PINGRP_KB_COL3_PQ3] = "kb_col3_pq3", + [PMUX_PINGRP_KB_COL4_PQ4] = "kb_col4_pq4", + [PMUX_PINGRP_KB_COL5_PQ5] = "kb_col5_pq5", + [PMUX_PINGRP_KB_COL6_PQ6] = "kb_col6_pq6", + [PMUX_PINGRP_KB_COL7_PQ7] = "kb_col7_pq7", + [PMUX_PINGRP_CLK_32K_OUT_PA0] = "clk_32k_out_pa0", + [PMUX_PINGRP_CORE_PWR_REQ] = "core_pwr_req", + [PMUX_PINGRP_CPU_PWR_REQ] = "cpu_pwr_req", + [PMUX_PINGRP_PWR_INT_N] = "pwr_int_n", + [PMUX_PINGRP_CLK_32K_IN] = "clk_32k_in", + [PMUX_PINGRP_OWR] = "owr", + [PMUX_PINGRP_DAP1_FS_PN0] = "dap1_fs_pn0", + [PMUX_PINGRP_DAP1_DIN_PN1] = "dap1_din_pn1", + [PMUX_PINGRP_DAP1_DOUT_PN2] = "dap1_dout_pn2", + [PMUX_PINGRP_DAP1_SCLK_PN3] = "dap1_sclk_pn3", + [PMUX_PINGRP_DAP_MCLK1_REQ_PEE2] = "dap_mclk1_req_pee2", + [PMUX_PINGRP_DAP_MCLK1_PW4] = "dap_mclk1_pw4", + [PMUX_PINGRP_SPDIF_IN_PK6] = "spdif_in_pk6", + [PMUX_PINGRP_SPDIF_OUT_PK5] = "spdif_out_pk5", + [PMUX_PINGRP_DAP2_FS_PA2] = "dap2_fs_pa2", + [PMUX_PINGRP_DAP2_DIN_PA4] = "dap2_din_pa4", + [PMUX_PINGRP_DAP2_DOUT_PA5] = "dap2_dout_pa5", + [PMUX_PINGRP_DAP2_SCLK_PA3] = "dap2_sclk_pa3", + [PMUX_PINGRP_DVFS_PWM_PX0] = "dvfs_pwm_px0", + [PMUX_PINGRP_GPIO_X1_AUD_PX1] = "gpio_x1_aud_px1", + [PMUX_PINGRP_GPIO_X3_AUD_PX3] = "gpio_x3_aud_px3", + [PMUX_PINGRP_DVFS_CLK_PX2] = "dvfs_clk_px2", + [PMUX_PINGRP_GPIO_X4_AUD_PX4] = "gpio_x4_aud_px4", + [PMUX_PINGRP_GPIO_X5_AUD_PX5] = "gpio_x5_aud_px5", + [PMUX_PINGRP_GPIO_X6_AUD_PX6] = "gpio_x6_aud_px6", + [PMUX_PINGRP_GPIO_X7_AUD_PX7] = "gpio_x7_aud_px7", + [PMUX_PINGRP_SDMMC3_CLK_PA6] = "sdmmc3_clk_pa6", + [PMUX_PINGRP_SDMMC3_CMD_PA7] = "sdmmc3_cmd_pa7", + [PMUX_PINGRP_SDMMC3_DAT0_PB7] = "sdmmc3_dat0_pb7", + [PMUX_PINGRP_SDMMC3_DAT1_PB6] = "sdmmc3_dat1_pb6", + [PMUX_PINGRP_SDMMC3_DAT2_PB5] = "sdmmc3_dat2_pb5", + [PMUX_PINGRP_SDMMC3_DAT3_PB4] = "sdmmc3_dat3_pb4", + [PMUX_PINGRP_PEX_L0_RST_N_PDD1] = "pex_l0_rst_n_pdd1", + [PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2] = "pex_l0_clkreq_n_pdd2", + [PMUX_PINGRP_PEX_WAKE_N_PDD3] = "pex_wake_n_pdd3", + [PMUX_PINGRP_PEX_L1_RST_N_PDD5] = "pex_l1_rst_n_pdd5", + [PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6] = "pex_l1_clkreq_n_pdd6", + [PMUX_PINGRP_HDMI_CEC_PEE3] = "hdmi_cec_pee3", + [PMUX_PINGRP_SDMMC1_WP_N_PV3] = "sdmmc1_wp_n_pv3", + [PMUX_PINGRP_SDMMC3_CD_N_PV2] = "sdmmc3_cd_n_pv2", + [PMUX_PINGRP_GPIO_W2_AUD_PW2] = "gpio_w2_aud_pw2", + [PMUX_PINGRP_GPIO_W3_AUD_PW3] = "gpio_w3_aud_pw3", + [PMUX_PINGRP_USB_VBUS_EN0_PN4] = "usb_vbus_en0_pn4", + [PMUX_PINGRP_USB_VBUS_EN1_PN5] = "usb_vbus_en1_pn5", + [PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5] = "sdmmc3_clk_lb_in_pee5", + [PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4] = "sdmmc3_clk_lb_out_pee4", + [PMUX_PINGRP_GMI_CLK_LB] = "gmi_clk_lb", + [PMUX_PINGRP_RESET_OUT_N] = "reset_out_n", + [PMUX_PINGRP_KB_ROW16_PT0] = "kb_row16_pt0", + [PMUX_PINGRP_KB_ROW17_PT1] = "kb_row17_pt1", + [PMUX_PINGRP_USB_VBUS_EN2_PFF1] = "usb_vbus_en2_pff1", + [PMUX_PINGRP_PFF2] = "pff2", + [PMUX_PINGRP_DP_HPD_PFF0] = "dp_hpd_pff0", +}; + +static const char * const tegra_pinctrl_to_drvgrp[] = { + [PMUX_DRVGRP_AO1] = "ao1", + [PMUX_DRVGRP_AO2] = "ao2", + [PMUX_DRVGRP_AT1] = "at1", + [PMUX_DRVGRP_AT2] = "at2", + [PMUX_DRVGRP_AT3] = "at3", + [PMUX_DRVGRP_AT4] = "at4", + [PMUX_DRVGRP_AT5] = "at5", + [PMUX_DRVGRP_CDEV1] = "cdev1", + [PMUX_DRVGRP_CDEV2] = "cdev2", + [PMUX_DRVGRP_DAP1] = "dap1", + [PMUX_DRVGRP_DAP2] = "dap2", + [PMUX_DRVGRP_DAP3] = "dap3", + [PMUX_DRVGRP_DAP4] = "dap4", + [PMUX_DRVGRP_DBG] = "dbg", + [PMUX_DRVGRP_SDIO3] = "sdio3", + [PMUX_DRVGRP_SPI] = "spi", + [PMUX_DRVGRP_UAA] = "uaa", + [PMUX_DRVGRP_UAB] = "uab", + [PMUX_DRVGRP_UART2] = "uart2", + [PMUX_DRVGRP_UART3] = "uart3", + [PMUX_DRVGRP_SDIO1] = "sdio1", + [PMUX_DRVGRP_DDC] = "ddc", + [PMUX_DRVGRP_GMA] = "gma", + [PMUX_DRVGRP_GME] = "gme", + [PMUX_DRVGRP_GMF] = "gmf", + [PMUX_DRVGRP_GMG] = "gmg", + [PMUX_DRVGRP_GMH] = "gmh", + [PMUX_DRVGRP_OWR] = "owr", + [PMUX_DRVGRP_UDA] = "uda", + [PMUX_DRVGRP_GPV] = "gpv", + [PMUX_DRVGRP_DEV3] = "dev3", + [PMUX_DRVGRP_CEC] = "cec", + [PMUX_DRVGRP_AT6] = "at6", + [PMUX_DRVGRP_DAP5] = "dap5", + [PMUX_DRVGRP_USB_VBUS_EN] = "usb_vbus_en", + [PMUX_DRVGRP_AO3] = "ao3", + [PMUX_DRVGRP_AO0] = "ao0", + [PMUX_DRVGRP_HV0] = "hv0", + [PMUX_DRVGRP_SDIO4] = "sdio4", + [PMUX_DRVGRP_AO4] = "ao4", +}; + +static const char * const tegra_pinctrl_to_func[] = { + [PMUX_FUNC_DEFAULT] = "default", + [PMUX_FUNC_BLINK] = "blink", + [PMUX_FUNC_CCLA] = "ccla", + [PMUX_FUNC_CEC] = "cec", + [PMUX_FUNC_CLDVFS] = "cldvfs", + [PMUX_FUNC_CLK] = "clk", + [PMUX_FUNC_CLK12] = "clk12", + [PMUX_FUNC_CPU] = "cpu", + [PMUX_FUNC_CSI] = "csi", + [PMUX_FUNC_DAP] = "dap", + [PMUX_FUNC_DAP1] = "dap1", + [PMUX_FUNC_DAP2] = "dap2", + [PMUX_FUNC_DEV3] = "dev3", + [PMUX_FUNC_DISPLAYA] = "displaya", + [PMUX_FUNC_DISPLAYA_ALT] = "displaya_alt", + [PMUX_FUNC_DISPLAYB] = "displayb", + [PMUX_FUNC_DP] = "dp", + [PMUX_FUNC_DSI_B] = "dsi_b", + [PMUX_FUNC_DTV] = "dtv", + [PMUX_FUNC_EXTPERIPH1] = "extperiph1", + [PMUX_FUNC_EXTPERIPH2] = "extperiph2", + [PMUX_FUNC_EXTPERIPH3] = "extperiph3", + [PMUX_FUNC_GMI] = "gmi", + [PMUX_FUNC_GMI_ALT] = "gmi_alt", + [PMUX_FUNC_HDA] = "hda", + [PMUX_FUNC_HSI] = "hsi", + [PMUX_FUNC_I2C1] = "i2c1", + [PMUX_FUNC_I2C2] = "i2c2", + [PMUX_FUNC_I2C3] = "i2c3", + [PMUX_FUNC_I2C4] = "i2c4", + [PMUX_FUNC_I2CPWR] = "i2cpwr", + [PMUX_FUNC_I2S0] = "i2s0", + [PMUX_FUNC_I2S1] = "i2s1", + [PMUX_FUNC_I2S2] = "i2s2", + [PMUX_FUNC_I2S3] = "i2s3", + [PMUX_FUNC_I2S4] = "i2s4", + [PMUX_FUNC_IRDA] = "irda", + [PMUX_FUNC_KBC] = "kbc", + [PMUX_FUNC_OWR] = "owr", + [PMUX_FUNC_PE] = "pe", + [PMUX_FUNC_PE0] = "pe0", + [PMUX_FUNC_PE1] = "pe1", + [PMUX_FUNC_PMI] = "pmi", + [PMUX_FUNC_PWM0] = "pwm0", + [PMUX_FUNC_PWM1] = "pwm1", + [PMUX_FUNC_PWM2] = "pwm2", + [PMUX_FUNC_PWM3] = "pwm3", + [PMUX_FUNC_PWRON] = "pwron", + [PMUX_FUNC_RESET_OUT_N] = "reset_out_n", + [PMUX_FUNC_RTCK] = "rtck", + [PMUX_FUNC_SATA] = "sata", + [PMUX_FUNC_SDMMC1] = "sdmmc1", + [PMUX_FUNC_SDMMC2] = "sdmmc2", + [PMUX_FUNC_SDMMC3] = "sdmmc3", + [PMUX_FUNC_SDMMC4] = "sdmmc4", + [PMUX_FUNC_SOC] = "soc", + [PMUX_FUNC_SPDIF] = "spdif", + [PMUX_FUNC_SPI1] = "spi1", + [PMUX_FUNC_SPI2] = "spi2", + [PMUX_FUNC_SPI3] = "spi3", + [PMUX_FUNC_SPI4] = "spi4", + [PMUX_FUNC_SPI5] = "spi5", + [PMUX_FUNC_SPI6] = "spi6", + [PMUX_FUNC_SYS] = "sys", + [PMUX_FUNC_TMDS] = "tmds", + [PMUX_FUNC_TRACE] = "trace", + [PMUX_FUNC_UARTA] = "uarta", + [PMUX_FUNC_UARTB] = "uartb", + [PMUX_FUNC_UARTC] = "uartc", + [PMUX_FUNC_UARTD] = "uartd", + [PMUX_FUNC_ULPI] = "ulpi", + [PMUX_FUNC_USB] = "usb", + [PMUX_FUNC_VGP1] = "vgp1", + [PMUX_FUNC_VGP2] = "vgp2", + [PMUX_FUNC_VGP3] = "vgp3", + [PMUX_FUNC_VGP4] = "vgp4", + [PMUX_FUNC_VGP5] = "vgp5", + [PMUX_FUNC_VGP6] = "vgp6", + [PMUX_FUNC_VI] = "vi", + [PMUX_FUNC_VI_ALT1] = "vi_alt1", + [PMUX_FUNC_VI_ALT3] = "vi_alt3", + [PMUX_FUNC_VIMCLK2] = "vimclk2", + [PMUX_FUNC_VIMCLK2_ALT] = "vimclk2_alt", + [PMUX_FUNC_RSVD1] = "rsvd1", + [PMUX_FUNC_RSVD2] = "rsvd2", + [PMUX_FUNC_RSVD3] = "rsvd3", + [PMUX_FUNC_RSVD4] = "rsvd4", +}; + #define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868 #define TEGRA_PMX_SOC_MIPIPADCTRL_BASE_REG 0x820 #define TEGRA_PMX_SOC_HAS_IO_CLAMPING diff --git a/arch/arm/include/asm/arch-tegra20/pinmux.h b/arch/arm/include/asm/arch-tegra20/pinmux.h index e9e3801e6f..8c8579e87e 100644 --- a/arch/arm/include/asm/arch-tegra20/pinmux.h +++ b/arch/arm/include/asm/arch-tegra20/pinmux.h @@ -159,6 +159,47 @@ enum pmux_pingrp { PMUX_PINGRP_COUNT, }; +enum pmux_drvgrp { + PMUX_DRVGRP_AO1, + PMUX_DRVGRP_AO2, + PMUX_DRVGRP_AT1, + PMUX_DRVGRP_AT2, + PMUX_DRVGRP_CDEV1, + PMUX_DRVGRP_CDEV2, + PMUX_DRVGRP_CSUS, + PMUX_DRVGRP_DAP1, + PMUX_DRVGRP_DAP2, + PMUX_DRVGRP_DAP3, + PMUX_DRVGRP_DAP4, + PMUX_DRVGRP_DBG, + PMUX_DRVGRP_LCD1, + PMUX_DRVGRP_LCD2, + PMUX_DRVGRP_SDIO2, + PMUX_DRVGRP_SDIO3, + PMUX_DRVGRP_SPI, + PMUX_DRVGRP_UAA, + PMUX_DRVGRP_UAB, + PMUX_DRVGRP_UART2, + PMUX_DRVGRP_UART3, + PMUX_DRVGRP_VI1, + PMUX_DRVGRP_VI2, + PMUX_DRVGRP_XM2A, + PMUX_DRVGRP_XM2C, + PMUX_DRVGRP_XM2D, + PMUX_DRVGRP_XM2CLK, + PMUX_DRVGRP_SDIO1 = (0x78 / 4), + PMUX_DRVGRP_CRT = (0x84 / 4), + PMUX_DRVGRP_DDC, + PMUX_DRVGRP_GMA, + PMUX_DRVGRP_GMB, + PMUX_DRVGRP_GMC, + PMUX_DRVGRP_GMD, + PMUX_DRVGRP_GME, + PMUX_DRVGRP_OWR, + PMUX_DRVGRP_UDA, + PMUX_DRVGRP_COUNT, +}; + /* * Functions which can be assigned to each of the pin groups. The values here * bear no relation to the values programmed into pinmux registers and are @@ -232,6 +273,256 @@ enum pmux_func { PMUX_FUNC_COUNT, }; +static const char * const tegra_pinctrl_to_pingrp[] = { + /* APB_MISC_PP_TRISTATE_REG_A_0 */ + [PMUX_PINGRP_ATA] = "ata", + [PMUX_PINGRP_ATB] = "atb", + [PMUX_PINGRP_ATC] = "atc", + [PMUX_PINGRP_ATD] = "atd", + [PMUX_PINGRP_CDEV1] = "cdev1", + [PMUX_PINGRP_CDEV2] = "cdev2", + [PMUX_PINGRP_CSUS] = "csus", + [PMUX_PINGRP_DAP1] = "dap1", + + [PMUX_PINGRP_DAP2] = "dap2", + [PMUX_PINGRP_DAP3] = "dap3", + [PMUX_PINGRP_DAP4] = "dap4", + [PMUX_PINGRP_DTA] = "dta", + [PMUX_PINGRP_DTB] = "dtb", + [PMUX_PINGRP_DTC] = "dtc", + [PMUX_PINGRP_DTD] = "dtd", + [PMUX_PINGRP_DTE] = "dte", + + [PMUX_PINGRP_GPU] = "gpu", + [PMUX_PINGRP_GPV] = "gpv", + [PMUX_PINGRP_I2CP] = "i2cp", + [PMUX_PINGRP_IRTX] = "irtx", + [PMUX_PINGRP_IRRX] = "irrx", + [PMUX_PINGRP_KBCB] = "kbcb", + [PMUX_PINGRP_KBCA] = "kbca", + [PMUX_PINGRP_PMC] = "pmc", + + [PMUX_PINGRP_PTA] = "pta", + [PMUX_PINGRP_RM] = "rm", + [PMUX_PINGRP_KBCE] = "kbce", + [PMUX_PINGRP_KBCF] = "kbcf", + [PMUX_PINGRP_GMA] = "gma", + [PMUX_PINGRP_GMC] = "gmc", + [PMUX_PINGRP_SDIO1] = "sdio1", + [PMUX_PINGRP_OWC] = "owc", + + /* 32: APB_MISC_PP_TRISTATE_REG_B_0 */ + [PMUX_PINGRP_GME] = "gme", + [PMUX_PINGRP_SDC] = "sdc", + [PMUX_PINGRP_SDD] = "sdd", + [PMUX_PINGRP_RESERVED0] = "reserved0", + [PMUX_PINGRP_SLXA] = "slxa", + [PMUX_PINGRP_SLXC] = "slxc", + [PMUX_PINGRP_SLXD] = "slxd", + [PMUX_PINGRP_SLXK] = "slxk", + + [PMUX_PINGRP_SPDI] = "spdi", + [PMUX_PINGRP_SPDO] = "spdo", + [PMUX_PINGRP_SPIA] = "spia", + [PMUX_PINGRP_SPIB] = "spib", + [PMUX_PINGRP_SPIC] = "spic", + [PMUX_PINGRP_SPID] = "spid", + [PMUX_PINGRP_SPIE] = "spie", + [PMUX_PINGRP_SPIF] = "spif", + + [PMUX_PINGRP_SPIG] = "spig", + [PMUX_PINGRP_SPIH] = "spih", + [PMUX_PINGRP_UAA] = "uaa", + [PMUX_PINGRP_UAB] = "uab", + [PMUX_PINGRP_UAC] = "uac", + [PMUX_PINGRP_UAD] = "uad", + [PMUX_PINGRP_UCA] = "uca", + [PMUX_PINGRP_UCB] = "ucb", + + [PMUX_PINGRP_RESERVED1] = "reserved1", + [PMUX_PINGRP_ATE] = "ate", + [PMUX_PINGRP_KBCC] = "kbcc", + [PMUX_PINGRP_RESERVED2] = "reserved2", + [PMUX_PINGRP_RESERVED3] = "reserved3", + [PMUX_PINGRP_GMB] = "gmb", + [PMUX_PINGRP_GMD] = "gmd", + [PMUX_PINGRP_DDC] = "ddc", + + /* 64: APB_MISC_PP_TRISTATE_REG_C_0 */ + [PMUX_PINGRP_LD0] = "ld0", + [PMUX_PINGRP_LD1] = "ld1", + [PMUX_PINGRP_LD2] = "ld2", + [PMUX_PINGRP_LD3] = "ld3", + [PMUX_PINGRP_LD4] = "ld4", + [PMUX_PINGRP_LD5] = "ld5", + [PMUX_PINGRP_LD6] = "ld6", + [PMUX_PINGRP_LD7] = "ld7", + + [PMUX_PINGRP_LD8] = "ld8", + [PMUX_PINGRP_LD9] = "ld9", + [PMUX_PINGRP_LD10] = "ld10", + [PMUX_PINGRP_LD11] = "ld11", + [PMUX_PINGRP_LD12] = "ld12", + [PMUX_PINGRP_LD13] = "ld13", + [PMUX_PINGRP_LD14] = "ld14", + [PMUX_PINGRP_LD15] = "ld15", + + [PMUX_PINGRP_LD16] = "ld16", + [PMUX_PINGRP_LD17] = "ld17", + [PMUX_PINGRP_LHP0] = "lhp0", + [PMUX_PINGRP_LHP1] = "lhp1", + [PMUX_PINGRP_LHP2] = "lhp2", + [PMUX_PINGRP_LVP0] = "lvp0", + [PMUX_PINGRP_LVP1] = "lvp1", + [PMUX_PINGRP_HDINT] = "hdint", + + [PMUX_PINGRP_LM0] = "lm0", + [PMUX_PINGRP_LM1] = "lm1", + [PMUX_PINGRP_LVS] = "lvs", + [PMUX_PINGRP_LSC0] = "lsc0", + [PMUX_PINGRP_LSC1] = "lsc1", + [PMUX_PINGRP_LSCK] = "lsck", + [PMUX_PINGRP_LDC] = "ldc", + [PMUX_PINGRP_LCSN] = "lcsn", + + /* 96: APB_MISC_PP_TRISTATE_REG_D_0 */ + [PMUX_PINGRP_LSPI] = "lspi", + [PMUX_PINGRP_LSDA] = "lsda", + [PMUX_PINGRP_LSDI] = "lsdi", + [PMUX_PINGRP_LPW0] = "lpw0", + [PMUX_PINGRP_LPW1] = "lpw1", + [PMUX_PINGRP_LPW2] = "lpw2", + [PMUX_PINGRP_LDI] = "ldi", + [PMUX_PINGRP_LHS] = "lhs", + + [PMUX_PINGRP_LPP] = "lpp", + [PMUX_PINGRP_RESERVED4] = "reserved4", + [PMUX_PINGRP_KBCD] = "kbcd", + [PMUX_PINGRP_GPU7] = "gpu7", + [PMUX_PINGRP_DTF] = "dtf", + [PMUX_PINGRP_UDA] = "uda", + [PMUX_PINGRP_CRTP] = "crtp", + [PMUX_PINGRP_SDB] = "sdb", + + /* these pin groups only have pullup and pull down control */ + [PMUX_PINGRP_CK32] = "ck32", + [PMUX_PINGRP_DDRC] = "ddrc", + [PMUX_PINGRP_PMCA] = "pmca", + [PMUX_PINGRP_PMCB] = "pmcb", + [PMUX_PINGRP_PMCC] = "pmcc", + [PMUX_PINGRP_PMCD] = "pmcd", + [PMUX_PINGRP_PMCE] = "pmce", + [PMUX_PINGRP_XM2C] = "xm2c", + [PMUX_PINGRP_XM2D] = "xm2d", +}; + +static const char * const tegra_pinctrl_to_drvgrp[] = { + [PMUX_DRVGRP_AO1] = "drive_ao1", + [PMUX_DRVGRP_AO2] = "drive_ao2", + [PMUX_DRVGRP_AT1] = "drive_at1", + [PMUX_DRVGRP_AT2] = "drive_at2", + [PMUX_DRVGRP_CDEV1] = "drive_cdev1", + [PMUX_DRVGRP_CDEV2] = "drive_cdev2", + [PMUX_DRVGRP_CSUS] = "drive_csus", + [PMUX_DRVGRP_DAP1] = "drive_dap1", + [PMUX_DRVGRP_DAP2] = "drive_dap2", + [PMUX_DRVGRP_DAP3] = "drive_dap3", + [PMUX_DRVGRP_DAP4] = "drive_dap4", + [PMUX_DRVGRP_DBG] = "drive_dbg", + [PMUX_DRVGRP_LCD1] = "drive_lcd1", + [PMUX_DRVGRP_LCD2] = "drive_lcd2", + [PMUX_DRVGRP_SDIO2] = "drive_sdio2", + [PMUX_DRVGRP_SDIO3] = "drive_sdio3", + [PMUX_DRVGRP_SPI] = "drive_spi", + [PMUX_DRVGRP_UAA] = "drive_uaa", + [PMUX_DRVGRP_UAB] = "drive_uab", + [PMUX_DRVGRP_UART2] = "drive_uart2", + [PMUX_DRVGRP_UART3] = "drive_uart3", + [PMUX_DRVGRP_VI1] = "drive_vi1", + [PMUX_DRVGRP_VI2] = "drive_vi2", + [PMUX_DRVGRP_XM2A] = "drive_xm2a", + [PMUX_DRVGRP_XM2C] = "drive_xm2c", + [PMUX_DRVGRP_XM2D] = "drive_xm2d", + [PMUX_DRVGRP_XM2CLK] = "drive_xm2clk", + [PMUX_DRVGRP_SDIO1] = "drive_sdio1", + [PMUX_DRVGRP_CRT] = "drive_crt", + [PMUX_DRVGRP_DDC] = "drive_ddc", + [PMUX_DRVGRP_GMA] = "drive_gma", + [PMUX_DRVGRP_GMB] = "drive_gmb", + [PMUX_DRVGRP_GMC] = "drive_gmc", + [PMUX_DRVGRP_GMD] = "drive_gmd", + [PMUX_DRVGRP_GME] = "drive_gme", + [PMUX_DRVGRP_OWR] = "drive_owr", + [PMUX_DRVGRP_UDA] = "drive_uda", +}; + +static const char * const tegra_pinctrl_to_func[] = { + [PMUX_FUNC_DEFAULT] = "default", + [PMUX_FUNC_AHB_CLK] = "ahb_clk", + [PMUX_FUNC_APB_CLK] = "apb_clk", + [PMUX_FUNC_AUDIO_SYNC] = "audio_sync", + [PMUX_FUNC_CRT] = "crt", + [PMUX_FUNC_DAP1] = "dap1", + [PMUX_FUNC_DAP2] = "dap2", + [PMUX_FUNC_DAP3] = "dap3", + [PMUX_FUNC_DAP4] = "dap4", + [PMUX_FUNC_DAP5] = "dap5", + [PMUX_FUNC_DISPA] = "dispa", + [PMUX_FUNC_DISPB] = "dispb", + [PMUX_FUNC_EMC_TEST0_DLL] = "emc_test0_dll", + [PMUX_FUNC_EMC_TEST1_DLL] = "emc_test1_dll", + [PMUX_FUNC_GMI] = "gmi", + [PMUX_FUNC_GMI_INT] = "gmi_int", + [PMUX_FUNC_HDMI] = "hdmi", + [PMUX_FUNC_I2C] = "i2c", + [PMUX_FUNC_I2C2] = "i2c2", + [PMUX_FUNC_I2C3] = "i2c3", + [PMUX_FUNC_IDE] = "ide", + [PMUX_FUNC_KBC] = "kbc", + [PMUX_FUNC_MIO] = "mio", + [PMUX_FUNC_MIPI_HS] = "mipi_hs", + [PMUX_FUNC_NAND] = "nand", + [PMUX_FUNC_OSC] = "osc", + [PMUX_FUNC_OWR] = "owr", + [PMUX_FUNC_PCIE] = "pcie", + [PMUX_FUNC_PLLA_OUT] = "plla_out", + [PMUX_FUNC_PLLC_OUT1] = "pllc_out1", + [PMUX_FUNC_PLLM_OUT1] = "pllm_out1", + [PMUX_FUNC_PLLP_OUT2] = "pllp_out2", + [PMUX_FUNC_PLLP_OUT3] = "pllp_out3", + [PMUX_FUNC_PLLP_OUT4] = "pllp_out4", + [PMUX_FUNC_PWM] = "pwm", + [PMUX_FUNC_PWR_INTR] = "pwr_intr", + [PMUX_FUNC_PWR_ON] = "pwr_on", + [PMUX_FUNC_RTCK] = "rtck", + [PMUX_FUNC_SDIO1] = "sdio1", + [PMUX_FUNC_SDIO2] = "sdio2", + [PMUX_FUNC_SDIO3] = "sdio3", + [PMUX_FUNC_SDIO4] = "sdio4", + [PMUX_FUNC_SFLASH] = "sflash", + [PMUX_FUNC_SPDIF] = "spdif", + [PMUX_FUNC_SPI1] = "spi1", + [PMUX_FUNC_SPI2] = "spi2", + [PMUX_FUNC_SPI2_ALT] = "spi2_alt", + [PMUX_FUNC_SPI3] = "spi3", + [PMUX_FUNC_SPI4] = "spi4", + [PMUX_FUNC_TRACE] = "trace", + [PMUX_FUNC_TWC] = "twc", + [PMUX_FUNC_UARTA] = "uarta", + [PMUX_FUNC_UARTB] = "uartb", + [PMUX_FUNC_UARTC] = "uartc", + [PMUX_FUNC_UARTD] = "uartd", + [PMUX_FUNC_UARTE] = "uarte", + [PMUX_FUNC_ULPI] = "ulpi", + [PMUX_FUNC_VI] = "vi", + [PMUX_FUNC_VI_SENSOR_CLK] = "vi_sensor_clk", + [PMUX_FUNC_XIO] = "xio", + [PMUX_FUNC_RSVD1] = "rsvd1", + [PMUX_FUNC_RSVD2] = "rsvd2", + [PMUX_FUNC_RSVD3] = "rsvd3", + [PMUX_FUNC_RSVD4] = "rsvd4", +}; + #define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868 #include <asm/arch-tegra/pinmux.h> diff --git a/arch/arm/include/asm/arch-tegra210/pinmux.h b/arch/arm/include/asm/arch-tegra210/pinmux.h index 9e94074628..062d724319 100644 --- a/arch/arm/include/asm/arch-tegra210/pinmux.h +++ b/arch/arm/include/asm/arch-tegra210/pinmux.h @@ -403,6 +403,400 @@ enum pmux_func { PMUX_FUNC_COUNT, }; +static const char * const tegra_pinctrl_to_pingrp[] = { + [PMUX_PINGRP_SDMMC1_CLK_PM0] = "sdmmc1_clk_pm0", + [PMUX_PINGRP_SDMMC1_CMD_PM1] = "sdmmc1_cmd_pm1", + [PMUX_PINGRP_SDMMC1_DAT3_PM2] = "sdmmc1_dat3_pm2", + [PMUX_PINGRP_SDMMC1_DAT2_PM3] = "sdmmc1_dat2_pm3", + [PMUX_PINGRP_SDMMC1_DAT1_PM4] = "sdmmc1_dat1_pm4", + [PMUX_PINGRP_SDMMC1_DAT0_PM5] = "sdmmc1_dat0_pm5", + [PMUX_PINGRP_SDMMC3_CLK_PP0] = "sdmmc3_clk_pp0", + [PMUX_PINGRP_SDMMC3_CMD_PP1] = "sdmmc3_cmd_pp1", + [PMUX_PINGRP_SDMMC3_DAT0_PP5] = "sdmmc3_dat0_pp5", + [PMUX_PINGRP_SDMMC3_DAT1_PP4] = "sdmmc3_dat1_pp4", + [PMUX_PINGRP_SDMMC3_DAT2_PP3] = "sdmmc3_dat2_pp3", + [PMUX_PINGRP_SDMMC3_DAT3_PP2] = "sdmmc3_dat3_pp2", + [PMUX_PINGRP_PEX_L0_RST_N_PA0] = "pex_l0_rst_n_pa0", + [PMUX_PINGRP_PEX_L0_CLKREQ_N_PA1] = "pex_l0_clkreq_n_pa1", + [PMUX_PINGRP_PEX_WAKE_N_PA2] = "pex_wake_n_pa2", + [PMUX_PINGRP_PEX_L1_RST_N_PA3] = "pex_l1_rst_n_pa3", + [PMUX_PINGRP_PEX_L1_CLKREQ_N_PA4] = "pex_l1_clkreq_n_pa4", + [PMUX_PINGRP_SATA_LED_ACTIVE_PA5] = "sata_led_active_pa5", + [PMUX_PINGRP_SPI1_MOSI_PC0] = "spi1_mosi_pc0", + [PMUX_PINGRP_SPI1_MISO_PC1] = "spi1_miso_pc1", + [PMUX_PINGRP_SPI1_SCK_PC2] = "spi1_sck_pc2", + [PMUX_PINGRP_SPI1_CS0_PC3] = "spi1_cs0_pc3", + [PMUX_PINGRP_SPI1_CS1_PC4] = "spi1_cs1_pc4", + [PMUX_PINGRP_SPI2_MOSI_PB4] = "spi2_mosi_pb4", + [PMUX_PINGRP_SPI2_MISO_PB5] = "spi2_miso_pb5", + [PMUX_PINGRP_SPI2_SCK_PB6] = "spi2_sck_pb6", + [PMUX_PINGRP_SPI2_CS0_PB7] = "spi2_cs0_pb7", + [PMUX_PINGRP_SPI2_CS1_PDD0] = "spi2_cs1_pdd0", + [PMUX_PINGRP_SPI4_MOSI_PC7] = "spi4_mosi_pc7", + [PMUX_PINGRP_SPI4_MISO_PD0] = "spi4_miso_pd0", + [PMUX_PINGRP_SPI4_SCK_PC5] = "spi4_sck_pc5", + [PMUX_PINGRP_SPI4_CS0_PC6] = "spi4_cs0_pc6", + [PMUX_PINGRP_QSPI_SCK_PEE0] = "qspi_sck_pee0", + [PMUX_PINGRP_QSPI_CS_N_PEE1] = "qspi_cs_n_pee1", + [PMUX_PINGRP_QSPI_IO0_PEE2] = "qspi_io0_pee2", + [PMUX_PINGRP_QSPI_IO1_PEE3] = "qspi_io1_pee3", + [PMUX_PINGRP_QSPI_IO2_PEE4] = "qspi_io2_pee4", + [PMUX_PINGRP_QSPI_IO3_PEE5] = "qspi_io3_pee5", + [PMUX_PINGRP_DMIC1_CLK_PE0] = "dmic1_clk_pe0", + [PMUX_PINGRP_DMIC1_DAT_PE1] = "dmic1_dat_pe1", + [PMUX_PINGRP_DMIC2_CLK_PE2] = "dmic2_clk_pe2", + [PMUX_PINGRP_DMIC2_DAT_PE3] = "dmic2_dat_pe3", + [PMUX_PINGRP_DMIC3_CLK_PE4] = "dmic3_clk_pe4", + [PMUX_PINGRP_DMIC3_DAT_PE5] = "dmic3_dat_pe5", + [PMUX_PINGRP_GEN1_I2C_SCL_PJ1] = "gen1_i2c_scl_pj1", + [PMUX_PINGRP_GEN1_I2C_SDA_PJ0] = "gen1_i2c_sda_pj0", + [PMUX_PINGRP_GEN2_I2C_SCL_PJ2] = "gen2_i2c_scl_pj2", + [PMUX_PINGRP_GEN2_I2C_SDA_PJ3] = "gen2_i2c_sda_pj3", + [PMUX_PINGRP_GEN3_I2C_SCL_PF0] = "gen3_i2c_scl_pf0", + [PMUX_PINGRP_GEN3_I2C_SDA_PF1] = "gen3_i2c_sda_pf1", + [PMUX_PINGRP_CAM_I2C_SCL_PS2] = "cam_i2c_scl_ps2", + [PMUX_PINGRP_CAM_I2C_SDA_PS3] = "cam_i2c_sda_ps3", + [PMUX_PINGRP_PWR_I2C_SCL_PY3] = "pwr_i2c_scl_py3", + [PMUX_PINGRP_PWR_I2C_SDA_PY4] = "pwr_i2c_sda_py4", + [PMUX_PINGRP_UART1_TX_PU0] = "uart1_tx_pu0", + [PMUX_PINGRP_UART1_RX_PU1] = "uart1_rx_pu1", + [PMUX_PINGRP_UART1_RTS_PU2] = "uart1_rts_pu2", + [PMUX_PINGRP_UART1_CTS_PU3] = "uart1_cts_pu3", + [PMUX_PINGRP_UART2_TX_PG0] = "uart2_tx_pg0", + [PMUX_PINGRP_UART2_RX_PG1] = "uart2_rx_pg1", + [PMUX_PINGRP_UART2_RTS_PG2] = "uart2_rts_pg2", + [PMUX_PINGRP_UART2_CTS_PG3] = "uart2_cts_pg3", + [PMUX_PINGRP_UART3_TX_PD1] = "uart3_tx_pd1", + [PMUX_PINGRP_UART3_RX_PD2] = "uart3_rx_pd2", + [PMUX_PINGRP_UART3_RTS_PD3] = "uart3_rts_pd3", + [PMUX_PINGRP_UART3_CTS_PD4] = "uart3_cts_pd4", + [PMUX_PINGRP_UART4_TX_PI4] = "uart4_tx_pi4", + [PMUX_PINGRP_UART4_RX_PI5] = "uart4_rx_pi5", + [PMUX_PINGRP_UART4_RTS_PI6] = "uart4_rts_pi6", + [PMUX_PINGRP_UART4_CTS_PI7] = "uart4_cts_pi7", + [PMUX_PINGRP_DAP1_FS_PB0] = "dap1_fs_pb0", + [PMUX_PINGRP_DAP1_DIN_PB1] = "dap1_din_pb1", + [PMUX_PINGRP_DAP1_DOUT_PB2] = "dap1_dout_pb2", + [PMUX_PINGRP_DAP1_SCLK_PB3] = "dap1_sclk_pb3", + [PMUX_PINGRP_DAP2_FS_PAA0] = "dap2_fs_paa0", + [PMUX_PINGRP_DAP2_DIN_PAA2] = "dap2_din_paa2", + [PMUX_PINGRP_DAP2_DOUT_PAA3] = "dap2_dout_paa3", + [PMUX_PINGRP_DAP2_SCLK_PAA1] = "dap2_sclk_paa1", + [PMUX_PINGRP_DAP4_FS_PJ4] = "dap4_fs_pj4", + [PMUX_PINGRP_DAP4_DIN_PJ5] = "dap4_din_pj5", + [PMUX_PINGRP_DAP4_DOUT_PJ6] = "dap4_dout_pj6", + [PMUX_PINGRP_DAP4_SCLK_PJ7] = "dap4_sclk_pj7", + [PMUX_PINGRP_CAM1_MCLK_PS0] = "cam1_mclk_ps0", + [PMUX_PINGRP_CAM2_MCLK_PS1] = "cam2_mclk_ps1", + [PMUX_PINGRP_JTAG_RTCK] = "jtag_rtck", + [PMUX_PINGRP_CLK_32K_IN] = "clk_32k_in", + [PMUX_PINGRP_CLK_32K_OUT_PY5] = "clk_32k_out_py5", + [PMUX_PINGRP_BATT_BCL] = "batt_bcl", + [PMUX_PINGRP_CLK_REQ] = "clk_req", + [PMUX_PINGRP_CPU_PWR_REQ] = "cpu_pwr_req", + [PMUX_PINGRP_PWR_INT_N] = "pwr_int_n", + [PMUX_PINGRP_SHUTDOWN] = "shutdown", + [PMUX_PINGRP_CORE_PWR_REQ] = "core_pwr_req", + [PMUX_PINGRP_AUD_MCLK_PBB0] = "aud_mclk_pbb0", + [PMUX_PINGRP_DVFS_PWM_PBB1] = "dvfs_pwm_pbb1", + [PMUX_PINGRP_DVFS_CLK_PBB2] = "dvfs_clk_pbb2", + [PMUX_PINGRP_GPIO_X1_AUD_PBB3] = "gpio_x1_aud_pbb3", + [PMUX_PINGRP_GPIO_X3_AUD_PBB4] = "gpio_x3_aud_pbb4", + [PMUX_PINGRP_PCC7] = "pcc7", + [PMUX_PINGRP_HDMI_CEC_PCC0] = "hdmi_cec_pcc0", + [PMUX_PINGRP_HDMI_INT_DP_HPD_PCC1] = "hdmi_int_dp_hpd_pcc1", + [PMUX_PINGRP_SPDIF_OUT_PCC2] = "spdif_out_pcc2", + [PMUX_PINGRP_SPDIF_IN_PCC3] = "spdif_in_pcc3", + [PMUX_PINGRP_USB_VBUS_EN0_PCC4] = "usb_vbus_en0_pcc4", + [PMUX_PINGRP_USB_VBUS_EN1_PCC5] = "usb_vbus_en1_pcc5", + [PMUX_PINGRP_DP_HPD0_PCC6] = "dp_hpd0_pcc6", + [PMUX_PINGRP_WIFI_EN_PH0] = "wifi_en_ph0", + [PMUX_PINGRP_WIFI_RST_PH1] = "wifi_rst_ph1", + [PMUX_PINGRP_WIFI_WAKE_AP_PH2] = "wifi_wake_ap_ph2", + [PMUX_PINGRP_AP_WAKE_BT_PH3] = "ap_wake_bt_ph3", + [PMUX_PINGRP_BT_RST_PH4] = "bt_rst_ph4", + [PMUX_PINGRP_BT_WAKE_AP_PH5] = "bt_wake_ap_ph5", + [PMUX_PINGRP_AP_WAKE_NFC_PH7] = "ap_wake_nfc_ph7", + [PMUX_PINGRP_NFC_EN_PI0] = "nfc_en_pi0", + [PMUX_PINGRP_NFC_INT_PI1] = "nfc_int_pi1", + [PMUX_PINGRP_GPS_EN_PI2] = "gps_en_pi2", + [PMUX_PINGRP_GPS_RST_PI3] = "gps_rst_pi3", + [PMUX_PINGRP_CAM_RST_PS4] = "cam_rst_ps4", + [PMUX_PINGRP_CAM_AF_EN_PS5] = "cam_af_en_ps5", + [PMUX_PINGRP_CAM_FLASH_EN_PS6] = "cam_flash_en_ps6", + [PMUX_PINGRP_CAM1_PWDN_PS7] = "cam1_pwdn_ps7", + [PMUX_PINGRP_CAM2_PWDN_PT0] = "cam2_pwdn_pt0", + [PMUX_PINGRP_CAM1_STROBE_PT1] = "cam1_strobe_pt1", + [PMUX_PINGRP_LCD_TE_PY2] = "lcd_te_py2", + [PMUX_PINGRP_LCD_BL_PWM_PV0] = "lcd_bl_pwm_pv0", + [PMUX_PINGRP_LCD_BL_EN_PV1] = "lcd_bl_en_pv1", + [PMUX_PINGRP_LCD_RST_PV2] = "lcd_rst_pv2", + [PMUX_PINGRP_LCD_GPIO1_PV3] = "lcd_gpio1_pv3", + [PMUX_PINGRP_LCD_GPIO2_PV4] = "lcd_gpio2_pv4", + [PMUX_PINGRP_AP_READY_PV5] = "ap_ready_pv5", + [PMUX_PINGRP_TOUCH_RST_PV6] = "touch_rst_pv6", + [PMUX_PINGRP_TOUCH_CLK_PV7] = "touch_clk_pv7", + [PMUX_PINGRP_MODEM_WAKE_AP_PX0] = "modem_wake_ap_px0", + [PMUX_PINGRP_TOUCH_INT_PX1] = "touch_int_px1", + [PMUX_PINGRP_MOTION_INT_PX2] = "motion_int_px2", + [PMUX_PINGRP_ALS_PROX_INT_PX3] = "als_prox_int_px3", + [PMUX_PINGRP_TEMP_ALERT_PX4] = "temp_alert_px4", + [PMUX_PINGRP_BUTTON_POWER_ON_PX5] = "button_power_on_px5", + [PMUX_PINGRP_BUTTON_VOL_UP_PX6] = "button_vol_up_px6", + [PMUX_PINGRP_BUTTON_VOL_DOWN_PX7] = "button_vol_down_px7", + [PMUX_PINGRP_BUTTON_SLIDE_SW_PY0] = "button_slide_sw_py0", + [PMUX_PINGRP_BUTTON_HOME_PY1] = "button_home_py1", + [PMUX_PINGRP_PA6] = "pa6", + [PMUX_PINGRP_PE6] = "pe6", + [PMUX_PINGRP_PE7] = "pe7", + [PMUX_PINGRP_PH6] = "ph6", + [PMUX_PINGRP_PK0] = "pk0", + [PMUX_PINGRP_PK1] = "pk1", + [PMUX_PINGRP_PK2] = "pk2", + [PMUX_PINGRP_PK3] = "pk3", + [PMUX_PINGRP_PK4] = "pk4", + [PMUX_PINGRP_PK5] = "pk5", + [PMUX_PINGRP_PK6] = "pk6", + [PMUX_PINGRP_PK7] = "pk7", + [PMUX_PINGRP_PL0] = "pl0", + [PMUX_PINGRP_PL1] = "pl1", + [PMUX_PINGRP_PZ0] = "pz0", + [PMUX_PINGRP_PZ1] = "pz1", + [PMUX_PINGRP_PZ2] = "pz2", + [PMUX_PINGRP_PZ3] = "pz3", + [PMUX_PINGRP_PZ4] = "pz4", + [PMUX_PINGRP_PZ5] = "pz5", +}; + +static const char * const tegra_pinctrl_to_drvgrp[] = { + [PMUX_DRVGRP_ALS_PROX_INT] = "als_prox_int", + [PMUX_DRVGRP_AP_READY] = "ap_ready", + [PMUX_DRVGRP_AP_WAKE_BT] = "ap_wake_bt", + [PMUX_DRVGRP_AP_WAKE_NFC] = "ap_wake_nfc", + [PMUX_DRVGRP_AUD_MCLK] = "aud_mclk", + [PMUX_DRVGRP_BATT_BCL] = "batt_bcl", + [PMUX_DRVGRP_BT_RST] = "bt_rst", + [PMUX_DRVGRP_BT_WAKE_AP] = "bt_wake_ap", + [PMUX_DRVGRP_BUTTON_HOME] = "button_home", + [PMUX_DRVGRP_BUTTON_POWER_ON] = "button_power_on", + [PMUX_DRVGRP_BUTTON_SLIDE_SW] = "button_slide_sw", + [PMUX_DRVGRP_BUTTON_VOL_DOWN] = "button_vol_down", + [PMUX_DRVGRP_BUTTON_VOL_UP] = "button_vol_up", + [PMUX_DRVGRP_CAM1_MCLK] = "cam1_mclk", + [PMUX_DRVGRP_CAM1_PWDN] = "cam1_pwdn", + [PMUX_DRVGRP_CAM1_STROBE] = "cam1_strobe", + [PMUX_DRVGRP_CAM2_MCLK] = "cam2_mclk", + [PMUX_DRVGRP_CAM2_PWDN] = "cam2_pwdn", + [PMUX_DRVGRP_CAM_AF_EN] = "cam_af_en", + [PMUX_DRVGRP_CAM_FLASH_EN] = "cam_flash_en", + [PMUX_DRVGRP_CAM_I2C_SCL] = "cam_i2c_scl", + [PMUX_DRVGRP_CAM_I2C_SDA] = "cam_i2c_sda", + [PMUX_DRVGRP_CAM_RST] = "cam_rst", + [PMUX_DRVGRP_CLK_32K_IN] = "clk_32k_in", + [PMUX_DRVGRP_CLK_32K_OUT] = "clk_32k_out", + [PMUX_DRVGRP_CLK_REQ] = "clk_req", + [PMUX_DRVGRP_CORE_PWR_REQ] = "core_pwr_req", + [PMUX_DRVGRP_CPU_PWR_REQ] = "cpu_pwr_req", + [PMUX_DRVGRP_DAP1_DIN] = "dap1_din", + [PMUX_DRVGRP_DAP1_DOUT] = "dap1_dout", + [PMUX_DRVGRP_DAP1_FS] = "dap1_fs", + [PMUX_DRVGRP_DAP1_SCLK] = "dap1_sclk", + [PMUX_DRVGRP_DAP2_DIN] = "dap2_din", + [PMUX_DRVGRP_DAP2_DOUT] = "dap2_dout", + [PMUX_DRVGRP_DAP2_FS] = "dap2_fs", + [PMUX_DRVGRP_DAP2_SCLK] = "dap2_sclk", + [PMUX_DRVGRP_DAP4_DIN] = "dap4_din", + [PMUX_DRVGRP_DAP4_DOUT] = "dap4_dout", + [PMUX_DRVGRP_DAP4_FS] = "dap4_fs", + [PMUX_DRVGRP_DAP4_SCLK] = "dap4_sclk", + [PMUX_DRVGRP_DMIC1_CLK] = "dmic1_clk", + [PMUX_DRVGRP_DMIC1_DAT] = "dmic1_dat", + [PMUX_DRVGRP_DMIC2_CLK] = "dmic2_clk", + [PMUX_DRVGRP_DMIC2_DAT] = "dmic2_dat", + [PMUX_DRVGRP_DMIC3_CLK] = "dmic3_clk", + [PMUX_DRVGRP_DMIC3_DAT] = "dmic3_dat", + [PMUX_DRVGRP_DP_HPD0] = "dp_hpd0", + [PMUX_DRVGRP_DVFS_CLK] = "dvfs_clk", + [PMUX_DRVGRP_DVFS_PWM] = "dvfs_pwm", + [PMUX_DRVGRP_GEN1_I2C_SCL] = "gen1_i2c_scl", + [PMUX_DRVGRP_GEN1_I2C_SDA] = "gen1_i2c_sda", + [PMUX_DRVGRP_GEN2_I2C_SCL] = "gen2_i2c_scl", + [PMUX_DRVGRP_GEN2_I2C_SDA] = "gen2_i2c_sda", + [PMUX_DRVGRP_GEN3_I2C_SCL] = "gen3_i2c_scl", + [PMUX_DRVGRP_GEN3_I2C_SDA] = "gen3_i2c_sda", + [PMUX_DRVGRP_PA6] = "pa6", + [PMUX_DRVGRP_PCC7] = "pcc7", + [PMUX_DRVGRP_PE6] = "pe6", + [PMUX_DRVGRP_PE7] = "pe7", + [PMUX_DRVGRP_PH6] = "ph6", + [PMUX_DRVGRP_PK0] = "pk0", + [PMUX_DRVGRP_PK1] = "pk1", + [PMUX_DRVGRP_PK2] = "pk2", + [PMUX_DRVGRP_PK3] = "pk3", + [PMUX_DRVGRP_PK4] = "pk4", + [PMUX_DRVGRP_PK5] = "pk5", + [PMUX_DRVGRP_PK6] = "pk6", + [PMUX_DRVGRP_PK7] = "pk7", + [PMUX_DRVGRP_PL0] = "pl0", + [PMUX_DRVGRP_PL1] = "pl1", + [PMUX_DRVGRP_PZ0] = "pz0", + [PMUX_DRVGRP_PZ1] = "pz1", + [PMUX_DRVGRP_PZ2] = "pz2", + [PMUX_DRVGRP_PZ3] = "pz3", + [PMUX_DRVGRP_PZ4] = "pz4", + [PMUX_DRVGRP_PZ5] = "pz5", + [PMUX_DRVGRP_GPIO_X1_AUD] = "gpio_x1_aud", + [PMUX_DRVGRP_GPIO_X3_AUD] = "gpio_x3_aud", + [PMUX_DRVGRP_GPS_EN] = "gps_en", + [PMUX_DRVGRP_GPS_RST] = "gps_rst", + [PMUX_DRVGRP_HDMI_CEC] = "hdmi_cec", + [PMUX_DRVGRP_HDMI_INT_DP_HPD] = "hdmi_int_dp_hpd", + [PMUX_DRVGRP_JTAG_RTCK] = "jtag_rtck", + [PMUX_DRVGRP_LCD_BL_EN] = "lcd_bl_en", + [PMUX_DRVGRP_LCD_BL_PWM] = "lcd_bl_pwm", + [PMUX_DRVGRP_LCD_GPIO1] = "lcd_gpio1", + [PMUX_DRVGRP_LCD_GPIO2] = "lcd_gpio2", + [PMUX_DRVGRP_LCD_RST] = "lcd_rst", + [PMUX_DRVGRP_LCD_TE] = "lcd_te", + [PMUX_DRVGRP_MODEM_WAKE_AP] = "modem_wake_ap", + [PMUX_DRVGRP_MOTION_INT] = "motion_int", + [PMUX_DRVGRP_NFC_EN] = "nfc_en", + [PMUX_DRVGRP_NFC_INT] = "nfc_int", + [PMUX_DRVGRP_PEX_L0_CLKREQ_N] = "pex_l0_clkreq_n", + [PMUX_DRVGRP_PEX_L0_RST_N] = "pex_l0_rst_n", + [PMUX_DRVGRP_PEX_L1_CLKREQ_N] = "pex_l1_clkreq_n", + [PMUX_DRVGRP_PEX_L1_RST_N] = "pex_l1_rst_n", + [PMUX_DRVGRP_PEX_WAKE_N] = "pex_wake_n", + [PMUX_DRVGRP_PWR_I2C_SCL] = "pwr_i2c_scl", + [PMUX_DRVGRP_PWR_I2C_SDA] = "pwr_i2c_sda", + [PMUX_DRVGRP_PWR_INT_N] = "pwr_int_n", + [PMUX_DRVGRP_QSPI_SCK] = "qspi_sck", + [PMUX_DRVGRP_SATA_LED_ACTIVE] = "sata_led_active", + [PMUX_DRVGRP_SDMMC1] = "sdmmc1", + [PMUX_DRVGRP_SDMMC2] = "sdmmc2", + [PMUX_DRVGRP_SDMMC3] = "sdmmc3", + [PMUX_DRVGRP_SDMMC4] = "sdmmc4", + [PMUX_DRVGRP_SHUTDOWN] = "shutdown", + [PMUX_DRVGRP_SPDIF_IN] = "spdif_in", + [PMUX_DRVGRP_SPDIF_OUT] = "spdif_out", + [PMUX_DRVGRP_SPI1_CS0] = "spi1_cs0", + [PMUX_DRVGRP_SPI1_CS1] = "spi1_cs1", + [PMUX_DRVGRP_SPI1_MISO] = "spi1_miso", + [PMUX_DRVGRP_SPI1_MOSI] = "spi1_mosi", + [PMUX_DRVGRP_SPI1_SCK] = "spi1_sck", + [PMUX_DRVGRP_SPI2_CS0] = "spi2_cs0", + [PMUX_DRVGRP_SPI2_CS1] = "spi2_cs1", + [PMUX_DRVGRP_SPI2_MISO] = "spi2_miso", + [PMUX_DRVGRP_SPI2_MOSI] = "spi2_mosi", + [PMUX_DRVGRP_SPI2_SCK] = "spi2_sck", + [PMUX_DRVGRP_SPI4_CS0] = "spi4_cs0", + [PMUX_DRVGRP_SPI4_MISO] = "spi4_miso", + [PMUX_DRVGRP_SPI4_MOSI] = "spi4_mosi", + [PMUX_DRVGRP_SPI4_SCK] = "spi4_sck", + [PMUX_DRVGRP_TEMP_ALERT] = "temp_alert", + [PMUX_DRVGRP_TOUCH_CLK] = "touch_clk", + [PMUX_DRVGRP_TOUCH_INT] = "touch_int", + [PMUX_DRVGRP_TOUCH_RST] = "touch_rst", + [PMUX_DRVGRP_UART1_CTS] = "uart1_cts", + [PMUX_DRVGRP_UART1_RTS] = "uart1_rts", + [PMUX_DRVGRP_UART1_RX] = "uart1_rx", + [PMUX_DRVGRP_UART1_TX] = "uart1_tx", + [PMUX_DRVGRP_UART2_CTS] = "uart2_cts", + [PMUX_DRVGRP_UART2_RTS] = "uart2_rts", + [PMUX_DRVGRP_UART2_RX] = "uart2_rx", + [PMUX_DRVGRP_UART2_TX] = "uart2_tx", + [PMUX_DRVGRP_UART3_CTS] = "uart3_cts", + [PMUX_DRVGRP_UART3_RTS] = "uart3_rts", + [PMUX_DRVGRP_UART3_RX] = "uart3_rx", + [PMUX_DRVGRP_UART3_TX] = "uart3_tx", + [PMUX_DRVGRP_UART4_CTS] = "uart4_cts", + [PMUX_DRVGRP_UART4_RTS] = "uart4_rts", + [PMUX_DRVGRP_UART4_RX] = "uart4_rx", + [PMUX_DRVGRP_UART4_TX] = "uart4_tx", + [PMUX_DRVGRP_USB_VBUS_EN0] = "usb_vbus_en0", + [PMUX_DRVGRP_USB_VBUS_EN1] = "usb_vbus_en1", + [PMUX_DRVGRP_WIFI_EN] = "wifi_en", + [PMUX_DRVGRP_WIFI_RST] = "wifi_rst", + [PMUX_DRVGRP_WIFI_WAKE_AP] = "wifi_wake_ap", +}; + +static const char * const tegra_pinctrl_to_func[] = { + [PMUX_FUNC_DEFAULT] = "default", + [PMUX_FUNC_AUD] = "aud", + [PMUX_FUNC_BCL] = "bcl", + [PMUX_FUNC_BLINK] = "blink", + [PMUX_FUNC_CCLA] = "ccla", + [PMUX_FUNC_CEC] = "cec", + [PMUX_FUNC_CLDVFS] = "cldvfs", + [PMUX_FUNC_CLK] = "clk", + [PMUX_FUNC_CORE] = "core", + [PMUX_FUNC_CPU] = "cpu", + [PMUX_FUNC_DISPLAYA] = "displaya", + [PMUX_FUNC_DISPLAYB] = "displayb", + [PMUX_FUNC_DMIC1] = "dmic1", + [PMUX_FUNC_DMIC2] = "dmic2", + [PMUX_FUNC_DMIC3] = "dmic3", + [PMUX_FUNC_DP] = "dp", + [PMUX_FUNC_DTV] = "dtv", + [PMUX_FUNC_EXTPERIPH3] = "extperiph3", + [PMUX_FUNC_I2C1] = "i2c1", + [PMUX_FUNC_I2C2] = "i2c2", + [PMUX_FUNC_I2C3] = "i2c3", + [PMUX_FUNC_I2CPMU] = "i2cpmu", + [PMUX_FUNC_I2CVI] = "i2cvi", + [PMUX_FUNC_I2S1] = "i2s1", + [PMUX_FUNC_I2S2] = "i2s2", + [PMUX_FUNC_I2S3] = "i2s3", + [PMUX_FUNC_I2S4A] = "i2s4a", + [PMUX_FUNC_I2S4B] = "i2s4b", + [PMUX_FUNC_I2S5A] = "i2s5a", + [PMUX_FUNC_I2S5B] = "i2s5b", + [PMUX_FUNC_IQC0] = "iqc0", + [PMUX_FUNC_IQC1] = "iqc1", + [PMUX_FUNC_JTAG] = "jtag", + [PMUX_FUNC_PE] = "pe", + [PMUX_FUNC_PE0] = "pe0", + [PMUX_FUNC_PE1] = "pe1", + [PMUX_FUNC_PMI] = "pmi", + [PMUX_FUNC_PWM0] = "pwm0", + [PMUX_FUNC_PWM1] = "pwm1", + [PMUX_FUNC_PWM2] = "pwm2", + [PMUX_FUNC_PWM3] = "pwm3", + [PMUX_FUNC_QSPI] = "qspi", + [PMUX_FUNC_SATA] = "sata", + [PMUX_FUNC_SDMMC1] = "sdmmc1", + [PMUX_FUNC_SDMMC3] = "sdmmc3", + [PMUX_FUNC_SHUTDOWN] = "shutdown", + [PMUX_FUNC_SOC] = "soc", + [PMUX_FUNC_SOR0] = "sor0", + [PMUX_FUNC_SOR1] = "sor1", + [PMUX_FUNC_SPDIF] = "spdif", + [PMUX_FUNC_SPI1] = "spi1", + [PMUX_FUNC_SPI2] = "spi2", + [PMUX_FUNC_SPI3] = "spi3", + [PMUX_FUNC_SPI4] = "spi4", + [PMUX_FUNC_SYS] = "sys", + [PMUX_FUNC_TOUCH] = "touch", + [PMUX_FUNC_UART] = "uart", + [PMUX_FUNC_UARTA] = "uarta", + [PMUX_FUNC_UARTB] = "uartb", + [PMUX_FUNC_UARTC] = "uartc", + [PMUX_FUNC_UARTD] = "uartd", + [PMUX_FUNC_USB] = "usb", + [PMUX_FUNC_VGP1] = "vgp1", + [PMUX_FUNC_VGP2] = "vgp2", + [PMUX_FUNC_VGP3] = "vgp3", + [PMUX_FUNC_VGP4] = "vgp4", + [PMUX_FUNC_VGP5] = "vgp5", + [PMUX_FUNC_VGP6] = "vgp6", + [PMUX_FUNC_VIMCLK] = "vimclk", + [PMUX_FUNC_VIMCLK2] = "vimclk2", + [PMUX_FUNC_RSVD0] = "rsvd0", + [PMUX_FUNC_RSVD1] = "rsvd1", + [PMUX_FUNC_RSVD2] = "rsvd2", + [PMUX_FUNC_RSVD3] = "rsvd3", +}; + #define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x8d4 #define TEGRA_PMX_SOC_HAS_IO_CLAMPING #define TEGRA_PMX_SOC_HAS_DRVGRPS diff --git a/arch/arm/include/asm/arch-tegra30/clock-tables.h b/arch/arm/include/asm/arch-tegra30/clock-tables.h index 6c899ff64c..5ebcbc2c9a 100644 --- a/arch/arm/include/asm/arch-tegra30/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra30/clock-tables.h @@ -23,6 +23,7 @@ enum clock_id { CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, CLOCK_ID_EPCI, CLOCK_ID_SFROM32KHZ, + CLOCK_ID_DISPLAY2, /* These are the base clocks (inputs to the Tegra SOC) */ CLOCK_ID_32KHZ, @@ -30,7 +31,6 @@ enum clock_id { CLOCK_ID_CLK_M, CLOCK_ID_COUNT, /* number of PLLs */ - CLOCK_ID_DISPLAY2, /* Tegra3, placeholder */ CLOCK_ID_NONE = -1, }; diff --git a/arch/arm/include/asm/arch-tegra30/pinmux.h b/arch/arm/include/asm/arch-tegra30/pinmux.h index 1261943f58..686417d5b3 100644 --- a/arch/arm/include/asm/arch-tegra30/pinmux.h +++ b/arch/arm/include/asm/arch-tegra30/pinmux.h @@ -390,6 +390,387 @@ enum pmux_func { PMUX_FUNC_COUNT, }; +static const char * const tegra_pinctrl_to_pingrp[] = { + [PMUX_PINGRP_ULPI_DATA0_PO1] = "ulpi_data0_po1", + [PMUX_PINGRP_ULPI_DATA1_PO2] = "ulpi_data1_po2", + [PMUX_PINGRP_ULPI_DATA2_PO3] = "ulpi_data2_po3", + [PMUX_PINGRP_ULPI_DATA3_PO4] = "ulpi_data3_po4", + [PMUX_PINGRP_ULPI_DATA4_PO5] = "ulpi_data4_po5", + [PMUX_PINGRP_ULPI_DATA5_PO6] = "ulpi_data5_po6", + [PMUX_PINGRP_ULPI_DATA6_PO7] = "ulpi_data6_po7", + [PMUX_PINGRP_ULPI_DATA7_PO0] = "ulpi_data7_po0", + [PMUX_PINGRP_ULPI_CLK_PY0] = "ulpi_clk_py0", + [PMUX_PINGRP_ULPI_DIR_PY1] = "ulpi_dir_py1", + [PMUX_PINGRP_ULPI_NXT_PY2] = "ulpi_nxt_py2", + [PMUX_PINGRP_ULPI_STP_PY3] = "ulpi_stp_py3", + [PMUX_PINGRP_DAP3_FS_PP0] = "dap3_fs_pp0", + [PMUX_PINGRP_DAP3_DIN_PP1] = "dap3_din_pp1", + [PMUX_PINGRP_DAP3_DOUT_PP2] = "dap3_dout_pp2", + [PMUX_PINGRP_DAP3_SCLK_PP3] = "dap3_sclk_pp3", + [PMUX_PINGRP_PV0] = "pv0", + [PMUX_PINGRP_PV1] = "pv1", + [PMUX_PINGRP_SDMMC1_CLK_PZ0] = "sdmmc1_clk_pz0", + [PMUX_PINGRP_SDMMC1_CMD_PZ1] = "sdmmc1_cmd_pz1", + [PMUX_PINGRP_SDMMC1_DAT3_PY4] = "sdmmc1_dat3_py4", + [PMUX_PINGRP_SDMMC1_DAT2_PY5] = "sdmmc1_dat2_py5", + [PMUX_PINGRP_SDMMC1_DAT1_PY6] = "sdmmc1_dat1_py6", + [PMUX_PINGRP_SDMMC1_DAT0_PY7] = "sdmmc1_dat0_py7", + [PMUX_PINGRP_PV2] = "pv2", + [PMUX_PINGRP_PV3] = "pv3", + [PMUX_PINGRP_CLK2_OUT_PW5] = "clk2_out_pw5", + [PMUX_PINGRP_CLK2_REQ_PCC5] = "clk2_req_pcc5", + [PMUX_PINGRP_LCD_PWR1_PC1] = "lcd_pwr1_pc1", + [PMUX_PINGRP_LCD_PWR2_PC6] = "lcd_pwr2_pc6", + [PMUX_PINGRP_LCD_SDIN_PZ2] = "lcd_sdin_pz2", + [PMUX_PINGRP_LCD_SDOUT_PN5] = "lcd_sdout_pn5", + [PMUX_PINGRP_LCD_WR_N_PZ3] = "lcd_wr_n_pz3", + [PMUX_PINGRP_LCD_CS0_N_PN4] = "lcd_cs0_n_pn4", + [PMUX_PINGRP_LCD_DC0_PN6] = "lcd_dc0_pn6", + [PMUX_PINGRP_LCD_SCK_PZ4] = "lcd_sck_pz4", + [PMUX_PINGRP_LCD_PWR0_PB2] = "lcd_pwr0_pb2", + [PMUX_PINGRP_LCD_PCLK_PB3] = "lcd_pclk_pb3", + [PMUX_PINGRP_LCD_DE_PJ1] = "lcd_de_pj1", + [PMUX_PINGRP_LCD_HSYNC_PJ3] = "lcd_hsync_pj3", + [PMUX_PINGRP_LCD_VSYNC_PJ4] = "lcd_vsync_pj4", + [PMUX_PINGRP_LCD_D0_PE0] = "lcd_d0_pe0", + [PMUX_PINGRP_LCD_D1_PE1] = "lcd_d1_pe1", + [PMUX_PINGRP_LCD_D2_PE2] = "lcd_d2_pe2", + [PMUX_PINGRP_LCD_D3_PE3] = "lcd_d3_pe3", + [PMUX_PINGRP_LCD_D4_PE4] = "lcd_d4_pe4", + [PMUX_PINGRP_LCD_D5_PE5] = "lcd_d5_pe5", + [PMUX_PINGRP_LCD_D6_PE6] = "lcd_d6_pe6", + [PMUX_PINGRP_LCD_D7_PE7] = "lcd_d7_pe7", + [PMUX_PINGRP_LCD_D8_PF0] = "lcd_d8_pf0", + [PMUX_PINGRP_LCD_D9_PF1] = "lcd_d9_pf1", + [PMUX_PINGRP_LCD_D10_PF2] = "lcd_d10_pf2", + [PMUX_PINGRP_LCD_D11_PF3] = "lcd_d11_pf3", + [PMUX_PINGRP_LCD_D12_PF4] = "lcd_d12_pf4", + [PMUX_PINGRP_LCD_D13_PF5] = "lcd_d13_pf5", + [PMUX_PINGRP_LCD_D14_PF6] = "lcd_d14_pf6", + [PMUX_PINGRP_LCD_D15_PF7] = "lcd_d15_pf7", + [PMUX_PINGRP_LCD_D16_PM0] = "lcd_d16_pm0", + [PMUX_PINGRP_LCD_D17_PM1] = "lcd_d17_pm1", + [PMUX_PINGRP_LCD_D18_PM2] = "lcd_d18_pm2", + [PMUX_PINGRP_LCD_D19_PM3] = "lcd_d19_pm3", + [PMUX_PINGRP_LCD_D20_PM4] = "lcd_d20_pm4", + [PMUX_PINGRP_LCD_D21_PM5] = "lcd_d21_pm5", + [PMUX_PINGRP_LCD_D22_PM6] = "lcd_d22_pm6", + [PMUX_PINGRP_LCD_D23_PM7] = "lcd_d23_pm7", + [PMUX_PINGRP_LCD_CS1_N_PW0] = "lcd_cs1_n_pw0", + [PMUX_PINGRP_LCD_M1_PW1] = "lcd_m1_pw1", + [PMUX_PINGRP_LCD_DC1_PD2] = "lcd_dc1_pd2", + [PMUX_PINGRP_HDMI_INT_PN7] = "hdmi_int_pn7", + [PMUX_PINGRP_DDC_SCL_PV4] = "ddc_scl_pv4", + [PMUX_PINGRP_DDC_SDA_PV5] = "ddc_sda_pv5", + [PMUX_PINGRP_CRT_HSYNC_PV6] = "crt_hsync_pv6", + [PMUX_PINGRP_CRT_VSYNC_PV7] = "crt_vsync_pv7", + [PMUX_PINGRP_VI_D0_PT4] = "vi_d0_pt4", + [PMUX_PINGRP_VI_D1_PD5] = "vi_d1_pd5", + [PMUX_PINGRP_VI_D2_PL0] = "vi_d2_pl0", + [PMUX_PINGRP_VI_D3_PL1] = "vi_d3_pl1", + [PMUX_PINGRP_VI_D4_PL2] = "vi_d4_pl2", + [PMUX_PINGRP_VI_D5_PL3] = "vi_d5_pl3", + [PMUX_PINGRP_VI_D6_PL4] = "vi_d6_pl4", + [PMUX_PINGRP_VI_D7_PL5] = "vi_d7_pl5", + [PMUX_PINGRP_VI_D8_PL6] = "vi_d8_pl6", + [PMUX_PINGRP_VI_D9_PL7] = "vi_d9_pl7", + [PMUX_PINGRP_VI_D10_PT2] = "vi_d10_pt2", + [PMUX_PINGRP_VI_D11_PT3] = "vi_d11_pt3", + [PMUX_PINGRP_VI_PCLK_PT0] = "vi_pclk_pt0", + [PMUX_PINGRP_VI_MCLK_PT1] = "vi_mclk_pt1", + [PMUX_PINGRP_VI_VSYNC_PD6] = "vi_vsync_pd6", + [PMUX_PINGRP_VI_HSYNC_PD7] = "vi_hsync_pd7", + [PMUX_PINGRP_UART2_RXD_PC3] = "uart2_rxd_pc3", + [PMUX_PINGRP_UART2_TXD_PC2] = "uart2_txd_pc2", + [PMUX_PINGRP_UART2_RTS_N_PJ6] = "uart2_rts_n_pj6", + [PMUX_PINGRP_UART2_CTS_N_PJ5] = "uart2_cts_n_pj5", + [PMUX_PINGRP_UART3_TXD_PW6] = "uart3_txd_pw6", + [PMUX_PINGRP_UART3_RXD_PW7] = "uart3_rxd_pw7", + [PMUX_PINGRP_UART3_CTS_N_PA1] = "uart3_cts_n_pa1", + [PMUX_PINGRP_UART3_RTS_N_PC0] = "uart3_rts_n_pc0", + [PMUX_PINGRP_PU0] = "pu0", + [PMUX_PINGRP_PU1] = "pu1", + [PMUX_PINGRP_PU2] = "pu2", + [PMUX_PINGRP_PU3] = "pu3", + [PMUX_PINGRP_PU4] = "pu4", + [PMUX_PINGRP_PU5] = "pu5", + [PMUX_PINGRP_PU6] = "pu6", + [PMUX_PINGRP_GEN1_I2C_SDA_PC5] = "gen1_i2c_sda_pc5", + [PMUX_PINGRP_GEN1_I2C_SCL_PC4] = "gen1_i2c_scl_pc4", + [PMUX_PINGRP_DAP4_FS_PP4] = "dap4_fs_pp4", + [PMUX_PINGRP_DAP4_DIN_PP5] = "dap4_din_pp5", + [PMUX_PINGRP_DAP4_DOUT_PP6] = "dap4_dout_pp6", + [PMUX_PINGRP_DAP4_SCLK_PP7] = "dap4_sclk_pp7", + [PMUX_PINGRP_CLK3_OUT_PEE0] = "clk3_out_pee0", + [PMUX_PINGRP_CLK3_REQ_PEE1] = "clk3_req_pee1", + [PMUX_PINGRP_GMI_WP_N_PC7] = "gmi_wp_n_pc7", + [PMUX_PINGRP_GMI_IORDY_PI5] = "gmi_iordy_pi5", + [PMUX_PINGRP_GMI_WAIT_PI7] = "gmi_wait_pi7", + [PMUX_PINGRP_GMI_ADV_N_PK0] = "gmi_adv_n_pk0", + [PMUX_PINGRP_GMI_CLK_PK1] = "gmi_clk_pk1", + [PMUX_PINGRP_GMI_CS0_N_PJ0] = "gmi_cs0_n_pj0", + [PMUX_PINGRP_GMI_CS1_N_PJ2] = "gmi_cs1_n_pj2", + [PMUX_PINGRP_GMI_CS2_N_PK3] = "gmi_cs2_n_pk3", + [PMUX_PINGRP_GMI_CS3_N_PK4] = "gmi_cs3_n_pk4", + [PMUX_PINGRP_GMI_CS4_N_PK2] = "gmi_cs4_n_pk2", + [PMUX_PINGRP_GMI_CS6_N_PI3] = "gmi_cs6_n_pi3", + [PMUX_PINGRP_GMI_CS7_N_PI6] = "gmi_cs7_n_pi6", + [PMUX_PINGRP_GMI_AD0_PG0] = "gmi_ad0_pg0", + [PMUX_PINGRP_GMI_AD1_PG1] = "gmi_ad1_pg1", + [PMUX_PINGRP_GMI_AD2_PG2] = "gmi_ad2_pg2", + [PMUX_PINGRP_GMI_AD3_PG3] = "gmi_ad3_pg3", + [PMUX_PINGRP_GMI_AD4_PG4] = "gmi_ad4_pg4", + [PMUX_PINGRP_GMI_AD5_PG5] = "gmi_ad5_pg5", + [PMUX_PINGRP_GMI_AD6_PG6] = "gmi_ad6_pg6", + [PMUX_PINGRP_GMI_AD7_PG7] = "gmi_ad7_pg7", + [PMUX_PINGRP_GMI_AD8_PH0] = "gmi_ad8_ph0", + [PMUX_PINGRP_GMI_AD9_PH1] = "gmi_ad9_ph1", + [PMUX_PINGRP_GMI_AD10_PH2] = "gmi_ad10_ph2", + [PMUX_PINGRP_GMI_AD11_PH3] = "gmi_ad11_ph3", + [PMUX_PINGRP_GMI_AD12_PH4] = "gmi_ad12_ph4", + [PMUX_PINGRP_GMI_AD13_PH5] = "gmi_ad13_ph5", + [PMUX_PINGRP_GMI_AD14_PH6] = "gmi_ad14_ph6", + [PMUX_PINGRP_GMI_AD15_PH7] = "gmi_ad15_ph7", + [PMUX_PINGRP_GMI_A16_PJ7] = "gmi_a16_pj7", + [PMUX_PINGRP_GMI_A17_PB0] = "gmi_a17_pb0", + [PMUX_PINGRP_GMI_A18_PB1] = "gmi_a18_pb1", + [PMUX_PINGRP_GMI_A19_PK7] = "gmi_a19_pk7", + [PMUX_PINGRP_GMI_WR_N_PI0] = "gmi_wr_n_pi0", + [PMUX_PINGRP_GMI_OE_N_PI1] = "gmi_oe_n_pi1", + [PMUX_PINGRP_GMI_DQS_PI2] = "gmi_dqs_pi2", + [PMUX_PINGRP_GMI_RST_N_PI4] = "gmi_rst_n_pi4", + [PMUX_PINGRP_GEN2_I2C_SCL_PT5] = "gen2_i2c_scl_pt5", + [PMUX_PINGRP_GEN2_I2C_SDA_PT6] = "gen2_i2c_sda_pt6", + [PMUX_PINGRP_SDMMC4_CLK_PCC4] = "sdmmc4_clk_pcc4", + [PMUX_PINGRP_SDMMC4_CMD_PT7] = "sdmmc4_cmd_pt7", + [PMUX_PINGRP_SDMMC4_DAT0_PAA0] = "sdmmc4_dat0_paa0", + [PMUX_PINGRP_SDMMC4_DAT1_PAA1] = "sdmmc4_dat1_paa1", + [PMUX_PINGRP_SDMMC4_DAT2_PAA2] = "sdmmc4_dat2_paa2", + [PMUX_PINGRP_SDMMC4_DAT3_PAA3] = "sdmmc4_dat3_paa3", + [PMUX_PINGRP_SDMMC4_DAT4_PAA4] = "sdmmc4_dat4_paa4", + [PMUX_PINGRP_SDMMC4_DAT5_PAA5] = "sdmmc4_dat5_paa5", + [PMUX_PINGRP_SDMMC4_DAT6_PAA6] = "sdmmc4_dat6_paa6", + [PMUX_PINGRP_SDMMC4_DAT7_PAA7] = "sdmmc4_dat7_paa7", + [PMUX_PINGRP_SDMMC4_RST_N_PCC3] = "sdmmc4_rst_n_pcc3", + [PMUX_PINGRP_CAM_MCLK_PCC0] = "cam_mclk_pcc0", + [PMUX_PINGRP_PCC1] = "pcc1", + [PMUX_PINGRP_PBB0] = "pbb0", + [PMUX_PINGRP_CAM_I2C_SCL_PBB1] = "cam_i2c_scl_pbb1", + [PMUX_PINGRP_CAM_I2C_SDA_PBB2] = "cam_i2c_sda_pbb2", + [PMUX_PINGRP_PBB3] = "pbb3", + [PMUX_PINGRP_PBB4] = "pbb4", + [PMUX_PINGRP_PBB5] = "pbb5", + [PMUX_PINGRP_PBB6] = "pbb6", + [PMUX_PINGRP_PBB7] = "pbb7", + [PMUX_PINGRP_PCC2] = "pcc2", + [PMUX_PINGRP_JTAG_RTCK_PU7] = "jtag_rtck_pu7", + [PMUX_PINGRP_PWR_I2C_SCL_PZ6] = "pwr_i2c_scl_pz6", + [PMUX_PINGRP_PWR_I2C_SDA_PZ7] = "pwr_i2c_sda_pz7", + [PMUX_PINGRP_KB_ROW0_PR0] = "kb_row0_pr0", + [PMUX_PINGRP_KB_ROW1_PR1] = "kb_row1_pr1", + [PMUX_PINGRP_KB_ROW2_PR2] = "kb_row2_pr2", + [PMUX_PINGRP_KB_ROW3_PR3] = "kb_row3_pr3", + [PMUX_PINGRP_KB_ROW4_PR4] = "kb_row4_pr4", + [PMUX_PINGRP_KB_ROW5_PR5] = "kb_row5_pr5", + [PMUX_PINGRP_KB_ROW6_PR6] = "kb_row6_pr6", + [PMUX_PINGRP_KB_ROW7_PR7] = "kb_row7_pr7", + [PMUX_PINGRP_KB_ROW8_PS0] = "kb_row8_ps0", + [PMUX_PINGRP_KB_ROW9_PS1] = "kb_row9_ps1", + [PMUX_PINGRP_KB_ROW10_PS2] = "kb_row10_ps2", + [PMUX_PINGRP_KB_ROW11_PS3] = "kb_row11_ps3", + [PMUX_PINGRP_KB_ROW12_PS4] = "kb_row12_ps4", + [PMUX_PINGRP_KB_ROW13_PS5] = "kb_row13_ps5", + [PMUX_PINGRP_KB_ROW14_PS6] = "kb_row14_ps6", + [PMUX_PINGRP_KB_ROW15_PS7] = "kb_row15_ps7", + [PMUX_PINGRP_KB_COL0_PQ0] = "kb_col0_pq0", + [PMUX_PINGRP_KB_COL1_PQ1] = "kb_col1_pq1", + [PMUX_PINGRP_KB_COL2_PQ2] = "kb_col2_pq2", + [PMUX_PINGRP_KB_COL3_PQ3] = "kb_col3_pq3", + [PMUX_PINGRP_KB_COL4_PQ4] = "kb_col4_pq4", + [PMUX_PINGRP_KB_COL5_PQ5] = "kb_col5_pq5", + [PMUX_PINGRP_KB_COL6_PQ6] = "kb_col6_pq6", + [PMUX_PINGRP_KB_COL7_PQ7] = "kb_col7_pq7", + [PMUX_PINGRP_CLK_32K_OUT_PA0] = "clk_32k_out_pa0", + [PMUX_PINGRP_SYS_CLK_REQ_PZ5] = "sys_clk_req_pz5", + [PMUX_PINGRP_CORE_PWR_REQ] = "core_pwr_req", + [PMUX_PINGRP_CPU_PWR_REQ] = "cpu_pwr_req", + [PMUX_PINGRP_PWR_INT_N] = "pwr_int_n", + [PMUX_PINGRP_CLK_32K_IN] = "clk_32k_in", + [PMUX_PINGRP_OWR] = "owr", + [PMUX_PINGRP_DAP1_FS_PN0] = "dap1_fs_pn0", + [PMUX_PINGRP_DAP1_DIN_PN1] = "dap1_din_pn1", + [PMUX_PINGRP_DAP1_DOUT_PN2] = "dap1_dout_pn2", + [PMUX_PINGRP_DAP1_SCLK_PN3] = "dap1_sclk_pn3", + [PMUX_PINGRP_CLK1_REQ_PEE2] = "clk1_req_pee2", + [PMUX_PINGRP_CLK1_OUT_PW4] = "clk1_out_pw4", + [PMUX_PINGRP_SPDIF_IN_PK6] = "spdif_in_pk6", + [PMUX_PINGRP_SPDIF_OUT_PK5] = "spdif_out_pk5", + [PMUX_PINGRP_DAP2_FS_PA2] = "dap2_fs_pa2", + [PMUX_PINGRP_DAP2_DIN_PA4] = "dap2_din_pa4", + [PMUX_PINGRP_DAP2_DOUT_PA5] = "dap2_dout_pa5", + [PMUX_PINGRP_DAP2_SCLK_PA3] = "dap2_sclk_pa3", + [PMUX_PINGRP_SPI2_MOSI_PX0] = "spi2_mosi_px0", + [PMUX_PINGRP_SPI2_MISO_PX1] = "spi2_miso_px1", + [PMUX_PINGRP_SPI2_CS0_N_PX3] = "spi2_cs0_n_px3", + [PMUX_PINGRP_SPI2_SCK_PX2] = "spi2_sck_px2", + [PMUX_PINGRP_SPI1_MOSI_PX4] = "spi1_mosi_px4", + [PMUX_PINGRP_SPI1_SCK_PX5] = "spi1_sck_px5", + [PMUX_PINGRP_SPI1_CS0_N_PX6] = "spi1_cs0_n_px6", + [PMUX_PINGRP_SPI1_MISO_PX7] = "spi1_miso_px7", + [PMUX_PINGRP_SPI2_CS1_N_PW2] = "spi2_cs1_n_pw2", + [PMUX_PINGRP_SPI2_CS2_N_PW3] = "spi2_cs2_n_pw3", + [PMUX_PINGRP_SDMMC3_CLK_PA6] = "sdmmc3_clk_pa6", + [PMUX_PINGRP_SDMMC3_CMD_PA7] = "sdmmc3_cmd_pa7", + [PMUX_PINGRP_SDMMC3_DAT0_PB7] = "sdmmc3_dat0_pb7", + [PMUX_PINGRP_SDMMC3_DAT1_PB6] = "sdmmc3_dat1_pb6", + [PMUX_PINGRP_SDMMC3_DAT2_PB5] = "sdmmc3_dat2_pb5", + [PMUX_PINGRP_SDMMC3_DAT3_PB4] = "sdmmc3_dat3_pb4", + [PMUX_PINGRP_SDMMC3_DAT4_PD1] = "sdmmc3_dat4_pd1", + [PMUX_PINGRP_SDMMC3_DAT5_PD0] = "sdmmc3_dat5_pd0", + [PMUX_PINGRP_SDMMC3_DAT6_PD3] = "sdmmc3_dat6_pd3", + [PMUX_PINGRP_SDMMC3_DAT7_PD4] = "sdmmc3_dat7_pd4", + [PMUX_PINGRP_PEX_L0_PRSNT_N_PDD0] = "pex_l0_prsnt_n_pdd0", + [PMUX_PINGRP_PEX_L0_RST_N_PDD1] = "pex_l0_rst_n_pdd1", + [PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2] = "pex_l0_clkreq_n_pdd2", + [PMUX_PINGRP_PEX_WAKE_N_PDD3] = "pex_wake_n_pdd3", + [PMUX_PINGRP_PEX_L1_PRSNT_N_PDD4] = "pex_l1_prsnt_n_pdd4", + [PMUX_PINGRP_PEX_L1_RST_N_PDD5] = "pex_l1_rst_n_pdd5", + [PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6] = "pex_l1_clkreq_n_pdd6", + [PMUX_PINGRP_PEX_L2_PRSNT_N_PDD7] = "pex_l2_prsnt_n_pdd7", + [PMUX_PINGRP_PEX_L2_RST_N_PCC6] = "pex_l2_rst_n_pcc6", + [PMUX_PINGRP_PEX_L2_CLKREQ_N_PCC7] = "pex_l2_clkreq_n_pcc7", + [PMUX_PINGRP_HDMI_CEC_PEE3] = "hdmi_cec_pee3", +}; + +static const char * const tegra_pinctrl_to_drvgrp[] = { + [PMUX_DRVGRP_AO1] = "drive_ao1", + [PMUX_DRVGRP_AO2] = "drive_ao2", + [PMUX_DRVGRP_AT1] = "drive_at1", + [PMUX_DRVGRP_AT2] = "drive_at2", + [PMUX_DRVGRP_AT3] = "drive_at3", + [PMUX_DRVGRP_AT4] = "drive_at4", + [PMUX_DRVGRP_AT5] = "drive_at5", + [PMUX_DRVGRP_CDEV1] = "drive_cdev1", + [PMUX_DRVGRP_CDEV2] = "drive_cdev2", + [PMUX_DRVGRP_CSUS] = "drive_csus", + [PMUX_DRVGRP_DAP1] = "drive_dap1", + [PMUX_DRVGRP_DAP2] = "drive_dap2", + [PMUX_DRVGRP_DAP3] = "drive_dap3", + [PMUX_DRVGRP_DAP4] = "drive_dap4", + [PMUX_DRVGRP_DBG] = "drive_dbg", + [PMUX_DRVGRP_LCD1] = "drive_lcd1", + [PMUX_DRVGRP_LCD2] = "drive_lcd2", + [PMUX_DRVGRP_SDIO2] = "drive_sdio2", + [PMUX_DRVGRP_SDIO3] = "drive_sdio3", + [PMUX_DRVGRP_SPI] = "drive_spi", + [PMUX_DRVGRP_UAA] = "drive_uaa", + [PMUX_DRVGRP_UAB] = "drive_uab", + [PMUX_DRVGRP_UART2] = "drive_uart2", + [PMUX_DRVGRP_UART3] = "drive_uart3", + [PMUX_DRVGRP_VI1] = "drive_vi1", + [PMUX_DRVGRP_SDIO1] = "drive_sdio1", + [PMUX_DRVGRP_CRT] = "drive_crt", + [PMUX_DRVGRP_DDC] = "drive_ddc", + [PMUX_DRVGRP_GMA] = "drive_gma", + [PMUX_DRVGRP_GMB] = "drive_gmb", + [PMUX_DRVGRP_GMC] = "drive_gmc", + [PMUX_DRVGRP_GMD] = "drive_gmd", + [PMUX_DRVGRP_GME] = "drive_gme", + [PMUX_DRVGRP_GMF] = "drive_gmf", + [PMUX_DRVGRP_GMG] = "drive_gmg", + [PMUX_DRVGRP_GMH] = "drive_gmh", + [PMUX_DRVGRP_OWR] = "drive_owr", + [PMUX_DRVGRP_UDA] = "drive_uda", + [PMUX_DRVGRP_GPV] = "drive_gpv", + [PMUX_DRVGRP_DEV3] = "drive_dev3", + [PMUX_DRVGRP_CEC] = "drive_cec", +}; + +static const char * const tegra_pinctrl_to_func[] = { + [PMUX_FUNC_DEFAULT] = "default", + [PMUX_FUNC_BLINK] = "blink", + [PMUX_FUNC_CEC] = "cec", + [PMUX_FUNC_CLK_12M_OUT] = "clk_12m_out", + [PMUX_FUNC_CLK_32K_IN] = "clk_32k_in", + [PMUX_FUNC_CORE_PWR_REQ] = "core_pwr_req", + [PMUX_FUNC_CPU_PWR_REQ] = "cpu_pwr_req", + [PMUX_FUNC_CRT] = "crt", + [PMUX_FUNC_DAP] = "dap", + [PMUX_FUNC_DDR] = "ddr", + [PMUX_FUNC_DEV3] = "dev3", + [PMUX_FUNC_DISPLAYA] = "displaya", + [PMUX_FUNC_DISPLAYB] = "displayb", + [PMUX_FUNC_DTV] = "dtv", + [PMUX_FUNC_EXTPERIPH1] = "extperiph1", + [PMUX_FUNC_EXTPERIPH2] = "extperiph2", + [PMUX_FUNC_EXTPERIPH3] = "extperiph3", + [PMUX_FUNC_GMI] = "gmi", + [PMUX_FUNC_GMI_ALT] = "gmi_alt", + [PMUX_FUNC_HDA] = "hda", + [PMUX_FUNC_HDCP] = "hdcp", + [PMUX_FUNC_HDMI] = "hdmi", + [PMUX_FUNC_HSI] = "hsi", + [PMUX_FUNC_I2C1] = "i2c1", + [PMUX_FUNC_I2C2] = "i2c2", + [PMUX_FUNC_I2C3] = "i2c3", + [PMUX_FUNC_I2C4] = "i2c4", + [PMUX_FUNC_I2CPWR] = "i2cpwr", + [PMUX_FUNC_I2S0] = "i2s0", + [PMUX_FUNC_I2S1] = "i2s1", + [PMUX_FUNC_I2S2] = "i2s2", + [PMUX_FUNC_I2S3] = "i2s3", + [PMUX_FUNC_I2S4] = "i2s4", + [PMUX_FUNC_INVALID] = "invalid", + [PMUX_FUNC_KBC] = "kbc", + [PMUX_FUNC_MIO] = "mio", + [PMUX_FUNC_NAND] = "nand", + [PMUX_FUNC_NAND_ALT] = "nand_alt", + [PMUX_FUNC_OWR] = "owr", + [PMUX_FUNC_PCIE] = "pcie", + [PMUX_FUNC_PWM0] = "pwm0", + [PMUX_FUNC_PWM1] = "pwm1", + [PMUX_FUNC_PWM2] = "pwm2", + [PMUX_FUNC_PWM3] = "pwm3", + [PMUX_FUNC_PWR_INT_N] = "pwr_int_n", + [PMUX_FUNC_RTCK] = "rtck", + [PMUX_FUNC_SATA] = "sata", + [PMUX_FUNC_SDMMC1] = "sdmmc1", + [PMUX_FUNC_SDMMC2] = "sdmmc2", + [PMUX_FUNC_SDMMC3] = "sdmmc3", + [PMUX_FUNC_SDMMC4] = "sdmmc4", + [PMUX_FUNC_SPDIF] = "spdif", + [PMUX_FUNC_SPI1] = "spi1", + [PMUX_FUNC_SPI2] = "spi2", + [PMUX_FUNC_SPI2_ALT] = "spi2_alt", + [PMUX_FUNC_SPI3] = "spi3", + [PMUX_FUNC_SPI4] = "spi4", + [PMUX_FUNC_SPI5] = "spi5", + [PMUX_FUNC_SPI6] = "spi6", + [PMUX_FUNC_SYSCLK] = "sysclk", + [PMUX_FUNC_TEST] = "test", + [PMUX_FUNC_TRACE] = "trace", + [PMUX_FUNC_UARTA] = "uarta", + [PMUX_FUNC_UARTB] = "uartb", + [PMUX_FUNC_UARTC] = "uartc", + [PMUX_FUNC_UARTD] = "uartd", + [PMUX_FUNC_UARTE] = "uarte", + [PMUX_FUNC_ULPI] = "ulpi", + [PMUX_FUNC_VGP1] = "vgp1", + [PMUX_FUNC_VGP2] = "vgp2", + [PMUX_FUNC_VGP3] = "vgp3", + [PMUX_FUNC_VGP4] = "vgp4", + [PMUX_FUNC_VGP5] = "vgp5", + [PMUX_FUNC_VGP6] = "vgp6", + [PMUX_FUNC_VI] = "vi", + [PMUX_FUNC_VI_ALT1] = "vi_alt1", + [PMUX_FUNC_VI_ALT2] = "vi_alt2", + [PMUX_FUNC_VI_ALT3] = "vi_alt3", + [PMUX_FUNC_RSVD1] = "rsvd1", + [PMUX_FUNC_RSVD2] = "rsvd2", + [PMUX_FUNC_RSVD3] = "rsvd3", + [PMUX_FUNC_RSVD4] = "rsvd4", +}; + #define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868 #define TEGRA_PMX_SOC_HAS_DRVGRPS #define TEGRA_PMX_GRPS_HAVE_LPMD diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index f273778128..b18885f4c1 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -33,9 +33,6 @@ config TEGRA_IVC config TEGRA_MC bool -config TEGRA_PINCTRL - bool - config TEGRA_PMC bool @@ -61,7 +58,6 @@ config TEGRA_COMMON select OF_CONTROL select SPI select SYSRESET - select SPL_SYSRESET if SPL select SYSRESET_TEGRA imply CMD_DM imply CRC32_VERIFY @@ -76,9 +72,15 @@ config TEGRA_ARMV7_COMMON bool "Tegra 32-bit common options" select BINMAN select CPU_V7A + select PINCTRL + select PINCTRL_TEGRA select SPL select SPL_BOARD_INIT if SPL + select SPL_DM if SPL + select SPL_PINCTRL if SPL + select SPL_PINCTRL_TEGRA if SPL select SPL_SKIP_LOWLEVEL_INIT_ONLY if SPL + select SPL_SYSRESET if SPL select SUPPORT_SPL select TIMER select TEGRA_CLKRST @@ -87,7 +89,6 @@ config TEGRA_ARMV7_COMMON select TEGRA_GP_PADCTRL select TEGRA_MC select TEGRA_NO_BPMP - select TEGRA_PINCTRL select TEGRA_PMC select TEGRA_TIMER @@ -134,6 +135,8 @@ config TEGRA124 config TEGRA210 bool "Tegra210 family" select GICV2 + select PINCTRL + select PINCTRL_TEGRA select TIMER select TEGRA_ARMV8_COMMON select TEGRA_CLKRST @@ -141,7 +144,6 @@ config TEGRA210 select TEGRA_GP_PADCTRL select TEGRA_MC select TEGRA_NO_BPMP - select TEGRA_PINCTRL select TEGRA_PMC select TEGRA_PMC_SECURE select TEGRA_TIMER @@ -194,7 +196,7 @@ config TEGRA_SPI choice prompt "UART to use for console" - depends on TEGRA_PINCTRL + depends on PINCTRL_TEGRA default TEGRA_ENABLE_UARTA config TEGRA_ENABLE_UARTA diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index a5733b0bf6..1d22dc3942 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -17,7 +17,6 @@ obj-y += board.o board2.o obj-y += cache.o obj-$(CONFIG_TEGRA_CLKRST) += clock.o obj-$(CONFIG_$(SPL_)TEGRA_CRYPTO) += crypto.o -obj-$(CONFIG_TEGRA_PINCTRL) += pinmux-common.o obj-$(CONFIG_TEGRA_PMC) += powergate.o obj-y += xusb-padctl-dummy.o diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index f8b61a2b3e..9224743d0e 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -17,7 +17,7 @@ #if IS_ENABLED(CONFIG_TEGRA_CLKRST) #include <asm/arch/clock.h> #endif -#if IS_ENABLED(CONFIG_TEGRA_PINCTRL) +#if CONFIG_IS_ENABLED(PINCTRL_TEGRA) #include <asm/arch/funcmux.h> #endif #if IS_ENABLED(CONFIG_TEGRA_MC) @@ -163,7 +163,7 @@ int dram_init(void) return 0; } -#if IS_ENABLED(CONFIG_TEGRA_PINCTRL) +#if CONFIG_IS_ENABLED(PINCTRL_TEGRA) static int uart_configs[] = { #if defined(CONFIG_TEGRA20) #if defined(CONFIG_TEGRA_UARTA_UAA_UAB) @@ -235,7 +235,7 @@ static void setup_uarts(int uart_ids) void board_init_uart_f(void) { -#if IS_ENABLED(CONFIG_TEGRA_PINCTRL) +#if CONFIG_IS_ENABLED(PINCTRL_TEGRA) int uart_ids = 0; /* bit mask of which UART ids to enable */ #ifdef CONFIG_TEGRA_ENABLE_UARTA diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 8ad76d5edf..adea12c9b7 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -34,7 +34,7 @@ #if IS_ENABLED(CONFIG_TEGRA_CLKRST) #include <asm/arch/clock.h> #endif -#if IS_ENABLED(CONFIG_TEGRA_PINCTRL) +#if CONFIG_IS_ENABLED(PINCTRL_TEGRA) #include <asm/arch/funcmux.h> #include <asm/arch/pinmux.h> #endif diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 966009f375..575da2bdb5 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -128,14 +128,14 @@ unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn, struct clk_pll_simple *simple_pll = NULL; u32 misc_data, data; - if (clkid < (enum clock_id)TEGRA_CLK_PLLS) { + if (clkid < (enum clock_id)TEGRA_CLK_PLLS) pll = get_pll(clkid); - } else { + else simple_pll = clock_get_simple_pll(clkid); - if (!simple_pll) { - debug("%s: Uknown simple PLL %d\n", __func__, clkid); - return 0; - } + + if (!simple_pll && !pll) { + log_err("Unknown PLL id %d\n", clkid); + return 0; } /* @@ -542,7 +542,8 @@ unsigned int __weak clk_m_get_rate(unsigned int parent_rate) unsigned clock_get_rate(enum clock_id clkid) { - struct clk_pll *pll; + struct clk_pll *pll = NULL; + struct clk_pll_simple *simple_pll = NULL; u32 base, divm; u64 parent_rate, rate; struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid]; @@ -554,10 +555,20 @@ unsigned clock_get_rate(enum clock_id clkid) if (clkid == CLOCK_ID_CLK_M) return clk_m_get_rate(parent_rate); - pll = get_pll(clkid); - if (!pll) + if (clkid < (enum clock_id)TEGRA_CLK_PLLS) + pll = get_pll(clkid); + else + simple_pll = clock_get_simple_pll(clkid); + + if (!simple_pll && !pll) { + log_err("Unknown PLL id %d\n", clkid); return 0; - base = readl(&pll->pll_base); + } + + if (pll) + base = readl(&pll->pll_base); + else + base = readl(&simple_pll->pll_base); rate = parent_rate * ((base >> pllinfo->n_shift) & pllinfo->n_mask); divm = (base >> pllinfo->m_shift) & pllinfo->m_mask; @@ -599,12 +610,24 @@ unsigned clock_get_rate(enum clock_id clkid) int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon) { u32 base_reg, misc_reg; - struct clk_pll *pll; + struct clk_pll *pll = NULL; + struct clk_pll_simple *simple_pll = NULL; struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid]; - pll = get_pll(clkid); + if (clkid < (enum clock_id)TEGRA_CLK_PLLS) + pll = get_pll(clkid); + else + simple_pll = clock_get_simple_pll(clkid); - base_reg = readl(&pll->pll_base); + if (!simple_pll && !pll) { + log_err("Unknown PLL id %d\n", clkid); + return 0; + } + + if (pll) + base_reg = readl(&pll->pll_base); + else + base_reg = readl(&simple_pll->pll_base); /* Set BYPASS, m, n and p to PLL_BASE */ base_reg &= ~(pllinfo->m_mask << pllinfo->m_shift); @@ -631,21 +654,37 @@ int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon) } base_reg |= PLL_BYPASS_MASK; - writel(base_reg, &pll->pll_base); + if (pll) + writel(base_reg, &pll->pll_base); + else + writel(base_reg, &simple_pll->pll_base); /* Set cpcon (KCP) to PLL_MISC */ - misc_reg = readl(&pll->pll_misc); + if (pll) + misc_reg = readl(&pll->pll_misc); + else + misc_reg = readl(&simple_pll->pll_misc); + misc_reg &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift); misc_reg |= cpcon << pllinfo->kcp_shift; - writel(misc_reg, &pll->pll_misc); + if (pll) + writel(misc_reg, &pll->pll_misc); + else + writel(misc_reg, &simple_pll->pll_misc); /* Enable PLL */ base_reg |= PLL_ENABLE_MASK; - writel(base_reg, &pll->pll_base); + if (pll) + writel(base_reg, &pll->pll_base); + else + writel(base_reg, &simple_pll->pll_base); /* Disable BYPASS */ base_reg &= ~PLL_BYPASS_MASK; - writel(base_reg, &pll->pll_base); + if (pll) + writel(base_reg, &pll->pll_base); + else + writel(base_reg, &simple_pll->pll_base); return 0; } @@ -729,6 +768,9 @@ void clock_init(void) pll_rate[CLOCK_ID_SFROM32KHZ] = 32768; pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC); pll_rate[CLOCK_ID_CLK_M] = clock_get_rate(CLOCK_ID_CLK_M); +#ifndef CONFIG_TEGRA20 + pll_rate[CLOCK_ID_DISPLAY2] = clock_get_rate(CLOCK_ID_DISPLAY2); +#endif debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]); debug("CLKM = %d\n", pll_rate[CLOCK_ID_CLK_M]); diff --git a/arch/arm/mach-tegra/pinmux-common.c b/arch/arm/mach-tegra/pinmux-common.c deleted file mode 100644 index 16b03bfe7b..0000000000 --- a/arch/arm/mach-tegra/pinmux-common.c +++ /dev/null @@ -1,755 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - * Copyright (c) 2011 The Chromium OS Authors. - */ - -#include <common.h> -#include <log.h> -#include <asm/io.h> -#include <asm/arch/pinmux.h> - -/* return 1 if a pingrp is in range */ -#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PMUX_PINGRP_COUNT)) - -/* return 1 if a pmux_func is in range */ -#define pmux_func_isvalid(func) \ - (((func) >= 0) && ((func) < PMUX_FUNC_COUNT)) - -/* return 1 if a pin_pupd_is in range */ -#define pmux_pin_pupd_isvalid(pupd) \ - (((pupd) >= PMUX_PULL_NORMAL) && ((pupd) <= PMUX_PULL_UP)) - -/* return 1 if a pin_tristate_is in range */ -#define pmux_pin_tristate_isvalid(tristate) \ - (((tristate) >= PMUX_TRI_NORMAL) && ((tristate) <= PMUX_TRI_TRISTATE)) - -#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT -/* return 1 if a pin_io_is in range */ -#define pmux_pin_io_isvalid(io) \ - (((io) >= PMUX_PIN_OUTPUT) && ((io) <= PMUX_PIN_INPUT)) -#endif - -#ifdef TEGRA_PMX_PINS_HAVE_LOCK -/* return 1 if a pin_lock is in range */ -#define pmux_pin_lock_isvalid(lock) \ - (((lock) >= PMUX_PIN_LOCK_DISABLE) && ((lock) <= PMUX_PIN_LOCK_ENABLE)) -#endif - -#ifdef TEGRA_PMX_PINS_HAVE_OD -/* return 1 if a pin_od is in range */ -#define pmux_pin_od_isvalid(od) \ - (((od) >= PMUX_PIN_OD_DISABLE) && ((od) <= PMUX_PIN_OD_ENABLE)) -#endif - -#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET -/* return 1 if a pin_ioreset_is in range */ -#define pmux_pin_ioreset_isvalid(ioreset) \ - (((ioreset) >= PMUX_PIN_IO_RESET_DISABLE) && \ - ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE)) -#endif - -#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL -/* return 1 if a pin_rcv_sel_is in range */ -#define pmux_pin_rcv_sel_isvalid(rcv_sel) \ - (((rcv_sel) >= PMUX_PIN_RCV_SEL_NORMAL) && \ - ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH)) -#endif - -#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV -/* return 1 if a pin_e_io_hv is in range */ -#define pmux_pin_e_io_hv_isvalid(e_io_hv) \ - (((e_io_hv) >= PMUX_PIN_E_IO_HV_NORMAL) && \ - ((e_io_hv) <= PMUX_PIN_E_IO_HV_HIGH)) -#endif - -#ifdef TEGRA_PMX_GRPS_HAVE_LPMD -#define pmux_lpmd_isvalid(lpm) \ - (((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X)) -#endif - -#if defined(TEGRA_PMX_PINS_HAVE_SCHMT) || defined(TEGRA_PMX_GRPS_HAVE_SCHMT) -#define pmux_schmt_isvalid(schmt) \ - (((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE)) -#endif - -#if defined(TEGRA_PMX_PINS_HAVE_HSM) || defined(TEGRA_PMX_GRPS_HAVE_HSM) -#define pmux_hsm_isvalid(hsm) \ - (((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE)) -#endif - -#define _R(offset) (u32 *)((unsigned long)NV_PA_APB_MISC_BASE + (offset)) - -#if defined(CONFIG_TEGRA20) - -#define MUX_REG(grp) _R(0x80 + ((tegra_soc_pingroups[grp].ctl_id / 16) * 4)) -#define MUX_SHIFT(grp) ((tegra_soc_pingroups[grp].ctl_id % 16) * 2) - -#define PULL_REG(grp) _R(0xa0 + ((tegra_soc_pingroups[grp].pull_id / 16) * 4)) -#define PULL_SHIFT(grp) ((tegra_soc_pingroups[grp].pull_id % 16) * 2) - -#define TRI_REG(grp) _R(0x14 + (((grp) / 32) * 4)) -#define TRI_SHIFT(grp) ((grp) % 32) - -#else - -#define REG(pin) _R(0x3000 + ((pin) * 4)) - -#define MUX_REG(pin) REG(pin) -#define MUX_SHIFT(pin) 0 - -#define PULL_REG(pin) REG(pin) -#define PULL_SHIFT(pin) 2 - -#define TRI_REG(pin) REG(pin) -#define TRI_SHIFT(pin) 4 - -#endif /* CONFIG_TEGRA20 */ - -#define DRV_REG(group) _R(TEGRA_PMX_SOC_DRV_GROUP_BASE_REG + ((group) * 4)) - -#define MIPIPADCTRL_REG(group) _R(TEGRA_PMX_SOC_MIPIPADCTRL_BASE_REG + ((group) * 4)) - -/* - * We could force arch-tegraNN/pinmux.h to define all of these. However, - * that's a lot of defines, and for now it's manageable to just put a - * special case here. It's possible this decision will change with future - * SoCs. - */ -#ifdef CONFIG_TEGRA210 -#define IO_SHIFT 6 -#define LOCK_SHIFT 7 -#ifdef TEGRA_PMX_PINS_HAVE_HSM -#define HSM_SHIFT 9 -#endif -#define E_IO_HV_SHIFT 10 -#define OD_SHIFT 11 -#ifdef TEGRA_PMX_PINS_HAVE_SCHMT -#define SCHMT_SHIFT 12 -#endif -#else -#define IO_SHIFT 5 -#define OD_SHIFT 6 -#define LOCK_SHIFT 7 -#define IO_RESET_SHIFT 8 -#define RCV_SEL_SHIFT 9 -#endif - -#ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING -/* This register/field only exists on Tegra114 and later */ -#define APB_MISC_PP_PINMUX_GLOBAL_0 0x40 -#define CLAMP_INPUTS_WHEN_TRISTATED 1 - -void pinmux_set_tristate_input_clamping(void) -{ - u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0); - - setbits_le32(reg, CLAMP_INPUTS_WHEN_TRISTATED); -} - -void pinmux_clear_tristate_input_clamping(void) -{ - u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0); - - clrbits_le32(reg, CLAMP_INPUTS_WHEN_TRISTATED); -} -#endif - -void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func) -{ - u32 *reg = MUX_REG(pin); - int i, mux = -1; - u32 val; - - if (func == PMUX_FUNC_DEFAULT) - return; - - /* Error check on pin and func */ - assert(pmux_pingrp_isvalid(pin)); - assert(pmux_func_isvalid(func)); - - if (func >= PMUX_FUNC_RSVD1) { - mux = (func - PMUX_FUNC_RSVD1) & 3; - } else { - /* Search for the appropriate function */ - for (i = 0; i < 4; i++) { - if (tegra_soc_pingroups[pin].funcs[i] == func) { - mux = i; - break; - } - } - } - assert(mux != -1); - - val = readl(reg); - val &= ~(3 << MUX_SHIFT(pin)); - val |= (mux << MUX_SHIFT(pin)); - writel(val, reg); -} - -void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd) -{ - u32 *reg = PULL_REG(pin); - u32 val; - - /* Error check on pin and pupd */ - assert(pmux_pingrp_isvalid(pin)); - assert(pmux_pin_pupd_isvalid(pupd)); - - val = readl(reg); - val &= ~(3 << PULL_SHIFT(pin)); - val |= (pupd << PULL_SHIFT(pin)); - writel(val, reg); -} - -static void pinmux_set_tristate(enum pmux_pingrp pin, int tri) -{ - u32 *reg = TRI_REG(pin); - u32 val; - - /* Error check on pin */ - assert(pmux_pingrp_isvalid(pin)); - assert(pmux_pin_tristate_isvalid(tri)); - - val = readl(reg); - if (tri == PMUX_TRI_TRISTATE) - val |= (1 << TRI_SHIFT(pin)); - else - val &= ~(1 << TRI_SHIFT(pin)); - writel(val, reg); -} - -void pinmux_tristate_enable(enum pmux_pingrp pin) -{ - pinmux_set_tristate(pin, PMUX_TRI_TRISTATE); -} - -void pinmux_tristate_disable(enum pmux_pingrp pin) -{ - pinmux_set_tristate(pin, PMUX_TRI_NORMAL); -} - -#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT -void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io) -{ - u32 *reg = REG(pin); - u32 val; - - if (io == PMUX_PIN_NONE) - return; - - /* Error check on pin and io */ - assert(pmux_pingrp_isvalid(pin)); - assert(pmux_pin_io_isvalid(io)); - - val = readl(reg); - if (io == PMUX_PIN_INPUT) - val |= (io & 1) << IO_SHIFT; - else - val &= ~(1 << IO_SHIFT); - writel(val, reg); -} -#endif - -#ifdef TEGRA_PMX_PINS_HAVE_LOCK -static void pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock) -{ - u32 *reg = REG(pin); - u32 val; - - if (lock == PMUX_PIN_LOCK_DEFAULT) - return; - - /* Error check on pin and lock */ - assert(pmux_pingrp_isvalid(pin)); - assert(pmux_pin_lock_isvalid(lock)); - - val = readl(reg); - if (lock == PMUX_PIN_LOCK_ENABLE) { - val |= (1 << LOCK_SHIFT); - } else { - if (val & (1 << LOCK_SHIFT)) - printf("%s: Cannot clear LOCK bit!\n", __func__); - val &= ~(1 << LOCK_SHIFT); - } - writel(val, reg); - - return; -} -#endif - -#ifdef TEGRA_PMX_PINS_HAVE_OD -static void pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od) -{ - u32 *reg = REG(pin); - u32 val; - - if (od == PMUX_PIN_OD_DEFAULT) - return; - - /* Error check on pin and od */ - assert(pmux_pingrp_isvalid(pin)); - assert(pmux_pin_od_isvalid(od)); - - val = readl(reg); - if (od == PMUX_PIN_OD_ENABLE) - val |= (1 << OD_SHIFT); - else - val &= ~(1 << OD_SHIFT); - writel(val, reg); - - return; -} -#endif - -#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET -static void pinmux_set_ioreset(enum pmux_pingrp pin, - enum pmux_pin_ioreset ioreset) -{ - u32 *reg = REG(pin); - u32 val; - - if (ioreset == PMUX_PIN_IO_RESET_DEFAULT) - return; - - /* Error check on pin and ioreset */ - assert(pmux_pingrp_isvalid(pin)); - assert(pmux_pin_ioreset_isvalid(ioreset)); - - val = readl(reg); - if (ioreset == PMUX_PIN_IO_RESET_ENABLE) - val |= (1 << IO_RESET_SHIFT); - else - val &= ~(1 << IO_RESET_SHIFT); - writel(val, reg); - - return; -} -#endif - -#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL -static void pinmux_set_rcv_sel(enum pmux_pingrp pin, - enum pmux_pin_rcv_sel rcv_sel) -{ - u32 *reg = REG(pin); - u32 val; - - if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT) - return; - - /* Error check on pin and rcv_sel */ - assert(pmux_pingrp_isvalid(pin)); - assert(pmux_pin_rcv_sel_isvalid(rcv_sel)); - - val = readl(reg); - if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH) - val |= (1 << RCV_SEL_SHIFT); - else - val &= ~(1 << RCV_SEL_SHIFT); - writel(val, reg); - - return; -} -#endif - -#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV -static void pinmux_set_e_io_hv(enum pmux_pingrp pin, - enum pmux_pin_e_io_hv e_io_hv) -{ - u32 *reg = REG(pin); - u32 val; - - if (e_io_hv == PMUX_PIN_E_IO_HV_DEFAULT) - return; - - /* Error check on pin and e_io_hv */ - assert(pmux_pingrp_isvalid(pin)); - assert(pmux_pin_e_io_hv_isvalid(e_io_hv)); - - val = readl(reg); - if (e_io_hv == PMUX_PIN_E_IO_HV_HIGH) - val |= (1 << E_IO_HV_SHIFT); - else - val &= ~(1 << E_IO_HV_SHIFT); - writel(val, reg); - - return; -} -#endif - -#ifdef TEGRA_PMX_PINS_HAVE_SCHMT -static void pinmux_set_schmt(enum pmux_pingrp pin, enum pmux_schmt schmt) -{ - u32 *reg = REG(grp); - u32 val; - - /* NONE means unspecified/do not change/use POR value */ - if (schmt == PMUX_SCHMT_NONE) - return; - - /* Error check pad */ - assert(pmux_pingrp_isvalid(pin)); - assert(pmux_schmt_isvalid(schmt)); - - val = readl(reg); - if (schmt == PMUX_SCHMT_ENABLE) - val |= (1 << SCHMT_SHIFT); - else - val &= ~(1 << SCHMT_SHIFT); - writel(val, reg); - - return; -} -#endif - -#ifdef TEGRA_PMX_PINS_HAVE_HSM -static void pinmux_set_hsm(enum pmux_pingrp pin, enum pmux_hsm hsm) -{ - u32 *reg = REG(grp); - u32 val; - - /* NONE means unspecified/do not change/use POR value */ - if (hsm == PMUX_HSM_NONE) - return; - - /* Error check pad */ - assert(pmux_pingrp_isvalid(pin)); - assert(pmux_hsm_isvalid(hsm)); - - val = readl(reg); - if (hsm == PMUX_HSM_ENABLE) - val |= (1 << HSM_SHIFT); - else - val &= ~(1 << HSM_SHIFT); - writel(val, reg); - - return; -} -#endif - -static void pinmux_config_pingrp(const struct pmux_pingrp_config *config) -{ - enum pmux_pingrp pin = config->pingrp; - - pinmux_set_func(pin, config->func); - pinmux_set_pullupdown(pin, config->pull); - pinmux_set_tristate(pin, config->tristate); -#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT - pinmux_set_io(pin, config->io); -#endif -#ifdef TEGRA_PMX_PINS_HAVE_LOCK - pinmux_set_lock(pin, config->lock); -#endif -#ifdef TEGRA_PMX_PINS_HAVE_OD - pinmux_set_od(pin, config->od); -#endif -#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET - pinmux_set_ioreset(pin, config->ioreset); -#endif -#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL - pinmux_set_rcv_sel(pin, config->rcv_sel); -#endif -#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV - pinmux_set_e_io_hv(pin, config->e_io_hv); -#endif -#ifdef TEGRA_PMX_PINS_HAVE_SCHMT - pinmux_set_schmt(pin, config->schmt); -#endif -#ifdef TEGRA_PMX_PINS_HAVE_HSM - pinmux_set_hsm(pin, config->hsm); -#endif -} - -void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config, - int len) -{ - int i; - - for (i = 0; i < len; i++) - pinmux_config_pingrp(&config[i]); -} - -#ifdef TEGRA_PMX_SOC_HAS_DRVGRPS - -#define pmux_drvgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_DRVGRP_COUNT)) - -#define pmux_slw_isvalid(slw) \ - (((slw) >= PMUX_SLWF_MIN) && ((slw) <= PMUX_SLWF_MAX)) - -#define pmux_drv_isvalid(drv) \ - (((drv) >= PMUX_DRVUP_MIN) && ((drv) <= PMUX_DRVUP_MAX)) - -#ifdef TEGRA_PMX_GRPS_HAVE_HSM -#define HSM_SHIFT 2 -#endif -#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT -#define SCHMT_SHIFT 3 -#endif -#ifdef TEGRA_PMX_GRPS_HAVE_LPMD -#define LPMD_SHIFT 4 -#define LPMD_MASK (3 << LPMD_SHIFT) -#endif -/* - * Note that the following DRV* and SLW* defines are accurate for many drive - * groups on many SoCs. We really need a per-group data structure to solve - * this, since the fields are in different positions/sizes in different - * registers (for different groups). - * - * On Tegra30/114/124, the DRV*_SHIFT values vary. - * On Tegra30, the SLW*_SHIFT values vary. - * On Tegra30/114/124/210, the DRV*_MASK values vary, although the values - * below are wide enough to cover the widest fields, and hopefully don't - * interfere with any other fields. - * On Tegra30, the SLW*_MASK values vary, but we can't use a value that's - * wide enough to cover all cases, since that would cause the field to - * overlap with other fields in the narrower cases. - */ -#define DRVDN_SHIFT 12 -#define DRVDN_MASK (0x7F << DRVDN_SHIFT) -#define DRVUP_SHIFT 20 -#define DRVUP_MASK (0x7F << DRVUP_SHIFT) -#define SLWR_SHIFT 28 -#define SLWR_MASK (3 << SLWR_SHIFT) -#define SLWF_SHIFT 30 -#define SLWF_MASK (3 << SLWF_SHIFT) - -static void pinmux_set_drvup_slwf(enum pmux_drvgrp grp, int slwf) -{ - u32 *reg = DRV_REG(grp); - u32 val; - - /* NONE means unspecified/do not change/use POR value */ - if (slwf == PMUX_SLWF_NONE) - return; - - /* Error check on pad and slwf */ - assert(pmux_drvgrp_isvalid(grp)); - assert(pmux_slw_isvalid(slwf)); - - val = readl(reg); - val &= ~SLWF_MASK; - val |= (slwf << SLWF_SHIFT); - writel(val, reg); - - return; -} - -static void pinmux_set_drvdn_slwr(enum pmux_drvgrp grp, int slwr) -{ - u32 *reg = DRV_REG(grp); - u32 val; - - /* NONE means unspecified/do not change/use POR value */ - if (slwr == PMUX_SLWR_NONE) - return; - - /* Error check on pad and slwr */ - assert(pmux_drvgrp_isvalid(grp)); - assert(pmux_slw_isvalid(slwr)); - - val = readl(reg); - val &= ~SLWR_MASK; - val |= (slwr << SLWR_SHIFT); - writel(val, reg); - - return; -} - -static void pinmux_set_drvup(enum pmux_drvgrp grp, int drvup) -{ - u32 *reg = DRV_REG(grp); - u32 val; - - /* NONE means unspecified/do not change/use POR value */ - if (drvup == PMUX_DRVUP_NONE) - return; - - /* Error check on pad and drvup */ - assert(pmux_drvgrp_isvalid(grp)); - assert(pmux_drv_isvalid(drvup)); - - val = readl(reg); - val &= ~DRVUP_MASK; - val |= (drvup << DRVUP_SHIFT); - writel(val, reg); - - return; -} - -static void pinmux_set_drvdn(enum pmux_drvgrp grp, int drvdn) -{ - u32 *reg = DRV_REG(grp); - u32 val; - - /* NONE means unspecified/do not change/use POR value */ - if (drvdn == PMUX_DRVDN_NONE) - return; - - /* Error check on pad and drvdn */ - assert(pmux_drvgrp_isvalid(grp)); - assert(pmux_drv_isvalid(drvdn)); - - val = readl(reg); - val &= ~DRVDN_MASK; - val |= (drvdn << DRVDN_SHIFT); - writel(val, reg); - - return; -} - -#ifdef TEGRA_PMX_GRPS_HAVE_LPMD -static void pinmux_set_lpmd(enum pmux_drvgrp grp, enum pmux_lpmd lpmd) -{ - u32 *reg = DRV_REG(grp); - u32 val; - - /* NONE means unspecified/do not change/use POR value */ - if (lpmd == PMUX_LPMD_NONE) - return; - - /* Error check pad and lpmd value */ - assert(pmux_drvgrp_isvalid(grp)); - assert(pmux_lpmd_isvalid(lpmd)); - - val = readl(reg); - val &= ~LPMD_MASK; - val |= (lpmd << LPMD_SHIFT); - writel(val, reg); - - return; -} -#endif - -#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT -static void pinmux_set_schmt(enum pmux_drvgrp grp, enum pmux_schmt schmt) -{ - u32 *reg = DRV_REG(grp); - u32 val; - - /* NONE means unspecified/do not change/use POR value */ - if (schmt == PMUX_SCHMT_NONE) - return; - - /* Error check pad */ - assert(pmux_drvgrp_isvalid(grp)); - assert(pmux_schmt_isvalid(schmt)); - - val = readl(reg); - if (schmt == PMUX_SCHMT_ENABLE) - val |= (1 << SCHMT_SHIFT); - else - val &= ~(1 << SCHMT_SHIFT); - writel(val, reg); - - return; -} -#endif - -#ifdef TEGRA_PMX_GRPS_HAVE_HSM -static void pinmux_set_hsm(enum pmux_drvgrp grp, enum pmux_hsm hsm) -{ - u32 *reg = DRV_REG(grp); - u32 val; - - /* NONE means unspecified/do not change/use POR value */ - if (hsm == PMUX_HSM_NONE) - return; - - /* Error check pad */ - assert(pmux_drvgrp_isvalid(grp)); - assert(pmux_hsm_isvalid(hsm)); - - val = readl(reg); - if (hsm == PMUX_HSM_ENABLE) - val |= (1 << HSM_SHIFT); - else - val &= ~(1 << HSM_SHIFT); - writel(val, reg); - - return; -} -#endif - -static void pinmux_config_drvgrp(const struct pmux_drvgrp_config *config) -{ - enum pmux_drvgrp grp = config->drvgrp; - - pinmux_set_drvup_slwf(grp, config->slwf); - pinmux_set_drvdn_slwr(grp, config->slwr); - pinmux_set_drvup(grp, config->drvup); - pinmux_set_drvdn(grp, config->drvdn); -#ifdef TEGRA_PMX_GRPS_HAVE_LPMD - pinmux_set_lpmd(grp, config->lpmd); -#endif -#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT - pinmux_set_schmt(grp, config->schmt); -#endif -#ifdef TEGRA_PMX_GRPS_HAVE_HSM - pinmux_set_hsm(grp, config->hsm); -#endif -} - -void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config, - int len) -{ - int i; - - for (i = 0; i < len; i++) - pinmux_config_drvgrp(&config[i]); -} -#endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */ - -#ifdef TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS - -#define pmux_mipipadctrlgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_MIPIPADCTRLGRP_COUNT)) - -static void pinmux_mipipadctrl_set_func(enum pmux_mipipadctrlgrp grp, - enum pmux_func func) -{ - u32 *reg = MIPIPADCTRL_REG(grp); - int i, mux = -1; - u32 val; - - if (func == PMUX_FUNC_DEFAULT) - return; - - /* Error check grp and func */ - assert(pmux_mipipadctrlgrp_isvalid(grp)); - assert(pmux_func_isvalid(func)); - - if (func >= PMUX_FUNC_RSVD1) { - mux = (func - PMUX_FUNC_RSVD1) & 1; - } else { - /* Search for the appropriate function */ - for (i = 0; i < 2; i++) { - if (tegra_soc_mipipadctrl_groups[grp].funcs[i] - == func) { - mux = i; - break; - } - } - } - assert(mux != -1); - - val = readl(reg); - val &= ~(1 << 1); - val |= (mux << 1); - writel(val, reg); -} - -static void pinmux_config_mipipadctrlgrp(const struct pmux_mipipadctrlgrp_config *config) -{ - enum pmux_mipipadctrlgrp grp = config->grp; - - pinmux_mipipadctrl_set_func(grp, config->func); -} - -void pinmux_config_mipipadctrlgrp_table( - const struct pmux_mipipadctrlgrp_config *config, int len) -{ - int i; - - for (i = 0; i < len; i++) - pinmux_config_mipipadctrlgrp(&config[i]); -} -#endif /* TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS */ diff --git a/arch/arm/mach-tegra/tegra114/Makefile b/arch/arm/mach-tegra/tegra114/Makefile index 0e8f32cbd6..346d6cb569 100644 --- a/arch/arm/mach-tegra/tegra114/Makefile +++ b/arch/arm/mach-tegra/tegra114/Makefile @@ -4,4 +4,4 @@ obj-$(CONFIG_SPL_BUILD) += cpu.o -obj-y += clock.o funcmux.o pinmux.o +obj-y += clock.o diff --git a/arch/arm/mach-tegra/tegra114/clock.c b/arch/arm/mach-tegra/tegra114/clock.c index 8ad71f590f..418ad48ddc 100644 --- a/arch/arm/mach-tegra/tegra114/clock.c +++ b/arch/arm/mach-tegra/tegra114/clock.c @@ -457,6 +457,8 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */ { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */ + { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, + .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD2 */ }; /* @@ -671,6 +673,9 @@ enum clock_id clk_id_to_pll_id(int clk_id) case TEGRA114_CLK_PLL_D: case TEGRA114_CLK_PLL_D_OUT0: return CLOCK_ID_DISPLAY; + case TEGRA114_CLK_PLL_D2: + case TEGRA114_CLK_PLL_D2_OUT0: + return CLOCK_ID_DISPLAY2; case TEGRA114_CLK_PLL_X: return CLOCK_ID_XCPU; case TEGRA114_CLK_PLL_E_OUT0: @@ -768,6 +773,23 @@ void arch_timer_init(void) debug("%s: TSC CNTCR = 0x%08X\n", __func__, val); } +struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + + switch (clkid) { + case CLOCK_ID_XCPU: + case CLOCK_ID_EPCI: + case CLOCK_ID_SFROM32KHZ: + return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE]; + case CLOCK_ID_DISPLAY2: + return &clkrst->plld2; + default: + return NULL; + } +} + struct periph_clk_init periph_clk_init_table[] = { { PERIPH_ID_SBC1, CLOCK_ID_PERIPH }, { PERIPH_ID_SBC2, CLOCK_ID_PERIPH }, diff --git a/arch/arm/mach-tegra/tegra114/funcmux.c b/arch/arm/mach-tegra/tegra114/funcmux.c deleted file mode 100644 index 23a27c8688..0000000000 --- a/arch/arm/mach-tegra/tegra114/funcmux.c +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - */ - -/* Tegra114 high-level function multiplexing */ - -#include <common.h> -#include <log.h> -#include <asm/arch/clock.h> -#include <asm/arch/funcmux.h> -#include <asm/arch/pinmux.h> - -int funcmux_select(enum periph_id id, int config) -{ - int bad_config = config != FUNCMUX_DEFAULT; - - switch (id) { - case PERIPH_ID_UART4: - switch (config) { - case FUNCMUX_UART4_GMI: - pinmux_set_func(PMUX_PINGRP_GMI_A16_PJ7, - PMUX_FUNC_UARTD); - pinmux_set_func(PMUX_PINGRP_GMI_A17_PB0, - PMUX_FUNC_UARTD); - pinmux_set_func(PMUX_PINGRP_GMI_A18_PB1, - PMUX_FUNC_UARTD); - pinmux_set_func(PMUX_PINGRP_GMI_A19_PK7, - PMUX_FUNC_UARTD); - - pinmux_set_io(PMUX_PINGRP_GMI_A16_PJ7, PMUX_PIN_OUTPUT); - pinmux_set_io(PMUX_PINGRP_GMI_A17_PB0, PMUX_PIN_INPUT); - pinmux_set_io(PMUX_PINGRP_GMI_A18_PB1, PMUX_PIN_INPUT); - pinmux_set_io(PMUX_PINGRP_GMI_A19_PK7, PMUX_PIN_OUTPUT); - - pinmux_tristate_disable(PMUX_PINGRP_GMI_A16_PJ7); - pinmux_tristate_disable(PMUX_PINGRP_GMI_A17_PB0); - pinmux_tristate_disable(PMUX_PINGRP_GMI_A18_PB1); - pinmux_tristate_disable(PMUX_PINGRP_GMI_A19_PK7); - break; - } - break; - - /* Add other periph IDs here as needed */ - - default: - debug("%s: invalid periph_id %d", __func__, id); - return -1; - } - - if (bad_config) { - debug("%s: invalid config %d for periph_id %d", __func__, - config, id); - return -1; - } - return 0; -} diff --git a/arch/arm/mach-tegra/tegra114/pinmux.c b/arch/arm/mach-tegra/tegra114/pinmux.c deleted file mode 100644 index 11796602c5..0000000000 --- a/arch/arm/mach-tegra/tegra114/pinmux.c +++ /dev/null @@ -1,292 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/pinmux.h> - -#define PIN(pin, f0, f1, f2, f3) \ - { \ - .funcs = { \ - PMUX_FUNC_##f0, \ - PMUX_FUNC_##f1, \ - PMUX_FUNC_##f2, \ - PMUX_FUNC_##f3, \ - }, \ - } - -#define PIN_RESERVED {} - -static const struct pmux_pingrp_desc tegra114_pingroups[] = { - /* pin, f0, f1, f2, f3 */ - /* Offset 0x3000 */ - PIN(ULPI_DATA0_PO1, SPI3, HSI, UARTA, ULPI), - PIN(ULPI_DATA1_PO2, SPI3, HSI, UARTA, ULPI), - PIN(ULPI_DATA2_PO3, SPI3, HSI, UARTA, ULPI), - PIN(ULPI_DATA3_PO4, SPI3, HSI, UARTA, ULPI), - PIN(ULPI_DATA4_PO5, SPI2, HSI, UARTA, ULPI), - PIN(ULPI_DATA5_PO6, SPI2, HSI, UARTA, ULPI), - PIN(ULPI_DATA6_PO7, SPI2, HSI, UARTA, ULPI), - PIN(ULPI_DATA7_PO0, SPI2, HSI, UARTA, ULPI), - PIN(ULPI_CLK_PY0, SPI1, SPI5, UARTD, ULPI), - PIN(ULPI_DIR_PY1, SPI1, SPI5, UARTD, ULPI), - PIN(ULPI_NXT_PY2, SPI1, SPI5, UARTD, ULPI), - PIN(ULPI_STP_PY3, SPI1, SPI5, UARTD, ULPI), - PIN(DAP3_FS_PP0, I2S2, SPI5, DISPLAYA, DISPLAYB), - PIN(DAP3_DIN_PP1, I2S2, SPI5, DISPLAYA, DISPLAYB), - PIN(DAP3_DOUT_PP2, I2S2, SPI5, DISPLAYA, DISPLAYB), - PIN(DAP3_SCLK_PP3, I2S2, SPI5, DISPLAYA, DISPLAYB), - PIN(PV0, USB, RSVD2, RSVD3, RSVD4), - PIN(PV1, RSVD1, RSVD2, RSVD3, RSVD4), - PIN(SDMMC1_CLK_PZ0, SDMMC1, CLK12, RSVD3, RSVD4), - PIN(SDMMC1_CMD_PZ1, SDMMC1, SPDIF, SPI4, UARTA), - PIN(SDMMC1_DAT3_PY4, SDMMC1, SPDIF, SPI4, UARTA), - PIN(SDMMC1_DAT2_PY5, SDMMC1, PWM0, SPI4, UARTA), - PIN(SDMMC1_DAT1_PY6, SDMMC1, PWM1, SPI4, UARTA), - PIN(SDMMC1_DAT0_PY7, SDMMC1, RSVD2, SPI4, UARTA), - PIN_RESERVED, - PIN_RESERVED, - /* Offset 0x3068 */ - PIN(CLK2_OUT_PW5, EXTPERIPH2, RSVD2, RSVD3, RSVD4), - PIN(CLK2_REQ_PCC5, DAP, RSVD2, RSVD3, RSVD4), - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - /* Offset 0x3110 */ - PIN(HDMI_INT_PN7, RSVD1, RSVD2, RSVD3, RSVD4), - PIN(DDC_SCL_PV4, I2C4, RSVD2, RSVD3, RSVD4), - PIN(DDC_SDA_PV5, I2C4, RSVD2, RSVD3, RSVD4), - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - /* Offset 0x3164 */ - PIN(UART2_RXD_PC3, IRDA, SPDIF, UARTA, SPI4), - PIN(UART2_TXD_PC2, IRDA, SPDIF, UARTA, SPI4), - PIN(UART2_RTS_N_PJ6, UARTA, UARTB, RSVD3, SPI4), - PIN(UART2_CTS_N_PJ5, UARTA, UARTB, RSVD3, SPI4), - PIN(UART3_TXD_PW6, UARTC, RSVD2, RSVD3, SPI4), - PIN(UART3_RXD_PW7, UARTC, RSVD2, RSVD3, SPI4), - PIN(UART3_CTS_N_PA1, UARTC, SDMMC1, DTV, SPI4), - PIN(UART3_RTS_N_PC0, UARTC, PWM0, DTV, DISPLAYA), - PIN(PU0, OWR, UARTA, RSVD3, RSVD4), - PIN(PU1, RSVD1, UARTA, RSVD3, RSVD4), - PIN(PU2, RSVD1, UARTA, RSVD3, RSVD4), - PIN(PU3, PWM0, UARTA, DISPLAYA, DISPLAYB), - PIN(PU4, PWM1, UARTA, DISPLAYA, DISPLAYB), - PIN(PU5, PWM2, UARTA, DISPLAYA, DISPLAYB), - PIN(PU6, PWM3, UARTA, USB, DISPLAYB), - PIN(GEN1_I2C_SDA_PC5, I2C1, RSVD2, RSVD3, RSVD4), - PIN(GEN1_I2C_SCL_PC4, I2C1, RSVD2, RSVD3, RSVD4), - PIN(DAP4_FS_PP4, I2S3, RSVD2, DTV, RSVD4), - PIN(DAP4_DIN_PP5, I2S3, RSVD2, RSVD3, RSVD4), - PIN(DAP4_DOUT_PP6, I2S3, RSVD2, DTV, RSVD4), - PIN(DAP4_SCLK_PP7, I2S3, RSVD2, RSVD3, RSVD4), - PIN(CLK3_OUT_PEE0, EXTPERIPH3, RSVD2, RSVD3, RSVD4), - PIN(CLK3_REQ_PEE1, DEV3, RSVD2, RSVD3, RSVD4), - PIN(GMI_WP_N_PC7, RSVD1, NAND, GMI, GMI_ALT), - PIN(GMI_IORDY_PI5, SDMMC2, RSVD2, GMI, TRACE), - PIN(GMI_WAIT_PI7, SPI4, NAND, GMI, DTV), - PIN(GMI_ADV_N_PK0, RSVD1, NAND, GMI, TRACE), - PIN(GMI_CLK_PK1, SDMMC2, NAND, GMI, TRACE), - PIN(GMI_CS0_N_PJ0, RSVD1, NAND, GMI, USB), - PIN(GMI_CS1_N_PJ2, RSVD1, NAND, GMI, SOC), - PIN(GMI_CS2_N_PK3, SDMMC2, NAND, GMI, TRACE), - PIN(GMI_CS3_N_PK4, SDMMC2, NAND, GMI, GMI_ALT), - PIN(GMI_CS4_N_PK2, USB, NAND, GMI, TRACE), - PIN(GMI_CS6_N_PI3, NAND, NAND_ALT, GMI, SPI4), - PIN(GMI_CS7_N_PI6, NAND, NAND_ALT, GMI, SDMMC2), - PIN(GMI_AD0_PG0, RSVD1, NAND, GMI, RSVD4), - PIN(GMI_AD1_PG1, RSVD1, NAND, GMI, RSVD4), - PIN(GMI_AD2_PG2, RSVD1, NAND, GMI, RSVD4), - PIN(GMI_AD3_PG3, RSVD1, NAND, GMI, RSVD4), - PIN(GMI_AD4_PG4, RSVD1, NAND, GMI, RSVD4), - PIN(GMI_AD5_PG5, RSVD1, NAND, GMI, SPI4), - PIN(GMI_AD6_PG6, RSVD1, NAND, GMI, SPI4), - PIN(GMI_AD7_PG7, RSVD1, NAND, GMI, SPI4), - PIN(GMI_AD8_PH0, PWM0, NAND, GMI, DTV), - PIN(GMI_AD9_PH1, PWM1, NAND, GMI, CLDVFS), - PIN(GMI_AD10_PH2, PWM2, NAND, GMI, CLDVFS), - PIN(GMI_AD11_PH3, PWM3, NAND, GMI, USB), - PIN(GMI_AD12_PH4, SDMMC2, NAND, GMI, RSVD4), - PIN(GMI_AD13_PH5, SDMMC2, NAND, GMI, RSVD4), - PIN(GMI_AD14_PH6, SDMMC2, NAND, GMI, DTV), - PIN(GMI_AD15_PH7, SDMMC2, NAND, GMI, DTV), - PIN(GMI_A16_PJ7, UARTD, TRACE, GMI, GMI_ALT), - PIN(GMI_A17_PB0, UARTD, RSVD2, GMI, TRACE), - PIN(GMI_A18_PB1, UARTD, RSVD2, GMI, TRACE), - PIN(GMI_A19_PK7, UARTD, SPI4, GMI, TRACE), - PIN(GMI_WR_N_PI0, RSVD1, NAND, GMI, SPI4), - PIN(GMI_OE_N_PI1, RSVD1, NAND, GMI, SOC), - PIN(GMI_DQS_P_PJ3, SDMMC2, NAND, GMI, TRACE), - PIN(GMI_RST_N_PI4, NAND, NAND_ALT, GMI, RSVD4), - PIN(GEN2_I2C_SCL_PT5, I2C2, RSVD2, GMI, RSVD4), - PIN(GEN2_I2C_SDA_PT6, I2C2, RSVD2, GMI, RSVD4), - PIN(SDMMC4_CLK_PCC4, SDMMC4, RSVD2, GMI, RSVD4), - PIN(SDMMC4_CMD_PT7, SDMMC4, RSVD2, GMI, RSVD4), - PIN(SDMMC4_DAT0_PAA0, SDMMC4, SPI3, GMI, RSVD4), - PIN(SDMMC4_DAT1_PAA1, SDMMC4, SPI3, GMI, RSVD4), - PIN(SDMMC4_DAT2_PAA2, SDMMC4, SPI3, GMI, RSVD4), - PIN(SDMMC4_DAT3_PAA3, SDMMC4, SPI3, GMI, RSVD4), - PIN(SDMMC4_DAT4_PAA4, SDMMC4, SPI3, GMI, RSVD4), - PIN(SDMMC4_DAT5_PAA5, SDMMC4, SPI3, GMI, RSVD4), - PIN(SDMMC4_DAT6_PAA6, SDMMC4, SPI3, GMI, RSVD4), - PIN(SDMMC4_DAT7_PAA7, SDMMC4, RSVD2, GMI, RSVD4), - PIN_RESERVED, - /* Offset 0x3284 */ - PIN(CAM_MCLK_PCC0, VI, VI_ALT1, VI_ALT3, RSVD4), - PIN(PCC1, I2S4, RSVD2, RSVD3, RSVD4), - PIN(PBB0, I2S4, VI, VI_ALT1, VI_ALT3), - PIN(CAM_I2C_SCL_PBB1, VGP1, I2C3, RSVD3, RSVD4), - PIN(CAM_I2C_SDA_PBB2, VGP2, I2C3, RSVD3, RSVD4), - PIN(PBB3, VGP3, DISPLAYA, DISPLAYB, RSVD4), - PIN(PBB4, VGP4, DISPLAYA, DISPLAYB, RSVD4), - PIN(PBB5, VGP5, DISPLAYA, DISPLAYB, RSVD4), - PIN(PBB6, VGP6, DISPLAYA, DISPLAYB, RSVD4), - PIN(PBB7, I2S4, RSVD2, RSVD3, RSVD4), - PIN(PCC2, I2S4, RSVD2, RSVD3, RSVD4), - PIN(JTAG_RTCK, RTCK, RSVD2, RSVD3, RSVD4), - PIN(PWR_I2C_SCL_PZ6, I2CPWR, RSVD2, RSVD3, RSVD4), - PIN(PWR_I2C_SDA_PZ7, I2CPWR, RSVD2, RSVD3, RSVD4), - PIN(KB_ROW0_PR0, KBC, RSVD2, RSVD3, RSVD4), - PIN(KB_ROW1_PR1, KBC, RSVD2, RSVD3, RSVD4), - PIN(KB_ROW2_PR2, KBC, RSVD2, RSVD3, RSVD4), - PIN(KB_ROW3_PR3, KBC, DISPLAYA, RSVD3, DISPLAYB), - PIN(KB_ROW4_PR4, KBC, DISPLAYA, SPI2, DISPLAYB), - PIN(KB_ROW5_PR5, KBC, DISPLAYA, SPI2, DISPLAYB), - PIN(KB_ROW6_PR6, KBC, DISPLAYA, DISPLAYA_ALT, DISPLAYB), - PIN(KB_ROW7_PR7, KBC, RSVD2, CLDVFS, UARTA), - PIN(KB_ROW8_PS0, KBC, RSVD2, CLDVFS, UARTA), - PIN(KB_ROW9_PS1, KBC, RSVD2, RSVD3, UARTA), - PIN(KB_ROW10_PS2, KBC, RSVD2, RSVD3, UARTA), - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - /* Offset 0x32fc */ - PIN(KB_COL0_PQ0, KBC, USB, SPI2, EMC_DLL), - PIN(KB_COL1_PQ1, KBC, RSVD2, SPI2, EMC_DLL), - PIN(KB_COL2_PQ2, KBC, RSVD2, SPI2, RSVD4), - PIN(KB_COL3_PQ3, KBC, DISPLAYA, PWM2, UARTA), - PIN(KB_COL4_PQ4, KBC, OWR, SDMMC3, UARTA), - PIN(KB_COL5_PQ5, KBC, RSVD2, SDMMC1, RSVD4), - PIN(KB_COL6_PQ6, KBC, RSVD2, SPI2, RSVD4), - PIN(KB_COL7_PQ7, KBC, RSVD2, SPI2, RSVD4), - PIN(CLK_32K_OUT_PA0, BLINK, SOC, RSVD3, RSVD4), - PIN(SYS_CLK_REQ_PZ5, SYSCLK, RSVD2, RSVD3, RSVD4), - PIN(CORE_PWR_REQ, PWRON, RSVD2, RSVD3, RSVD4), - PIN(CPU_PWR_REQ, CPU, RSVD2, RSVD3, RSVD4), - PIN(PWR_INT_N, PMI, RSVD2, RSVD3, RSVD4), - PIN(CLK_32K_IN, CLK, RSVD2, RSVD3, RSVD4), - PIN(OWR, OWR, RSVD2, RSVD3, RSVD4), - PIN(DAP1_FS_PN0, I2S0, HDA, GMI, RSVD4), - PIN(DAP1_DIN_PN1, I2S0, HDA, GMI, RSVD4), - PIN(DAP1_DOUT_PN2, I2S0, HDA, GMI, RSVD4), - PIN(DAP1_SCLK_PN3, I2S0, HDA, GMI, RSVD4), - PIN(CLK1_REQ_PEE2, DAP, DAP1, RSVD3, RSVD4), - PIN(CLK1_OUT_PW4, EXTPERIPH1, DAP2, RSVD3, RSVD4), - PIN(SPDIF_IN_PK6, SPDIF, USB, RSVD3, RSVD4), - PIN(SPDIF_OUT_PK5, SPDIF, RSVD2, RSVD3, RSVD4), - PIN(DAP2_FS_PA2, I2S1, HDA, RSVD3, RSVD4), - PIN(DAP2_DIN_PA4, I2S1, HDA, RSVD3, RSVD4), - PIN(DAP2_DOUT_PA5, I2S1, HDA, RSVD3, RSVD4), - PIN(DAP2_SCLK_PA3, I2S1, HDA, RSVD3, RSVD4), - PIN(DVFS_PWM_PX0, SPI6, CLDVFS, RSVD3, RSVD4), - PIN(GPIO_X1_AUD_PX1, SPI6, RSVD2, RSVD3, RSVD4), - PIN(GPIO_X3_AUD_PX3, SPI6, SPI1, RSVD3, RSVD4), - PIN(DVFS_CLK_PX2, SPI6, CLDVFS, RSVD3, RSVD4), - PIN(GPIO_X4_AUD_PX4, RSVD1, SPI1, SPI2, DAP2), - PIN(GPIO_X5_AUD_PX5, RSVD1, SPI1, SPI2, RSVD4), - PIN(GPIO_X6_AUD_PX6, SPI6, SPI1, SPI2, RSVD4), - PIN(GPIO_X7_AUD_PX7, RSVD1, SPI1, SPI2, RSVD4), - PIN_RESERVED, - PIN_RESERVED, - /* Offset 0x3390 */ - PIN(SDMMC3_CLK_PA6, SDMMC3, RSVD2, RSVD3, SPI3), - PIN(SDMMC3_CMD_PA7, SDMMC3, PWM3, UARTA, SPI3), - PIN(SDMMC3_DAT0_PB7, SDMMC3, RSVD2, RSVD3, SPI3), - PIN(SDMMC3_DAT1_PB6, SDMMC3, PWM2, UARTA, SPI3), - PIN(SDMMC3_DAT2_PB5, SDMMC3, PWM1, DISPLAYA, SPI3), - PIN(SDMMC3_DAT3_PB4, SDMMC3, PWM0, DISPLAYB, SPI3), - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - /* Offset 0x33e0 */ - PIN(HDMI_CEC_PEE3, CEC, SDMMC3, RSVD3, SOC), - PIN(SDMMC1_WP_N_PV3, SDMMC1, CLK12, SPI4, UARTA), - PIN(SDMMC3_CD_N_PV2, SDMMC3, OWR, RSVD3, RSVD4), - PIN(GPIO_W2_AUD_PW2, SPI6, RSVD2, SPI2, I2C1), - PIN(GPIO_W3_AUD_PW3, SPI6, SPI1, SPI2, I2C1), - PIN(USB_VBUS_EN0_PN4, USB, RSVD2, RSVD3, RSVD4), - PIN(USB_VBUS_EN1_PN5, USB, RSVD2, RSVD3, RSVD4), - PIN(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, RSVD2, RSVD3, RSVD4), - PIN(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, RSVD2, RSVD3, RSVD4), - PIN(GMI_CLK_LB, SDMMC2, NAND, GMI, RSVD4), - PIN(RESET_OUT_N, RSVD1, RSVD2, RSVD3, RESET_OUT_N), -}; -const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra114_pingroups; diff --git a/arch/arm/mach-tegra/tegra124/Makefile b/arch/arm/mach-tegra/tegra124/Makefile index d275dafdc4..6ea511e7b2 100644 --- a/arch/arm/mach-tegra/tegra124/Makefile +++ b/arch/arm/mach-tegra/tegra124/Makefile @@ -8,8 +8,6 @@ obj-$(CONFIG_SPL_BUILD) += cpu.o obj-y += clock.o -obj-y += funcmux.o -obj-y += pinmux.o obj-y += pmc.o obj-y += xusb-padctl.o obj-y += ../xusb-padctl-common.o diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c index ca9549a318..ed8b6d9638 100644 --- a/arch/arm/mach-tegra/tegra124/clock.c +++ b/arch/arm/mach-tegra/tegra124/clock.c @@ -1189,10 +1189,16 @@ struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid) struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; - if (clkid == CLOCK_ID_DP) + switch (clkid) { + case CLOCK_ID_XCPU: + case CLOCK_ID_EPCI: + case CLOCK_ID_SFROM32KHZ: + return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE]; + case CLOCK_ID_DP: return &clkrst->plldp; - - return NULL; + default: + return NULL; + } } struct periph_clk_init periph_clk_init_table[] = { diff --git a/arch/arm/mach-tegra/tegra124/funcmux.c b/arch/arm/mach-tegra/tegra124/funcmux.c deleted file mode 100644 index e7ad85fde2..0000000000 --- a/arch/arm/mach-tegra/tegra124/funcmux.c +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2013 - * NVIDIA Corporation <www.nvidia.com> - */ - -/* Tegra124 high-level function multiplexing */ - -#include <common.h> -#include <log.h> -#include <asm/arch/clock.h> -#include <asm/arch/funcmux.h> -#include <asm/arch/pinmux.h> - -int funcmux_select(enum periph_id id, int config) -{ - int bad_config = config != FUNCMUX_DEFAULT; - - switch (id) { - case PERIPH_ID_UART4: - switch (config) { - case FUNCMUX_UART4_GPIO: /* TXD,RXD,CTS,RTS */ - pinmux_set_func(PMUX_PINGRP_PJ7, PMUX_FUNC_UARTD); - pinmux_set_func(PMUX_PINGRP_PB0, PMUX_FUNC_UARTD); - pinmux_set_func(PMUX_PINGRP_PB1, PMUX_FUNC_UARTD); - pinmux_set_func(PMUX_PINGRP_PK7, PMUX_FUNC_UARTD); - - pinmux_set_io(PMUX_PINGRP_PJ7, PMUX_PIN_OUTPUT); - pinmux_set_io(PMUX_PINGRP_PB0, PMUX_PIN_INPUT); - pinmux_set_io(PMUX_PINGRP_PB1, PMUX_PIN_INPUT); - pinmux_set_io(PMUX_PINGRP_PK7, PMUX_PIN_OUTPUT); - - pinmux_tristate_disable(PMUX_PINGRP_PJ7); - pinmux_tristate_disable(PMUX_PINGRP_PB0); - pinmux_tristate_disable(PMUX_PINGRP_PB1); - pinmux_tristate_disable(PMUX_PINGRP_PK7); - break; - } - break; - - case PERIPH_ID_UART1: - switch (config) { - case FUNCMUX_UART1_KBC: - pinmux_set_func(PMUX_PINGRP_KB_ROW9_PS1, - PMUX_FUNC_UARTA); - pinmux_set_func(PMUX_PINGRP_KB_ROW10_PS2, - PMUX_FUNC_UARTA); - - pinmux_set_io(PMUX_PINGRP_KB_ROW9_PS1, PMUX_PIN_OUTPUT); - pinmux_set_io(PMUX_PINGRP_KB_ROW10_PS2, PMUX_PIN_INPUT); - - pinmux_tristate_disable(PMUX_PINGRP_KB_ROW9_PS1); - pinmux_tristate_disable(PMUX_PINGRP_KB_ROW10_PS2); - break; - } - break; - - /* Add other periph IDs here as needed */ - - default: - debug("%s: invalid periph_id %d", __func__, id); - return -1; - } - - if (bad_config) { - debug("%s: invalid config %d for periph_id %d", __func__, - config, id); - return -1; - } - return 0; -} diff --git a/arch/arm/mach-tegra/tegra124/pinmux.c b/arch/arm/mach-tegra/tegra124/pinmux.c deleted file mode 100644 index 261ce64b20..0000000000 --- a/arch/arm/mach-tegra/tegra124/pinmux.c +++ /dev/null @@ -1,322 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/pinmux.h> - -#define PIN(pin, f0, f1, f2, f3) \ - { \ - .funcs = { \ - PMUX_FUNC_##f0, \ - PMUX_FUNC_##f1, \ - PMUX_FUNC_##f2, \ - PMUX_FUNC_##f3, \ - }, \ - } - -#define PIN_RESERVED {} - -static const struct pmux_pingrp_desc tegra124_pingroups[] = { - /* pin, f0, f1, f2, f3 */ - /* Offset 0x3000 */ - PIN(ULPI_DATA0_PO1, SPI3, HSI, UARTA, ULPI), - PIN(ULPI_DATA1_PO2, SPI3, HSI, UARTA, ULPI), - PIN(ULPI_DATA2_PO3, SPI3, HSI, UARTA, ULPI), - PIN(ULPI_DATA3_PO4, SPI3, HSI, UARTA, ULPI), - PIN(ULPI_DATA4_PO5, SPI2, HSI, UARTA, ULPI), - PIN(ULPI_DATA5_PO6, SPI2, HSI, UARTA, ULPI), - PIN(ULPI_DATA6_PO7, SPI2, HSI, UARTA, ULPI), - PIN(ULPI_DATA7_PO0, SPI2, HSI, UARTA, ULPI), - PIN(ULPI_CLK_PY0, SPI1, SPI5, UARTD, ULPI), - PIN(ULPI_DIR_PY1, SPI1, SPI5, UARTD, ULPI), - PIN(ULPI_NXT_PY2, SPI1, SPI5, UARTD, ULPI), - PIN(ULPI_STP_PY3, SPI1, SPI5, UARTD, ULPI), - PIN(DAP3_FS_PP0, I2S2, SPI5, DISPLAYA, DISPLAYB), - PIN(DAP3_DIN_PP1, I2S2, SPI5, DISPLAYA, DISPLAYB), - PIN(DAP3_DOUT_PP2, I2S2, SPI5, DISPLAYA, RSVD4), - PIN(DAP3_SCLK_PP3, I2S2, SPI5, RSVD3, DISPLAYB), - PIN(PV0, RSVD1, RSVD2, RSVD3, RSVD4), - PIN(PV1, RSVD1, RSVD2, RSVD3, RSVD4), - PIN(SDMMC1_CLK_PZ0, SDMMC1, CLK12, RSVD3, RSVD4), - PIN(SDMMC1_CMD_PZ1, SDMMC1, SPDIF, SPI4, UARTA), - PIN(SDMMC1_DAT3_PY4, SDMMC1, SPDIF, SPI4, UARTA), - PIN(SDMMC1_DAT2_PY5, SDMMC1, PWM0, SPI4, UARTA), - PIN(SDMMC1_DAT1_PY6, SDMMC1, PWM1, SPI4, UARTA), - PIN(SDMMC1_DAT0_PY7, SDMMC1, RSVD2, SPI4, UARTA), - PIN_RESERVED, - PIN_RESERVED, - /* Offset 0x3068 */ - PIN(CLK2_OUT_PW5, EXTPERIPH2, RSVD2, RSVD3, RSVD4), - PIN(CLK2_REQ_PCC5, DAP, RSVD2, RSVD3, RSVD4), - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - /* Offset 0x3110 */ - PIN(HDMI_INT_PN7, RSVD1, RSVD2, RSVD3, RSVD4), - PIN(DDC_SCL_PV4, I2C4, RSVD2, RSVD3, RSVD4), - PIN(DDC_SDA_PV5, I2C4, RSVD2, RSVD3, RSVD4), - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - /* Offset 0x3164 */ - PIN(UART2_RXD_PC3, IRDA, SPDIF, UARTA, SPI4), - PIN(UART2_TXD_PC2, IRDA, SPDIF, UARTA, SPI4), - PIN(UART2_RTS_N_PJ6, UARTA, UARTB, GMI, SPI4), - PIN(UART2_CTS_N_PJ5, UARTA, UARTB, GMI, SPI4), - PIN(UART3_TXD_PW6, UARTC, RSVD2, GMI, SPI4), - PIN(UART3_RXD_PW7, UARTC, RSVD2, GMI, SPI4), - PIN(UART3_CTS_N_PA1, UARTC, SDMMC1, DTV, GMI), - PIN(UART3_RTS_N_PC0, UARTC, PWM0, DTV, GMI), - PIN(PU0, OWR, UARTA, GMI, RSVD4), - PIN(PU1, RSVD1, UARTA, GMI, RSVD4), - PIN(PU2, RSVD1, UARTA, GMI, RSVD4), - PIN(PU3, PWM0, UARTA, GMI, DISPLAYB), - PIN(PU4, PWM1, UARTA, GMI, DISPLAYB), - PIN(PU5, PWM2, UARTA, GMI, DISPLAYB), - PIN(PU6, PWM3, UARTA, RSVD3, GMI), - PIN(GEN1_I2C_SDA_PC5, I2C1, RSVD2, RSVD3, RSVD4), - PIN(GEN1_I2C_SCL_PC4, I2C1, RSVD2, RSVD3, RSVD4), - PIN(DAP4_FS_PP4, I2S3, GMI, DTV, RSVD4), - PIN(DAP4_DIN_PP5, I2S3, GMI, RSVD3, RSVD4), - PIN(DAP4_DOUT_PP6, I2S3, GMI, DTV, RSVD4), - PIN(DAP4_SCLK_PP7, I2S3, GMI, RSVD3, RSVD4), - PIN(CLK3_OUT_PEE0, EXTPERIPH3, RSVD2, RSVD3, RSVD4), - PIN(CLK3_REQ_PEE1, DEV3, RSVD2, RSVD3, RSVD4), - PIN(PC7, RSVD1, RSVD2, GMI, GMI_ALT), - PIN(PI5, SDMMC2, RSVD2, GMI, RSVD4), - PIN(PI7, RSVD1, TRACE, GMI, DTV), - PIN(PK0, RSVD1, SDMMC3, GMI, SOC), - PIN(PK1, SDMMC2, TRACE, GMI, RSVD4), - PIN(PJ0, RSVD1, RSVD2, GMI, USB), - PIN(PJ2, RSVD1, RSVD2, GMI, SOC), - PIN(PK3, SDMMC2, TRACE, GMI, CCLA), - PIN(PK4, SDMMC2, RSVD2, GMI, GMI_ALT), - PIN(PK2, RSVD1, RSVD2, GMI, RSVD4), - PIN(PI3, RSVD1, RSVD2, GMI, SPI4), - PIN(PI6, RSVD1, RSVD2, GMI, SDMMC2), - PIN(PG0, RSVD1, RSVD2, GMI, RSVD4), - PIN(PG1, RSVD1, RSVD2, GMI, RSVD4), - PIN(PG2, RSVD1, TRACE, GMI, RSVD4), - PIN(PG3, RSVD1, TRACE, GMI, RSVD4), - PIN(PG4, RSVD1, TMDS, GMI, SPI4), - PIN(PG5, RSVD1, RSVD2, GMI, SPI4), - PIN(PG6, RSVD1, RSVD2, GMI, SPI4), - PIN(PG7, RSVD1, RSVD2, GMI, SPI4), - PIN(PH0, PWM0, TRACE, GMI, DTV), - PIN(PH1, PWM1, TMDS, GMI, DISPLAYA), - PIN(PH2, PWM2, TMDS, GMI, CLDVFS), - PIN(PH3, PWM3, SPI4, GMI, CLDVFS), - PIN(PH4, SDMMC2, RSVD2, GMI, RSVD4), - PIN(PH5, SDMMC2, RSVD2, GMI, RSVD4), - PIN(PH6, SDMMC2, TRACE, GMI, DTV), - PIN(PH7, SDMMC2, TRACE, GMI, DTV), - PIN(PJ7, UARTD, RSVD2, GMI, GMI_ALT), - PIN(PB0, UARTD, RSVD2, GMI, RSVD4), - PIN(PB1, UARTD, RSVD2, GMI, RSVD4), - PIN(PK7, UARTD, RSVD2, GMI, RSVD4), - PIN(PI0, RSVD1, RSVD2, GMI, RSVD4), - PIN(PI1, RSVD1, RSVD2, GMI, RSVD4), - PIN(PI2, SDMMC2, TRACE, GMI, RSVD4), - PIN(PI4, SPI4, TRACE, GMI, DISPLAYA), - PIN(GEN2_I2C_SCL_PT5, I2C2, RSVD2, GMI, RSVD4), - PIN(GEN2_I2C_SDA_PT6, I2C2, RSVD2, GMI, RSVD4), - PIN(SDMMC4_CLK_PCC4, SDMMC4, RSVD2, GMI, RSVD4), - PIN(SDMMC4_CMD_PT7, SDMMC4, RSVD2, GMI, RSVD4), - PIN(SDMMC4_DAT0_PAA0, SDMMC4, SPI3, GMI, RSVD4), - PIN(SDMMC4_DAT1_PAA1, SDMMC4, SPI3, GMI, RSVD4), - PIN(SDMMC4_DAT2_PAA2, SDMMC4, SPI3, GMI, RSVD4), - PIN(SDMMC4_DAT3_PAA3, SDMMC4, SPI3, GMI, RSVD4), - PIN(SDMMC4_DAT4_PAA4, SDMMC4, SPI3, GMI, RSVD4), - PIN(SDMMC4_DAT5_PAA5, SDMMC4, SPI3, RSVD3, RSVD4), - PIN(SDMMC4_DAT6_PAA6, SDMMC4, SPI3, GMI, RSVD4), - PIN(SDMMC4_DAT7_PAA7, SDMMC4, RSVD2, GMI, RSVD4), - PIN_RESERVED, - /* Offset 0x3284 */ - PIN(CAM_MCLK_PCC0, VI, VI_ALT1, VI_ALT3, SDMMC2), - PIN(PCC1, I2S4, RSVD2, RSVD3, SDMMC2), - PIN(PBB0, VGP6, VIMCLK2, SDMMC2, VIMCLK2_ALT), - PIN(CAM_I2C_SCL_PBB1, VGP1, I2C3, RSVD3, SDMMC2), - PIN(CAM_I2C_SDA_PBB2, VGP2, I2C3, RSVD3, SDMMC2), - PIN(PBB3, VGP3, DISPLAYA, DISPLAYB, SDMMC2), - PIN(PBB4, VGP4, DISPLAYA, DISPLAYB, SDMMC2), - PIN(PBB5, VGP5, DISPLAYA, RSVD3, SDMMC2), - PIN(PBB6, I2S4, RSVD2, DISPLAYB, SDMMC2), - PIN(PBB7, I2S4, RSVD2, RSVD3, SDMMC2), - PIN(PCC2, I2S4, RSVD2, SDMMC3, SDMMC2), - PIN(JTAG_RTCK, RTCK, RSVD2, RSVD3, RSVD4), - PIN(PWR_I2C_SCL_PZ6, I2CPWR, RSVD2, RSVD3, RSVD4), - PIN(PWR_I2C_SDA_PZ7, I2CPWR, RSVD2, RSVD3, RSVD4), - PIN(KB_ROW0_PR0, KBC, RSVD2, RSVD3, RSVD4), - PIN(KB_ROW1_PR1, KBC, RSVD2, RSVD3, RSVD4), - PIN(KB_ROW2_PR2, KBC, RSVD2, RSVD3, RSVD4), - PIN(KB_ROW3_PR3, KBC, DISPLAYA, SYS, DISPLAYB), - PIN(KB_ROW4_PR4, KBC, DISPLAYA, RSVD3, DISPLAYB), - PIN(KB_ROW5_PR5, KBC, DISPLAYA, RSVD3, DISPLAYB), - PIN(KB_ROW6_PR6, KBC, DISPLAYA, DISPLAYA_ALT, DISPLAYB), - PIN(KB_ROW7_PR7, KBC, RSVD2, CLDVFS, UARTA), - PIN(KB_ROW8_PS0, KBC, RSVD2, CLDVFS, UARTA), - PIN(KB_ROW9_PS1, KBC, RSVD2, RSVD3, UARTA), - PIN(KB_ROW10_PS2, KBC, RSVD2, RSVD3, UARTA), - PIN(KB_ROW11_PS3, KBC, RSVD2, RSVD3, IRDA), - PIN(KB_ROW12_PS4, KBC, RSVD2, RSVD3, IRDA), - PIN(KB_ROW13_PS5, KBC, RSVD2, SPI2, RSVD4), - PIN(KB_ROW14_PS6, KBC, RSVD2, SPI2, RSVD4), - PIN(KB_ROW15_PS7, KBC, SOC, RSVD3, RSVD4), - PIN(KB_COL0_PQ0, KBC, RSVD2, SPI2, RSVD4), - PIN(KB_COL1_PQ1, KBC, RSVD2, SPI2, RSVD4), - PIN(KB_COL2_PQ2, KBC, RSVD2, SPI2, RSVD4), - PIN(KB_COL3_PQ3, KBC, DISPLAYA, PWM2, UARTA), - PIN(KB_COL4_PQ4, KBC, OWR, SDMMC3, UARTA), - PIN(KB_COL5_PQ5, KBC, RSVD2, SDMMC3, RSVD4), - PIN(KB_COL6_PQ6, KBC, RSVD2, SPI2, UARTD), - PIN(KB_COL7_PQ7, KBC, RSVD2, SPI2, UARTD), - PIN(CLK_32K_OUT_PA0, BLINK, SOC, RSVD3, RSVD4), - PIN_RESERVED, - /* Offset 0x3324 */ - PIN(CORE_PWR_REQ, PWRON, RSVD2, RSVD3, RSVD4), - PIN(CPU_PWR_REQ, CPU, RSVD2, RSVD3, RSVD4), - PIN(PWR_INT_N, PMI, RSVD2, RSVD3, RSVD4), - PIN(CLK_32K_IN, CLK, RSVD2, RSVD3, RSVD4), - PIN(OWR, OWR, RSVD2, RSVD3, RSVD4), - PIN(DAP1_FS_PN0, I2S0, HDA, GMI, RSVD4), - PIN(DAP1_DIN_PN1, I2S0, HDA, GMI, RSVD4), - PIN(DAP1_DOUT_PN2, I2S0, HDA, GMI, SATA), - PIN(DAP1_SCLK_PN3, I2S0, HDA, GMI, RSVD4), - PIN(DAP_MCLK1_REQ_PEE2, DAP, DAP1, SATA, RSVD4), - PIN(DAP_MCLK1_PW4, EXTPERIPH1, DAP2, RSVD3, RSVD4), - PIN(SPDIF_IN_PK6, SPDIF, RSVD2, RSVD3, I2C3), - PIN(SPDIF_OUT_PK5, SPDIF, RSVD2, RSVD3, I2C3), - PIN(DAP2_FS_PA2, I2S1, HDA, GMI, RSVD4), - PIN(DAP2_DIN_PA4, I2S1, HDA, GMI, RSVD4), - PIN(DAP2_DOUT_PA5, I2S1, HDA, GMI, RSVD4), - PIN(DAP2_SCLK_PA3, I2S1, HDA, GMI, RSVD4), - PIN(DVFS_PWM_PX0, SPI6, CLDVFS, GMI, RSVD4), - PIN(GPIO_X1_AUD_PX1, SPI6, RSVD2, GMI, RSVD4), - PIN(GPIO_X3_AUD_PX3, SPI6, SPI1, GMI, RSVD4), - PIN(DVFS_CLK_PX2, SPI6, CLDVFS, GMI, RSVD4), - PIN(GPIO_X4_AUD_PX4, GMI, SPI1, SPI2, DAP2), - PIN(GPIO_X5_AUD_PX5, GMI, SPI1, SPI2, RSVD4), - PIN(GPIO_X6_AUD_PX6, SPI6, SPI1, SPI2, GMI), - PIN(GPIO_X7_AUD_PX7, RSVD1, SPI1, SPI2, RSVD4), - PIN_RESERVED, - PIN_RESERVED, - /* Offset 0x3390 */ - PIN(SDMMC3_CLK_PA6, SDMMC3, RSVD2, RSVD3, SPI3), - PIN(SDMMC3_CMD_PA7, SDMMC3, PWM3, UARTA, SPI3), - PIN(SDMMC3_DAT0_PB7, SDMMC3, RSVD2, RSVD3, SPI3), - PIN(SDMMC3_DAT1_PB6, SDMMC3, PWM2, UARTA, SPI3), - PIN(SDMMC3_DAT2_PB5, SDMMC3, PWM1, DISPLAYA, SPI3), - PIN(SDMMC3_DAT3_PB4, SDMMC3, PWM0, DISPLAYB, SPI3), - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - /* Offset 0x33bc */ - PIN(PEX_L0_RST_N_PDD1, PE0, RSVD2, RSVD3, RSVD4), - PIN(PEX_L0_CLKREQ_N_PDD2, PE0, RSVD2, RSVD3, RSVD4), - PIN(PEX_WAKE_N_PDD3, PE, RSVD2, RSVD3, RSVD4), - PIN_RESERVED, - /* Offset 0x33cc */ - PIN(PEX_L1_RST_N_PDD5, PE1, RSVD2, RSVD3, RSVD4), - PIN(PEX_L1_CLKREQ_N_PDD6, PE1, RSVD2, RSVD3, RSVD4), - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - /* Offset 0x33e0 */ - PIN(HDMI_CEC_PEE3, CEC, RSVD2, RSVD3, RSVD4), - PIN(SDMMC1_WP_N_PV3, SDMMC1, CLK12, SPI4, UARTA), - PIN(SDMMC3_CD_N_PV2, SDMMC3, OWR, RSVD3, RSVD4), - PIN(GPIO_W2_AUD_PW2, SPI6, RSVD2, SPI2, I2C1), - PIN(GPIO_W3_AUD_PW3, SPI6, SPI1, SPI2, I2C1), - PIN(USB_VBUS_EN0_PN4, USB, RSVD2, RSVD3, RSVD4), - PIN(USB_VBUS_EN1_PN5, USB, RSVD2, RSVD3, RSVD4), - PIN(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, RSVD2, RSVD3, RSVD4), - PIN(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, RSVD2, RSVD3, RSVD4), - PIN(GMI_CLK_LB, SDMMC2, RSVD2, GMI, RSVD4), - PIN(RESET_OUT_N, RSVD1, RSVD2, RSVD3, RESET_OUT_N), - PIN(KB_ROW16_PT0, KBC, RSVD2, RSVD3, UARTC), - PIN(KB_ROW17_PT1, KBC, RSVD2, RSVD3, UARTC), - PIN(USB_VBUS_EN2_PFF1, USB, RSVD2, RSVD3, RSVD4), - PIN(PFF2, SATA, RSVD2, RSVD3, RSVD4), - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - PIN_RESERVED, - /* Offset 0x3430 */ - PIN(DP_HPD_PFF0, DP, RSVD2, RSVD3, RSVD4), -}; -const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra124_pingroups; - -#define MIPIPADCTRL_GRP(grp, f0, f1) \ - { \ - .funcs = { \ - PMUX_FUNC_##f0, \ - PMUX_FUNC_##f1, \ - }, \ - } - -#define MIPIPADCTRL_RESERVED {} - -static const struct pmux_mipipadctrlgrp_desc tegra124_mipipadctrl_groups[] = { - /* pin, f0, f1 */ - /* Offset 0x820 */ - MIPIPADCTRL_GRP(DSI_B, CSI, DSI_B), -}; -const struct pmux_mipipadctrlgrp_desc *tegra_soc_mipipadctrl_groups = tegra124_mipipadctrl_groups; diff --git a/arch/arm/mach-tegra/tegra20/Makefile b/arch/arm/mach-tegra/tegra20/Makefile index 991cabeec5..c2ae98eb37 100644 --- a/arch/arm/mach-tegra/tegra20/Makefile +++ b/arch/arm/mach-tegra/tegra20/Makefile @@ -11,7 +11,7 @@ CFLAGS_warmboot_avp.o = -march=armv4t -U__LINUX_ARM_ARCH__ \ -D__LINUX_ARM_ARCH__=4 CFLAGS_REMOVE_warmboot_avp.o := $(LTO_CFLAGS) -obj-y += clock.o funcmux.o pinmux.o +obj-y += clock.o obj-$(CONFIG_TEGRA_LP0) += warmboot.o warmboot_avp.o obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o obj-$(CONFIG_TEGRA_PMU) += pmu.o diff --git a/arch/arm/mach-tegra/tegra20/clock.c b/arch/arm/mach-tegra/tegra20/clock.c index abd6e3917a..109b73bfbe 100644 --- a/arch/arm/mach-tegra/tegra20/clock.c +++ b/arch/arm/mach-tegra/tegra20/clock.c @@ -792,6 +792,21 @@ int tegra_plle_enable(void) return 0; } +struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + + switch (clkid) { + case CLOCK_ID_XCPU: + case CLOCK_ID_EPCI: + case CLOCK_ID_SFROM32KHZ: + return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE]; + default: + return NULL; + } +} + struct periph_clk_init periph_clk_init_table[] = { { PERIPH_ID_SPI1, CLOCK_ID_PERIPH }, { PERIPH_ID_SBC1, CLOCK_ID_PERIPH }, diff --git a/arch/arm/mach-tegra/tegra20/funcmux.c b/arch/arm/mach-tegra/tegra20/funcmux.c deleted file mode 100644 index 90fe0cba8e..0000000000 --- a/arch/arm/mach-tegra/tegra20/funcmux.c +++ /dev/null @@ -1,298 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2011 The Chromium OS Authors. - */ - -/* Tegra20 high-level function multiplexing */ -#include <common.h> -#include <log.h> -#include <asm/arch/clock.h> -#include <asm/arch/funcmux.h> -#include <asm/arch/pinmux.h> - -/* - * The PINMUX macro is used to set up pinmux tables. - */ -#define PINMUX(grp, mux, pupd, tri) \ - {PMUX_PINGRP_##grp, PMUX_FUNC_##mux, PMUX_PULL_##pupd, PMUX_TRI_##tri} - -static const struct pmux_pingrp_config disp1_default[] = { - PINMUX(LDI, DISPA, NORMAL, NORMAL), - PINMUX(LHP0, DISPA, NORMAL, NORMAL), - PINMUX(LHP1, DISPA, NORMAL, NORMAL), - PINMUX(LHP2, DISPA, NORMAL, NORMAL), - PINMUX(LHS, DISPA, NORMAL, NORMAL), - PINMUX(LM0, RSVD4, NORMAL, NORMAL), - PINMUX(LPP, DISPA, NORMAL, NORMAL), - PINMUX(LPW0, DISPA, NORMAL, NORMAL), - PINMUX(LPW2, DISPA, NORMAL, NORMAL), - PINMUX(LSC0, DISPA, NORMAL, NORMAL), - PINMUX(LSPI, DISPA, NORMAL, NORMAL), - PINMUX(LVP1, DISPA, NORMAL, NORMAL), - PINMUX(LVS, DISPA, NORMAL, NORMAL), - PINMUX(SLXD, SPDIF, NORMAL, NORMAL), -}; - - -int funcmux_select(enum periph_id id, int config) -{ - int bad_config = config != FUNCMUX_DEFAULT; - - switch (id) { - case PERIPH_ID_UART1: - switch (config) { - case FUNCMUX_UART1_IRRX_IRTX: - pinmux_set_func(PMUX_PINGRP_IRRX, PMUX_FUNC_UARTA); - pinmux_set_func(PMUX_PINGRP_IRTX, PMUX_FUNC_UARTA); - pinmux_tristate_disable(PMUX_PINGRP_IRRX); - pinmux_tristate_disable(PMUX_PINGRP_IRTX); - break; - case FUNCMUX_UART1_UAA_UAB: - pinmux_set_func(PMUX_PINGRP_UAA, PMUX_FUNC_UARTA); - pinmux_set_func(PMUX_PINGRP_UAB, PMUX_FUNC_UARTA); - pinmux_tristate_disable(PMUX_PINGRP_UAA); - pinmux_tristate_disable(PMUX_PINGRP_UAB); - bad_config = 0; - break; - case FUNCMUX_UART1_GPU: - pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_UARTA); - pinmux_tristate_disable(PMUX_PINGRP_GPU); - bad_config = 0; - break; - case FUNCMUX_UART1_SDIO1: - pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_UARTA); - pinmux_tristate_disable(PMUX_PINGRP_SDIO1); - bad_config = 0; - break; - } - if (!bad_config) { - /* - * Tegra appears to boot with function UARTA pre- - * selected on mux group SDB. If two mux groups are - * both set to the same function, it's unclear which - * group's pins drive the RX signals into the HW. - * For UARTA, SDB certainly overrides group IRTX in - * practice. To solve this, configure some alternative - * function on SDB to avoid the conflict. Also, tri- - * state the group to avoid driving any signal onto it - * until we know what's connected. - */ - pinmux_tristate_enable(PMUX_PINGRP_SDB); - pinmux_set_func(PMUX_PINGRP_SDB, PMUX_FUNC_SDIO3); - } - break; - - case PERIPH_ID_UART2: - if (config == FUNCMUX_UART2_UAD) { - pinmux_set_func(PMUX_PINGRP_UAD, PMUX_FUNC_UARTB); - pinmux_tristate_disable(PMUX_PINGRP_UAD); - } - break; - - case PERIPH_ID_UART4: - if (config == FUNCMUX_UART4_GMC) { - pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_UARTD); - pinmux_tristate_disable(PMUX_PINGRP_GMC); - } - break; - - case PERIPH_ID_DVC_I2C: - /* there is only one selection, pinmux_config is ignored */ - if (config == FUNCMUX_DVC_I2CP) { - pinmux_set_func(PMUX_PINGRP_I2CP, PMUX_FUNC_I2C); - pinmux_tristate_disable(PMUX_PINGRP_I2CP); - } - break; - - case PERIPH_ID_I2C1: - /* support pinmux_config of 0 for now, */ - if (config == FUNCMUX_I2C1_RM) { - pinmux_set_func(PMUX_PINGRP_RM, PMUX_FUNC_I2C); - pinmux_tristate_disable(PMUX_PINGRP_RM); - } - break; - case PERIPH_ID_I2C2: /* I2C2 */ - switch (config) { - case FUNCMUX_I2C2_DDC: /* DDC pin group, select I2C2 */ - pinmux_set_func(PMUX_PINGRP_DDC, PMUX_FUNC_I2C2); - /* PTA to HDMI */ - pinmux_set_func(PMUX_PINGRP_PTA, PMUX_FUNC_HDMI); - pinmux_tristate_disable(PMUX_PINGRP_DDC); - break; - case FUNCMUX_I2C2_PTA: /* PTA pin group, select I2C2 */ - pinmux_set_func(PMUX_PINGRP_PTA, PMUX_FUNC_I2C2); - /* set DDC_SEL to RSVDx (RSVD2 works for now) */ - pinmux_set_func(PMUX_PINGRP_DDC, PMUX_FUNC_RSVD2); - pinmux_tristate_disable(PMUX_PINGRP_PTA); - bad_config = 0; - break; - } - break; - case PERIPH_ID_I2C3: /* I2C3 */ - /* support pinmux_config of 0 for now */ - if (config == FUNCMUX_I2C3_DTF) { - pinmux_set_func(PMUX_PINGRP_DTF, PMUX_FUNC_I2C3); - pinmux_tristate_disable(PMUX_PINGRP_DTF); - } - break; - - case PERIPH_ID_SDMMC1: - if (config == FUNCMUX_SDMMC1_SDIO1_4BIT) { - pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_SDIO1); - pinmux_tristate_disable(PMUX_PINGRP_SDIO1); - } - break; - - case PERIPH_ID_SDMMC2: - if (config == FUNCMUX_SDMMC2_DTA_DTD_8BIT) { - pinmux_set_func(PMUX_PINGRP_DTA, PMUX_FUNC_SDIO2); - pinmux_set_func(PMUX_PINGRP_DTD, PMUX_FUNC_SDIO2); - - pinmux_tristate_disable(PMUX_PINGRP_DTA); - pinmux_tristate_disable(PMUX_PINGRP_DTD); - } - break; - - case PERIPH_ID_SDMMC3: - switch (config) { - case FUNCMUX_SDMMC3_SDB_SLXA_8BIT: - pinmux_set_func(PMUX_PINGRP_SLXA, PMUX_FUNC_SDIO3); - pinmux_set_func(PMUX_PINGRP_SLXC, PMUX_FUNC_SDIO3); - pinmux_set_func(PMUX_PINGRP_SLXD, PMUX_FUNC_SDIO3); - pinmux_set_func(PMUX_PINGRP_SLXK, PMUX_FUNC_SDIO3); - - pinmux_tristate_disable(PMUX_PINGRP_SLXA); - pinmux_tristate_disable(PMUX_PINGRP_SLXC); - pinmux_tristate_disable(PMUX_PINGRP_SLXD); - pinmux_tristate_disable(PMUX_PINGRP_SLXK); - /* fall through */ - - case FUNCMUX_SDMMC3_SDB_4BIT: - pinmux_set_func(PMUX_PINGRP_SDB, PMUX_FUNC_SDIO3); - pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_SDIO3); - pinmux_set_func(PMUX_PINGRP_SDD, PMUX_FUNC_SDIO3); - - pinmux_tristate_disable(PMUX_PINGRP_SDB); - pinmux_tristate_disable(PMUX_PINGRP_SDC); - pinmux_tristate_disable(PMUX_PINGRP_SDD); - bad_config = 0; - break; - } - break; - - case PERIPH_ID_SDMMC4: - switch (config) { - case FUNCMUX_SDMMC4_ATC_ATD_8BIT: - pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_SDIO4); - pinmux_set_func(PMUX_PINGRP_ATD, PMUX_FUNC_SDIO4); - - pinmux_tristate_disable(PMUX_PINGRP_ATC); - pinmux_tristate_disable(PMUX_PINGRP_ATD); - break; - - case FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT: - pinmux_set_func(PMUX_PINGRP_GME, PMUX_FUNC_SDIO4); - pinmux_tristate_disable(PMUX_PINGRP_GME); - /* fall through */ - - case FUNCMUX_SDMMC4_ATB_GMA_4_BIT: - pinmux_set_func(PMUX_PINGRP_ATB, PMUX_FUNC_SDIO4); - pinmux_set_func(PMUX_PINGRP_GMA, PMUX_FUNC_SDIO4); - - pinmux_tristate_disable(PMUX_PINGRP_ATB); - pinmux_tristate_disable(PMUX_PINGRP_GMA); - bad_config = 0; - break; - } - break; - - case PERIPH_ID_KBC: - if (config == FUNCMUX_DEFAULT) { - enum pmux_pingrp grp[] = {PMUX_PINGRP_KBCA, - PMUX_PINGRP_KBCB, PMUX_PINGRP_KBCC, - PMUX_PINGRP_KBCD, PMUX_PINGRP_KBCE, - PMUX_PINGRP_KBCF}; - int i; - - for (i = 0; i < ARRAY_SIZE(grp); i++) { - pinmux_tristate_disable(grp[i]); - pinmux_set_func(grp[i], PMUX_FUNC_KBC); - pinmux_set_pullupdown(grp[i], PMUX_PULL_UP); - } - } - break; - - case PERIPH_ID_USB2: - if (config == FUNCMUX_USB2_ULPI) { - pinmux_set_func(PMUX_PINGRP_UAA, PMUX_FUNC_ULPI); - pinmux_set_func(PMUX_PINGRP_UAB, PMUX_FUNC_ULPI); - pinmux_set_func(PMUX_PINGRP_UDA, PMUX_FUNC_ULPI); - - pinmux_tristate_disable(PMUX_PINGRP_UAA); - pinmux_tristate_disable(PMUX_PINGRP_UAB); - pinmux_tristate_disable(PMUX_PINGRP_UDA); - } - break; - - case PERIPH_ID_SPI1: - if (config == FUNCMUX_SPI1_GMC_GMD) { - pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_SFLASH); - pinmux_set_func(PMUX_PINGRP_GMD, PMUX_FUNC_SFLASH); - - pinmux_tristate_disable(PMUX_PINGRP_GMC); - pinmux_tristate_disable(PMUX_PINGRP_GMD); - } - break; - - case PERIPH_ID_NDFLASH: - switch (config) { - case FUNCMUX_NDFLASH_ATC: - pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_NAND); - pinmux_tristate_disable(PMUX_PINGRP_ATC); - break; - case FUNCMUX_NDFLASH_KBC_8_BIT: - pinmux_set_func(PMUX_PINGRP_KBCA, PMUX_FUNC_NAND); - pinmux_set_func(PMUX_PINGRP_KBCB, PMUX_FUNC_NAND); - pinmux_set_func(PMUX_PINGRP_KBCC, PMUX_FUNC_NAND); - pinmux_set_func(PMUX_PINGRP_KBCD, PMUX_FUNC_NAND); - pinmux_set_func(PMUX_PINGRP_KBCE, PMUX_FUNC_NAND); - pinmux_set_func(PMUX_PINGRP_KBCF, PMUX_FUNC_NAND); - - pinmux_tristate_disable(PMUX_PINGRP_KBCA); - pinmux_tristate_disable(PMUX_PINGRP_KBCB); - pinmux_tristate_disable(PMUX_PINGRP_KBCC); - pinmux_tristate_disable(PMUX_PINGRP_KBCD); - pinmux_tristate_disable(PMUX_PINGRP_KBCE); - pinmux_tristate_disable(PMUX_PINGRP_KBCF); - - bad_config = 0; - break; - } - break; - case PERIPH_ID_DISP1: - if (config == FUNCMUX_DEFAULT) { - int i; - - for (i = PMUX_PINGRP_LD0; i <= PMUX_PINGRP_LD17; i++) { - pinmux_set_func(i, PMUX_FUNC_DISPA); - pinmux_tristate_disable(i); - pinmux_set_pullupdown(i, PMUX_PULL_NORMAL); - } - pinmux_config_pingrp_table(disp1_default, - ARRAY_SIZE(disp1_default)); - } - break; - - default: - debug("%s: invalid periph_id %d", __func__, id); - return -1; - } - - if (bad_config) { - debug("%s: invalid config %d for periph_id %d", __func__, - config, id); - return -1; - } - - return 0; -} diff --git a/arch/arm/mach-tegra/tegra20/pinmux.c b/arch/arm/mach-tegra/tegra20/pinmux.c deleted file mode 100644 index 0af39e74c5..0000000000 --- a/arch/arm/mach-tegra/tegra20/pinmux.c +++ /dev/null @@ -1,424 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2011 The Chromium OS Authors. - */ - -/* Tegra20 pin multiplexing functions */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/pinmux.h> - -/* - * This defines the order of the pin mux control bits in the registers. For - * some reason there is no correspendence between the tristate, pin mux and - * pullup/pulldown registers. - */ -enum pmux_ctlid { - /* 0: APB_MISC_PP_PIN_MUX_CTL_A_0 */ - MUXCTL_UAA, - MUXCTL_UAB, - MUXCTL_UAC, - MUXCTL_UAD, - MUXCTL_UDA, - MUXCTL_RESERVED5, - MUXCTL_ATE, - MUXCTL_RM, - - MUXCTL_ATB, - MUXCTL_RESERVED9, - MUXCTL_ATD, - MUXCTL_ATC, - MUXCTL_ATA, - MUXCTL_KBCF, - MUXCTL_KBCE, - MUXCTL_SDMMC1, - - /* 16: APB_MISC_PP_PIN_MUX_CTL_B_0 */ - MUXCTL_GMA, - MUXCTL_GMC, - MUXCTL_HDINT, - MUXCTL_SLXA, - MUXCTL_OWC, - MUXCTL_SLXC, - MUXCTL_SLXD, - MUXCTL_SLXK, - - MUXCTL_UCA, - MUXCTL_UCB, - MUXCTL_DTA, - MUXCTL_DTB, - MUXCTL_RESERVED28, - MUXCTL_DTC, - MUXCTL_DTD, - MUXCTL_DTE, - - /* 32: APB_MISC_PP_PIN_MUX_CTL_C_0 */ - MUXCTL_DDC, - MUXCTL_CDEV1, - MUXCTL_CDEV2, - MUXCTL_CSUS, - MUXCTL_I2CP, - MUXCTL_KBCA, - MUXCTL_KBCB, - MUXCTL_KBCC, - - MUXCTL_IRTX, - MUXCTL_IRRX, - MUXCTL_DAP1, - MUXCTL_DAP2, - MUXCTL_DAP3, - MUXCTL_DAP4, - MUXCTL_GMB, - MUXCTL_GMD, - - /* 48: APB_MISC_PP_PIN_MUX_CTL_D_0 */ - MUXCTL_GME, - MUXCTL_GPV, - MUXCTL_GPU, - MUXCTL_SPDO, - MUXCTL_SPDI, - MUXCTL_SDB, - MUXCTL_SDC, - MUXCTL_SDD, - - MUXCTL_SPIH, - MUXCTL_SPIG, - MUXCTL_SPIF, - MUXCTL_SPIE, - MUXCTL_SPID, - MUXCTL_SPIC, - MUXCTL_SPIB, - MUXCTL_SPIA, - - /* 64: APB_MISC_PP_PIN_MUX_CTL_E_0 */ - MUXCTL_LPW0, - MUXCTL_LPW1, - MUXCTL_LPW2, - MUXCTL_LSDI, - MUXCTL_LSDA, - MUXCTL_LSPI, - MUXCTL_LCSN, - MUXCTL_LDC, - - MUXCTL_LSCK, - MUXCTL_LSC0, - MUXCTL_LSC1, - MUXCTL_LHS, - MUXCTL_LVS, - MUXCTL_LM0, - MUXCTL_LM1, - MUXCTL_LVP0, - - /* 80: APB_MISC_PP_PIN_MUX_CTL_F_0 */ - MUXCTL_LD0, - MUXCTL_LD1, - MUXCTL_LD2, - MUXCTL_LD3, - MUXCTL_LD4, - MUXCTL_LD5, - MUXCTL_LD6, - MUXCTL_LD7, - - MUXCTL_LD8, - MUXCTL_LD9, - MUXCTL_LD10, - MUXCTL_LD11, - MUXCTL_LD12, - MUXCTL_LD13, - MUXCTL_LD14, - MUXCTL_LD15, - - /* 96: APB_MISC_PP_PIN_MUX_CTL_G_0 */ - MUXCTL_LD16, - MUXCTL_LD17, - MUXCTL_LHP1, - MUXCTL_LHP2, - MUXCTL_LVP1, - MUXCTL_LHP0, - MUXCTL_RESERVED102, - MUXCTL_LPP, - - MUXCTL_LDI, - MUXCTL_PMC, - MUXCTL_CRTP, - MUXCTL_PTA, - MUXCTL_RESERVED108, - MUXCTL_KBCD, - MUXCTL_GPU7, - MUXCTL_DTF, - - MUXCTL_NONE = -1, -}; - -/* - * And this defines the order of the pullup/pulldown controls which are again - * in a different order - */ -enum pmux_pullid { - /* 0: APB_MISC_PP_PULLUPDOWN_REG_A_0 */ - PUCTL_ATA, - PUCTL_ATB, - PUCTL_ATC, - PUCTL_ATD, - PUCTL_ATE, - PUCTL_DAP1, - PUCTL_DAP2, - PUCTL_DAP3, - - PUCTL_DAP4, - PUCTL_DTA, - PUCTL_DTB, - PUCTL_DTC, - PUCTL_DTD, - PUCTL_DTE, - PUCTL_DTF, - PUCTL_GPV, - - /* 16: APB_MISC_PP_PULLUPDOWN_REG_B_0 */ - PUCTL_RM, - PUCTL_I2CP, - PUCTL_PTA, - PUCTL_GPU7, - PUCTL_KBCA, - PUCTL_KBCB, - PUCTL_KBCC, - PUCTL_KBCD, - - PUCTL_SPDI, - PUCTL_SPDO, - PUCTL_GPSLXAU, - PUCTL_CRTP, - PUCTL_SLXC, - PUCTL_SLXD, - PUCTL_SLXK, - - /* 32: APB_MISC_PP_PULLUPDOWN_REG_C_0 */ - PUCTL_CDEV1, - PUCTL_CDEV2, - PUCTL_SPIA, - PUCTL_SPIB, - PUCTL_SPIC, - PUCTL_SPID, - PUCTL_SPIE, - PUCTL_SPIF, - - PUCTL_SPIG, - PUCTL_SPIH, - PUCTL_IRTX, - PUCTL_IRRX, - PUCTL_GME, - PUCTL_RESERVED45, - PUCTL_XM2D, - PUCTL_XM2C, - - /* 48: APB_MISC_PP_PULLUPDOWN_REG_D_0 */ - PUCTL_UAA, - PUCTL_UAB, - PUCTL_UAC, - PUCTL_UAD, - PUCTL_UCA, - PUCTL_UCB, - PUCTL_LD17, - PUCTL_LD19_18, - - PUCTL_LD21_20, - PUCTL_LD23_22, - PUCTL_LS, - PUCTL_LC, - PUCTL_CSUS, - PUCTL_DDRC, - PUCTL_SDC, - PUCTL_SDD, - - /* 64: APB_MISC_PP_PULLUPDOWN_REG_E_0 */ - PUCTL_KBCF, - PUCTL_KBCE, - PUCTL_PMCA, - PUCTL_PMCB, - PUCTL_PMCC, - PUCTL_PMCD, - PUCTL_PMCE, - PUCTL_CK32, - - PUCTL_UDA, - PUCTL_SDMMC1, - PUCTL_GMA, - PUCTL_GMB, - PUCTL_GMC, - PUCTL_GMD, - PUCTL_DDC, - PUCTL_OWC, - - PUCTL_NONE = -1 -}; - -/* Convenient macro for defining pin group properties */ -#define PINALL(pingrp, f0, f1, f2, f3, mux, pupd) \ - { \ - .funcs = { \ - PMUX_FUNC_ ## f0, \ - PMUX_FUNC_ ## f1, \ - PMUX_FUNC_ ## f2, \ - PMUX_FUNC_ ## f3, \ - }, \ - .ctl_id = mux, \ - .pull_id = pupd \ - } - -/* A normal pin group where the mux name and pull-up name match */ -#define PIN(pingrp, f0, f1, f2, f3) \ - PINALL(pingrp, f0, f1, f2, f3, MUXCTL_##pingrp, PUCTL_##pingrp) - -/* A pin group where the pull-up name doesn't have a 1-1 mapping */ -#define PINP(pingrp, f0, f1, f2, f3, pupd) \ - PINALL(pingrp, f0, f1, f2, f3, MUXCTL_##pingrp, PUCTL_##pupd) - -/* A pin group number which is not used */ -#define PIN_RESERVED \ - PIN(NONE, RSVD1, RSVD2, RSVD3, RSVD4) - -#define DRVGRP(drvgrp) \ - PINALL(drvgrp, RSVD1, RSVD2, RSVD3, RSVD4, MUXCTL_NONE, PUCTL_NONE) - -static const struct pmux_pingrp_desc tegra20_pingroups[] = { - PIN(ATA, IDE, NAND, GMI, RSVD4), - PIN(ATB, IDE, NAND, GMI, SDIO4), - PIN(ATC, IDE, NAND, GMI, SDIO4), - PIN(ATD, IDE, NAND, GMI, SDIO4), - PIN(CDEV1, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC), - PIN(CDEV2, OSC, AHB_CLK, APB_CLK, PLLP_OUT4), - PIN(CSUS, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK), - PIN(DAP1, DAP1, RSVD2, GMI, SDIO2), - - PIN(DAP2, DAP2, TWC, RSVD3, GMI), - PIN(DAP3, DAP3, RSVD2, RSVD3, RSVD4), - PIN(DAP4, DAP4, RSVD2, GMI, RSVD4), - PIN(DTA, RSVD1, SDIO2, VI, RSVD4), - PIN(DTB, RSVD1, RSVD2, VI, SPI1), - PIN(DTC, RSVD1, RSVD2, VI, RSVD4), - PIN(DTD, RSVD1, SDIO2, VI, RSVD4), - PIN(DTE, RSVD1, RSVD2, VI, SPI1), - - PINP(GPU, PWM, UARTA, GMI, RSVD4, GPSLXAU), - PIN(GPV, PCIE, RSVD2, RSVD3, RSVD4), - PIN(I2CP, I2C, RSVD2, RSVD3, RSVD4), - PIN(IRTX, UARTA, UARTB, GMI, SPI4), - PIN(IRRX, UARTA, UARTB, GMI, SPI4), - PIN(KBCB, KBC, NAND, SDIO2, MIO), - PIN(KBCA, KBC, NAND, SDIO2, EMC_TEST0_DLL), - PINP(PMC, PWR_ON, PWR_INTR, RSVD3, RSVD4, NONE), - - PIN(PTA, I2C2, HDMI, GMI, RSVD4), - PIN(RM, I2C, RSVD2, RSVD3, RSVD4), - PIN(KBCE, KBC, NAND, OWR, RSVD4), - PIN(KBCF, KBC, NAND, TRACE, MIO), - PIN(GMA, UARTE, SPI3, GMI, SDIO4), - PIN(GMC, UARTD, SPI4, GMI, SFLASH), - PIN(SDMMC1, SDIO1, RSVD2, UARTE, UARTA), - PIN(OWC, OWR, RSVD2, RSVD3, RSVD4), - - PIN(GME, RSVD1, DAP5, GMI, SDIO4), - PIN(SDC, PWM, TWC, SDIO3, SPI3), - PIN(SDD, UARTA, PWM, SDIO3, SPI3), - PIN_RESERVED, - PINP(SLXA, PCIE, SPI4, SDIO3, SPI2, CRTP), - PIN(SLXC, SPDIF, SPI4, SDIO3, SPI2), - PIN(SLXD, SPDIF, SPI4, SDIO3, SPI2), - PIN(SLXK, PCIE, SPI4, SDIO3, SPI2), - - PIN(SPDI, SPDIF, RSVD2, I2C, SDIO2), - PIN(SPDO, SPDIF, RSVD2, I2C, SDIO2), - PIN(SPIA, SPI1, SPI2, SPI3, GMI), - PIN(SPIB, SPI1, SPI2, SPI3, GMI), - PIN(SPIC, SPI1, SPI2, SPI3, GMI), - PIN(SPID, SPI2, SPI1, SPI2_ALT, GMI), - PIN(SPIE, SPI2, SPI1, SPI2_ALT, GMI), - PIN(SPIF, SPI3, SPI1, SPI2, RSVD4), - - PIN(SPIG, SPI3, SPI2, SPI2_ALT, I2C), - PIN(SPIH, SPI3, SPI2, SPI2_ALT, I2C), - PIN(UAA, SPI3, MIPI_HS, UARTA, ULPI), - PIN(UAB, SPI2, MIPI_HS, UARTA, ULPI), - PIN(UAC, OWR, RSVD2, RSVD3, RSVD4), - PIN(UAD, UARTB, SPDIF, UARTA, SPI4), - PIN(UCA, UARTC, RSVD2, GMI, RSVD4), - PIN(UCB, UARTC, PWM, GMI, RSVD4), - - PIN_RESERVED, - PIN(ATE, IDE, NAND, GMI, RSVD4), - PIN(KBCC, KBC, NAND, TRACE, EMC_TEST1_DLL), - PIN_RESERVED, - PIN_RESERVED, - PIN(GMB, IDE, NAND, GMI, GMI_INT), - PIN(GMD, RSVD1, NAND, GMI, SFLASH), - PIN(DDC, I2C2, RSVD2, RSVD3, RSVD4), - - /* 64 */ - PINP(LD0, DISPA, DISPB, XIO, RSVD4, LD17), - PINP(LD1, DISPA, DISPB, XIO, RSVD4, LD17), - PINP(LD2, DISPA, DISPB, XIO, RSVD4, LD17), - PINP(LD3, DISPA, DISPB, XIO, RSVD4, LD17), - PINP(LD4, DISPA, DISPB, XIO, RSVD4, LD17), - PINP(LD5, DISPA, DISPB, XIO, RSVD4, LD17), - PINP(LD6, DISPA, DISPB, XIO, RSVD4, LD17), - PINP(LD7, DISPA, DISPB, XIO, RSVD4, LD17), - - PINP(LD8, DISPA, DISPB, XIO, RSVD4, LD17), - PINP(LD9, DISPA, DISPB, XIO, RSVD4, LD17), - PINP(LD10, DISPA, DISPB, XIO, RSVD4, LD17), - PINP(LD11, DISPA, DISPB, XIO, RSVD4, LD17), - PINP(LD12, DISPA, DISPB, XIO, RSVD4, LD17), - PINP(LD13, DISPA, DISPB, XIO, RSVD4, LD17), - PINP(LD14, DISPA, DISPB, XIO, RSVD4, LD17), - PINP(LD15, DISPA, DISPB, XIO, RSVD4, LD17), - - PINP(LD16, DISPA, DISPB, XIO, RSVD4, LD17), - PINP(LD17, DISPA, DISPB, RSVD3, RSVD4, LD17), - PINP(LHP0, DISPA, DISPB, RSVD3, RSVD4, LD21_20), - PINP(LHP1, DISPA, DISPB, RSVD3, RSVD4, LD19_18), - PINP(LHP2, DISPA, DISPB, RSVD3, RSVD4, LD19_18), - PINP(LVP0, DISPA, DISPB, RSVD3, RSVD4, LC), - PINP(LVP1, DISPA, DISPB, RSVD3, RSVD4, LD21_20), - PINP(HDINT, HDMI, RSVD2, RSVD3, RSVD4, LC), - - PINP(LM0, DISPA, DISPB, SPI3, RSVD4, LC), - PINP(LM1, DISPA, DISPB, RSVD3, CRT, LC), - PINP(LVS, DISPA, DISPB, XIO, RSVD4, LC), - PINP(LSC0, DISPA, DISPB, XIO, RSVD4, LC), - PINP(LSC1, DISPA, DISPB, SPI3, HDMI, LS), - PINP(LSCK, DISPA, DISPB, SPI3, HDMI, LS), - PINP(LDC, DISPA, DISPB, RSVD3, RSVD4, LS), - PINP(LCSN, DISPA, DISPB, SPI3, RSVD4, LS), - - /* 96 */ - PINP(LSPI, DISPA, DISPB, XIO, HDMI, LC), - PINP(LSDA, DISPA, DISPB, SPI3, HDMI, LS), - PINP(LSDI, DISPA, DISPB, SPI3, RSVD4, LS), - PINP(LPW0, DISPA, DISPB, SPI3, HDMI, LS), - PINP(LPW1, DISPA, DISPB, RSVD3, RSVD4, LS), - PINP(LPW2, DISPA, DISPB, SPI3, HDMI, LS), - PINP(LDI, DISPA, DISPB, RSVD3, RSVD4, LD23_22), - PINP(LHS, DISPA, DISPB, XIO, RSVD4, LC), - - PINP(LPP, DISPA, DISPB, RSVD3, RSVD4, LD23_22), - PIN_RESERVED, - PIN(KBCD, KBC, NAND, SDIO2, MIO), - PIN(GPU7, RTCK, RSVD2, RSVD3, RSVD4), - PIN(DTF, I2C3, RSVD2, VI, RSVD4), - PIN(UDA, SPI1, RSVD2, UARTD, ULPI), - PIN(CRTP, CRT, RSVD2, RSVD3, RSVD4), - PINP(SDB, UARTA, PWM, SDIO3, SPI2, NONE), - - /* these pin groups only have pullup and pull down control */ - DRVGRP(CK32), - DRVGRP(DDRC), - DRVGRP(PMCA), - DRVGRP(PMCB), - DRVGRP(PMCC), - DRVGRP(PMCD), - DRVGRP(PMCE), - DRVGRP(XM2C), - DRVGRP(XM2D), -}; -const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra20_pingroups; diff --git a/arch/arm/mach-tegra/tegra210/Makefile b/arch/arm/mach-tegra/tegra210/Makefile index cfcba5b68f..5cc718d276 100644 --- a/arch/arm/mach-tegra/tegra210/Makefile +++ b/arch/arm/mach-tegra/tegra210/Makefile @@ -6,6 +6,5 @@ # obj-y += clock.o -obj-y += funcmux.o obj-y += xusb-padctl.o obj-y += ../xusb-padctl-common.o diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c index 900537afbe..74817e0440 100644 --- a/arch/arm/mach-tegra/tegra210/clock.c +++ b/arch/arm/mach-tegra/tegra210/clock.c @@ -1266,6 +1266,21 @@ int tegra_plle_enable(void) return 0; } +struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + + switch (clkid) { + case CLOCK_ID_XCPU: + case CLOCK_ID_EPCI: + case CLOCK_ID_SFROM32KHZ: + return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE]; + default: + return NULL; + } +} + struct periph_clk_init periph_clk_init_table[] = { { PERIPH_ID_SBC1, CLOCK_ID_PERIPH }, { PERIPH_ID_SBC2, CLOCK_ID_PERIPH }, diff --git a/arch/arm/mach-tegra/tegra210/funcmux.c b/arch/arm/mach-tegra/tegra210/funcmux.c deleted file mode 100644 index 30d994a17f..0000000000 --- a/arch/arm/mach-tegra/tegra210/funcmux.c +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2013-2015 - * NVIDIA Corporation <www.nvidia.com> - */ - -/* Tegra210 high-level function multiplexing */ - -#include <common.h> -#include <log.h> -#include <asm/arch/clock.h> -#include <asm/arch/funcmux.h> -#include <asm/arch/pinmux.h> - -int funcmux_select(enum periph_id id, int config) -{ - int bad_config = config != FUNCMUX_DEFAULT; - - switch (id) { - /* - * Add other periph IDs here as needed. - * Note that all pinmux/pads should have already - * been set up in the board pinmux table in - * pinmux-config-<board>.h for all periphs. - * Leave this in for the odd case where a mux - * needs to be changed on-the-fly. - */ - - default: - debug("%s: invalid periph_id %d", __func__, id); - return -1; - } - - if (bad_config) { - debug("%s: invalid config %d for periph_id %d", __func__, - config, id); - return -1; - } - return 0; -} diff --git a/arch/arm/mach-tegra/tegra30/Makefile b/arch/arm/mach-tegra/tegra30/Makefile index 28dd486d8d..ee0e6f5b94 100644 --- a/arch/arm/mach-tegra/tegra30/Makefile +++ b/arch/arm/mach-tegra/tegra30/Makefile @@ -5,4 +5,4 @@ obj-$(CONFIG_SPL_BUILD) += cpu.o obj-$(CONFIG_$(SPL_)CMD_EBTUPDATE) += bct.o -obj-y += clock.o funcmux.o pinmux.o +obj-y += clock.o diff --git a/arch/arm/mach-tegra/tegra30/clock.c b/arch/arm/mach-tegra/tegra30/clock.c index 698c7ab956..0af8cde8c6 100644 --- a/arch/arm/mach-tegra/tegra30/clock.c +++ b/arch/arm/mach-tegra/tegra30/clock.c @@ -438,6 +438,8 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */ { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */ + { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, + .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD2 */ }; /* @@ -654,6 +656,9 @@ enum clock_id clk_id_to_pll_id(int clk_id) case TEGRA30_CLK_PLL_D: case TEGRA30_CLK_PLL_D_OUT0: return CLOCK_ID_DISPLAY; + case TEGRA30_CLK_PLL_D2: + case TEGRA30_CLK_PLL_D2_OUT0: + return CLOCK_ID_DISPLAY2; case TEGRA30_CLK_PLL_X: return CLOCK_ID_XCPU; case TEGRA30_CLK_PLL_E: @@ -871,6 +876,23 @@ int tegra_plle_enable(void) return 0; } +struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + + switch (clkid) { + case CLOCK_ID_XCPU: + case CLOCK_ID_EPCI: + case CLOCK_ID_SFROM32KHZ: + return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE]; + case CLOCK_ID_DISPLAY2: + return &clkrst->plld2; + default: + return NULL; + } +} + struct periph_clk_init periph_clk_init_table[] = { { PERIPH_ID_SBC1, CLOCK_ID_PERIPH }, { PERIPH_ID_SBC2, CLOCK_ID_PERIPH }, diff --git a/arch/arm/mach-tegra/tegra30/funcmux.c b/arch/arm/mach-tegra/tegra30/funcmux.c deleted file mode 100644 index c3ee787f33..0000000000 --- a/arch/arm/mach-tegra/tegra30/funcmux.c +++ /dev/null @@ -1,51 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - */ - -/* Tegra30 high-level function multiplexing */ - -#include <common.h> -#include <log.h> -#include <asm/arch/clock.h> -#include <asm/arch/funcmux.h> -#include <asm/arch/pinmux.h> - -int funcmux_select(enum periph_id id, int config) -{ - int bad_config = config != FUNCMUX_DEFAULT; - - switch (id) { - case PERIPH_ID_UART1: - switch (config) { - case FUNCMUX_UART1_ULPI: - pinmux_set_func(PMUX_PINGRP_ULPI_DATA0_PO1, - PMUX_FUNC_UARTA); - pinmux_set_func(PMUX_PINGRP_ULPI_DATA1_PO2, - PMUX_FUNC_UARTA); - pinmux_set_func(PMUX_PINGRP_ULPI_DATA2_PO3, - PMUX_FUNC_UARTA); - pinmux_set_func(PMUX_PINGRP_ULPI_DATA3_PO4, - PMUX_FUNC_UARTA); - pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA0_PO1); - pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA1_PO2); - pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA2_PO3); - pinmux_tristate_disable(PMUX_PINGRP_ULPI_DATA3_PO4); - break; - } - break; - - /* Add other periph IDs here as needed */ - - default: - debug("%s: invalid periph_id %d", __func__, id); - return -1; - } - - if (bad_config) { - debug("%s: invalid config %d for periph_id %d", __func__, - config, id); - return -1; - } - return 0; -} diff --git a/arch/arm/mach-tegra/tegra30/pinmux.c b/arch/arm/mach-tegra/tegra30/pinmux.c deleted file mode 100644 index d11b2aa572..0000000000 --- a/arch/arm/mach-tegra/tegra30/pinmux.c +++ /dev/null @@ -1,275 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/pinmux.h> - -#define PIN(pin, f0, f1, f2, f3) \ - { \ - .funcs = { \ - PMUX_FUNC_##f0, \ - PMUX_FUNC_##f1, \ - PMUX_FUNC_##f2, \ - PMUX_FUNC_##f3, \ - }, \ - } - -#define PIN_RESERVED {} - -static const struct pmux_pingrp_desc tegra30_pingroups[] = { - /* pin, f0, f1, f2, f3 */ - /* Offset 0x3000 */ - PIN(ULPI_DATA0_PO1, SPI3, HSI, UARTA, ULPI), - PIN(ULPI_DATA1_PO2, SPI3, HSI, UARTA, ULPI), - PIN(ULPI_DATA2_PO3, SPI3, HSI, UARTA, ULPI), - PIN(ULPI_DATA3_PO4, SPI3, HSI, UARTA, ULPI), - PIN(ULPI_DATA4_PO5, SPI2, HSI, UARTA, ULPI), - PIN(ULPI_DATA5_PO6, SPI2, HSI, UARTA, ULPI), - PIN(ULPI_DATA6_PO7, SPI2, HSI, UARTA, ULPI), - PIN(ULPI_DATA7_PO0, SPI2, HSI, UARTA, ULPI), - PIN(ULPI_CLK_PY0, SPI1, RSVD2, UARTD, ULPI), - PIN(ULPI_DIR_PY1, SPI1, RSVD2, UARTD, ULPI), - PIN(ULPI_NXT_PY2, SPI1, RSVD2, UARTD, ULPI), - PIN(ULPI_STP_PY3, SPI1, RSVD2, UARTD, ULPI), - PIN(DAP3_FS_PP0, I2S2, RSVD2, DISPLAYA, DISPLAYB), - PIN(DAP3_DIN_PP1, I2S2, RSVD2, DISPLAYA, DISPLAYB), - PIN(DAP3_DOUT_PP2, I2S2, RSVD2, DISPLAYA, DISPLAYB), - PIN(DAP3_SCLK_PP3, I2S2, RSVD2, DISPLAYA, DISPLAYB), - PIN(PV0, RSVD1, RSVD2, RSVD3, RSVD4), - PIN(PV1, RSVD1, RSVD2, RSVD3, RSVD4), - PIN(SDMMC1_CLK_PZ0, SDMMC1, RSVD2, RSVD3, UARTA), - PIN(SDMMC1_CMD_PZ1, SDMMC1, RSVD2, RSVD3, UARTA), - PIN(SDMMC1_DAT3_PY4, SDMMC1, RSVD2, UARTE, UARTA), - PIN(SDMMC1_DAT2_PY5, SDMMC1, RSVD2, UARTE, UARTA), - PIN(SDMMC1_DAT1_PY6, SDMMC1, RSVD2, UARTE, UARTA), - PIN(SDMMC1_DAT0_PY7, SDMMC1, RSVD2, UARTE, UARTA), - PIN(PV2, OWR, RSVD2, RSVD3, RSVD4), - PIN(PV3, CLK_12M_OUT, RSVD2, RSVD3, RSVD4), - PIN(CLK2_OUT_PW5, EXTPERIPH2, RSVD2, RSVD3, RSVD4), - PIN(CLK2_REQ_PCC5, DAP, RSVD2, RSVD3, RSVD4), - PIN(LCD_PWR1_PC1, DISPLAYA, DISPLAYB, RSVD3, RSVD4), - PIN(LCD_PWR2_PC6, DISPLAYA, DISPLAYB, SPI5, HDCP), - PIN(LCD_SDIN_PZ2, DISPLAYA, DISPLAYB, SPI5, RSVD4), - PIN(LCD_SDOUT_PN5, DISPLAYA, DISPLAYB, SPI5, HDCP), - PIN(LCD_WR_N_PZ3, DISPLAYA, DISPLAYB, SPI5, HDCP), - PIN(LCD_CS0_N_PN4, DISPLAYA, DISPLAYB, SPI5, RSVD4), - PIN(LCD_DC0_PN6, DISPLAYA, DISPLAYB, RSVD3, RSVD4), - PIN(LCD_SCK_PZ4, DISPLAYA, DISPLAYB, SPI5, HDCP), - PIN(LCD_PWR0_PB2, DISPLAYA, DISPLAYB, SPI5, HDCP), - PIN(LCD_PCLK_PB3, DISPLAYA, DISPLAYB, RSVD3, RSVD4), - PIN(LCD_DE_PJ1, DISPLAYA, DISPLAYB, RSVD3, RSVD4), - PIN(LCD_HSYNC_PJ3, DISPLAYA, DISPLAYB, RSVD3, RSVD4), - PIN(LCD_VSYNC_PJ4, DISPLAYA, DISPLAYB, RSVD3, RSVD4), - PIN(LCD_D0_PE0, DISPLAYA, DISPLAYB, RSVD3, RSVD4), - PIN(LCD_D1_PE1, DISPLAYA, DISPLAYB, RSVD3, RSVD4), - PIN(LCD_D2_PE2, DISPLAYA, DISPLAYB, RSVD3, RSVD4), - PIN(LCD_D3_PE3, DISPLAYA, DISPLAYB, RSVD3, RSVD4), - PIN(LCD_D4_PE4, DISPLAYA, DISPLAYB, RSVD3, RSVD4), - PIN(LCD_D5_PE5, DISPLAYA, DISPLAYB, RSVD3, RSVD4), - PIN(LCD_D6_PE6, DISPLAYA, DISPLAYB, RSVD3, RSVD4), - PIN(LCD_D7_PE7, DISPLAYA, DISPLAYB, RSVD3, RSVD4), - PIN(LCD_D8_PF0, DISPLAYA, DISPLAYB, RSVD3, RSVD4), - PIN(LCD_D9_PF1, DISPLAYA, DISPLAYB, RSVD3, RSVD4), - PIN(LCD_D10_PF2, DISPLAYA, DISPLAYB, RSVD3, RSVD4), - PIN(LCD_D11_PF3, DISPLAYA, DISPLAYB, RSVD3, RSVD4), - PIN(LCD_D12_PF4, DISPLAYA, DISPLAYB, RSVD3, RSVD4), - PIN(LCD_D13_PF5, DISPLAYA, DISPLAYB, RSVD3, RSVD4), - PIN(LCD_D14_PF6, DISPLAYA, DISPLAYB, RSVD3, RSVD4), - PIN(LCD_D15_PF7, DISPLAYA, DISPLAYB, RSVD3, RSVD4), - PIN(LCD_D16_PM0, DISPLAYA, DISPLAYB, RSVD3, RSVD4), - PIN(LCD_D17_PM1, DISPLAYA, DISPLAYB, RSVD3, RSVD4), - PIN(LCD_D18_PM2, DISPLAYA, DISPLAYB, RSVD3, RSVD4), - PIN(LCD_D19_PM3, DISPLAYA, DISPLAYB, RSVD3, RSVD4), - PIN(LCD_D20_PM4, DISPLAYA, DISPLAYB, RSVD3, RSVD4), - PIN(LCD_D21_PM5, DISPLAYA, DISPLAYB, RSVD3, RSVD4), - PIN(LCD_D22_PM6, DISPLAYA, DISPLAYB, RSVD3, RSVD4), - PIN(LCD_D23_PM7, DISPLAYA, DISPLAYB, RSVD3, RSVD4), - PIN(LCD_CS1_N_PW0, DISPLAYA, DISPLAYB, SPI5, RSVD4), - PIN(LCD_M1_PW1, DISPLAYA, DISPLAYB, RSVD3, RSVD4), - PIN(LCD_DC1_PD2, DISPLAYA, DISPLAYB, RSVD3, RSVD4), - PIN(HDMI_INT_PN7, HDMI, RSVD2, RSVD3, RSVD4), - PIN(DDC_SCL_PV4, I2C4, RSVD2, RSVD3, RSVD4), - PIN(DDC_SDA_PV5, I2C4, RSVD2, RSVD3, RSVD4), - PIN(CRT_HSYNC_PV6, CRT, RSVD2, RSVD3, RSVD4), - PIN(CRT_VSYNC_PV7, CRT, RSVD2, RSVD3, RSVD4), - PIN(VI_D0_PT4, DDR, RSVD2, VI, RSVD4), - PIN(VI_D1_PD5, DDR, SDMMC2, VI, RSVD4), - PIN(VI_D2_PL0, DDR, SDMMC2, VI, RSVD4), - PIN(VI_D3_PL1, DDR, SDMMC2, VI, RSVD4), - PIN(VI_D4_PL2, DDR, SDMMC2, VI, RSVD4), - PIN(VI_D5_PL3, DDR, SDMMC2, VI, RSVD4), - PIN(VI_D6_PL4, DDR, SDMMC2, VI, RSVD4), - PIN(VI_D7_PL5, DDR, SDMMC2, VI, RSVD4), - PIN(VI_D8_PL6, DDR, SDMMC2, VI, RSVD4), - PIN(VI_D9_PL7, DDR, SDMMC2, VI, RSVD4), - PIN(VI_D10_PT2, DDR, RSVD2, VI, RSVD4), - PIN(VI_D11_PT3, DDR, RSVD2, VI, RSVD4), - PIN(VI_PCLK_PT0, RSVD1, SDMMC2, VI, RSVD4), - PIN(VI_MCLK_PT1, VI, VI_ALT1, VI_ALT2, VI_ALT3), - PIN(VI_VSYNC_PD6, DDR, RSVD2, VI, RSVD4), - PIN(VI_HSYNC_PD7, DDR, RSVD2, VI, RSVD4), - PIN(UART2_RXD_PC3, UARTB, SPDIF, UARTA, SPI4), - PIN(UART2_TXD_PC2, UARTB, SPDIF, UARTA, SPI4), - PIN(UART2_RTS_N_PJ6, UARTA, UARTB, GMI, SPI4), - PIN(UART2_CTS_N_PJ5, UARTA, UARTB, GMI, SPI4), - PIN(UART3_TXD_PW6, UARTC, RSVD2, GMI, RSVD4), - PIN(UART3_RXD_PW7, UARTC, RSVD2, GMI, RSVD4), - PIN(UART3_CTS_N_PA1, UARTC, RSVD2, GMI, RSVD4), - PIN(UART3_RTS_N_PC0, UARTC, PWM0, GMI, RSVD4), - PIN(PU0, OWR, UARTA, GMI, RSVD4), - PIN(PU1, RSVD1, UARTA, GMI, RSVD4), - PIN(PU2, RSVD1, UARTA, GMI, RSVD4), - PIN(PU3, PWM0, UARTA, GMI, RSVD4), - PIN(PU4, PWM1, UARTA, GMI, RSVD4), - PIN(PU5, PWM2, UARTA, GMI, RSVD4), - PIN(PU6, PWM3, UARTA, GMI, RSVD4), - PIN(GEN1_I2C_SDA_PC5, I2C1, RSVD2, RSVD3, RSVD4), - PIN(GEN1_I2C_SCL_PC4, I2C1, RSVD2, RSVD3, RSVD4), - PIN(DAP4_FS_PP4, I2S3, RSVD2, GMI, RSVD4), - PIN(DAP4_DIN_PP5, I2S3, RSVD2, GMI, RSVD4), - PIN(DAP4_DOUT_PP6, I2S3, RSVD2, GMI, RSVD4), - PIN(DAP4_SCLK_PP7, I2S3, RSVD2, GMI, RSVD4), - PIN(CLK3_OUT_PEE0, EXTPERIPH3, RSVD2, RSVD3, RSVD4), - PIN(CLK3_REQ_PEE1, DEV3, RSVD2, RSVD3, RSVD4), - PIN(GMI_WP_N_PC7, RSVD1, NAND, GMI, GMI_ALT), - PIN(GMI_IORDY_PI5, RSVD1, NAND, GMI, RSVD4), - PIN(GMI_WAIT_PI7, RSVD1, NAND, GMI, RSVD4), - PIN(GMI_ADV_N_PK0, RSVD1, NAND, GMI, RSVD4), - PIN(GMI_CLK_PK1, RSVD1, NAND, GMI, RSVD4), - PIN(GMI_CS0_N_PJ0, RSVD1, NAND, GMI, DTV), - PIN(GMI_CS1_N_PJ2, RSVD1, NAND, GMI, DTV), - PIN(GMI_CS2_N_PK3, RSVD1, NAND, GMI, RSVD4), - PIN(GMI_CS3_N_PK4, RSVD1, NAND, GMI, GMI_ALT), - PIN(GMI_CS4_N_PK2, RSVD1, NAND, GMI, RSVD4), - PIN(GMI_CS6_N_PI3, NAND, NAND_ALT, GMI, SATA), - PIN(GMI_CS7_N_PI6, NAND, NAND_ALT, GMI, GMI_ALT), - PIN(GMI_AD0_PG0, RSVD1, NAND, GMI, RSVD4), - PIN(GMI_AD1_PG1, RSVD1, NAND, GMI, RSVD4), - PIN(GMI_AD2_PG2, RSVD1, NAND, GMI, RSVD4), - PIN(GMI_AD3_PG3, RSVD1, NAND, GMI, RSVD4), - PIN(GMI_AD4_PG4, RSVD1, NAND, GMI, RSVD4), - PIN(GMI_AD5_PG5, RSVD1, NAND, GMI, RSVD4), - PIN(GMI_AD6_PG6, RSVD1, NAND, GMI, RSVD4), - PIN(GMI_AD7_PG7, RSVD1, NAND, GMI, RSVD4), - PIN(GMI_AD8_PH0, PWM0, NAND, GMI, RSVD4), - PIN(GMI_AD9_PH1, PWM1, NAND, GMI, RSVD4), - PIN(GMI_AD10_PH2, PWM2, NAND, GMI, RSVD4), - PIN(GMI_AD11_PH3, PWM3, NAND, GMI, RSVD4), - PIN(GMI_AD12_PH4, RSVD1, NAND, GMI, RSVD4), - PIN(GMI_AD13_PH5, RSVD1, NAND, GMI, RSVD4), - PIN(GMI_AD14_PH6, RSVD1, NAND, GMI, RSVD4), - PIN(GMI_AD15_PH7, RSVD1, NAND, GMI, RSVD4), - PIN(GMI_A16_PJ7, UARTD, SPI4, GMI, GMI_ALT), - PIN(GMI_A17_PB0, UARTD, SPI4, GMI, DTV), - PIN(GMI_A18_PB1, UARTD, SPI4, GMI, DTV), - PIN(GMI_A19_PK7, UARTD, SPI4, GMI, RSVD4), - PIN(GMI_WR_N_PI0, RSVD1, NAND, GMI, RSVD4), - PIN(GMI_OE_N_PI1, RSVD1, NAND, GMI, RSVD4), - PIN(GMI_DQS_PI2, RSVD1, NAND, GMI, RSVD4), - PIN(GMI_RST_N_PI4, NAND, NAND_ALT, GMI, RSVD4), - PIN(GEN2_I2C_SCL_PT5, I2C2, HDCP, GMI, RSVD4), - PIN(GEN2_I2C_SDA_PT6, I2C2, HDCP, GMI, RSVD4), - PIN(SDMMC4_CLK_PCC4, INVALID, NAND, GMI, SDMMC4), - PIN(SDMMC4_CMD_PT7, I2C3, NAND, GMI, SDMMC4), - PIN(SDMMC4_DAT0_PAA0, UARTE, SPI3, GMI, SDMMC4), - PIN(SDMMC4_DAT1_PAA1, UARTE, SPI3, GMI, SDMMC4), - PIN(SDMMC4_DAT2_PAA2, UARTE, SPI3, GMI, SDMMC4), - PIN(SDMMC4_DAT3_PAA3, UARTE, SPI3, GMI, SDMMC4), - PIN(SDMMC4_DAT4_PAA4, I2C3, I2S4, GMI, SDMMC4), - PIN(SDMMC4_DAT5_PAA5, VGP3, I2S4, GMI, SDMMC4), - PIN(SDMMC4_DAT6_PAA6, VGP4, I2S4, GMI, SDMMC4), - PIN(SDMMC4_DAT7_PAA7, VGP5, I2S4, GMI, SDMMC4), - PIN(SDMMC4_RST_N_PCC3, VGP6, RSVD2, RSVD3, SDMMC4), - PIN(CAM_MCLK_PCC0, VI, VI_ALT1, VI_ALT3, SDMMC4), - PIN(PCC1, I2S4, RSVD2, RSVD3, SDMMC4), - PIN(PBB0, I2S4, RSVD2, RSVD3, SDMMC4), - PIN(CAM_I2C_SCL_PBB1, VGP1, I2C3, RSVD3, SDMMC4), - PIN(CAM_I2C_SDA_PBB2, VGP2, I2C3, RSVD3, SDMMC4), - PIN(PBB3, VGP3, DISPLAYA, DISPLAYB, SDMMC4), - PIN(PBB4, VGP4, DISPLAYA, DISPLAYB, SDMMC4), - PIN(PBB5, VGP5, DISPLAYA, DISPLAYB, SDMMC4), - PIN(PBB6, VGP6, DISPLAYA, DISPLAYB, SDMMC4), - PIN(PBB7, I2S4, RSVD2, RSVD3, SDMMC4), - PIN(PCC2, I2S4, RSVD2, RSVD3, RSVD4), - PIN(JTAG_RTCK_PU7, RTCK, RSVD2, RSVD3, RSVD4), - PIN(PWR_I2C_SCL_PZ6, I2CPWR, RSVD2, RSVD3, RSVD4), - PIN(PWR_I2C_SDA_PZ7, I2CPWR, RSVD2, RSVD3, RSVD4), - PIN(KB_ROW0_PR0, KBC, NAND, RSVD3, RSVD4), - PIN(KB_ROW1_PR1, KBC, NAND, RSVD3, RSVD4), - PIN(KB_ROW2_PR2, KBC, NAND, RSVD3, RSVD4), - PIN(KB_ROW3_PR3, KBC, NAND, RSVD3, INVALID), - PIN(KB_ROW4_PR4, KBC, NAND, TRACE, RSVD4), - PIN(KB_ROW5_PR5, KBC, NAND, TRACE, OWR), - PIN(KB_ROW6_PR6, KBC, NAND, SDMMC2, MIO), - PIN(KB_ROW7_PR7, KBC, NAND, SDMMC2, MIO), - PIN(KB_ROW8_PS0, KBC, NAND, SDMMC2, MIO), - PIN(KB_ROW9_PS1, KBC, NAND, SDMMC2, MIO), - PIN(KB_ROW10_PS2, KBC, NAND, SDMMC2, MIO), - PIN(KB_ROW11_PS3, KBC, NAND, SDMMC2, MIO), - PIN(KB_ROW12_PS4, KBC, NAND, SDMMC2, MIO), - PIN(KB_ROW13_PS5, KBC, NAND, SDMMC2, MIO), - PIN(KB_ROW14_PS6, KBC, NAND, SDMMC2, MIO), - PIN(KB_ROW15_PS7, KBC, NAND, SDMMC2, MIO), - PIN(KB_COL0_PQ0, KBC, NAND, TRACE, TEST), - PIN(KB_COL1_PQ1, KBC, NAND, TRACE, TEST), - PIN(KB_COL2_PQ2, KBC, NAND, TRACE, RSVD4), - PIN(KB_COL3_PQ3, KBC, NAND, TRACE, RSVD4), - PIN(KB_COL4_PQ4, KBC, NAND, TRACE, RSVD4), - PIN(KB_COL5_PQ5, KBC, NAND, TRACE, RSVD4), - PIN(KB_COL6_PQ6, KBC, NAND, TRACE, MIO), - PIN(KB_COL7_PQ7, KBC, NAND, TRACE, MIO), - PIN(CLK_32K_OUT_PA0, BLINK, RSVD2, RSVD3, RSVD4), - PIN(SYS_CLK_REQ_PZ5, SYSCLK, RSVD2, RSVD3, RSVD4), - PIN(CORE_PWR_REQ, CORE_PWR_REQ, RSVD2, RSVD3, RSVD4), - PIN(CPU_PWR_REQ, CPU_PWR_REQ, RSVD2, RSVD3, RSVD4), - PIN(PWR_INT_N, PWR_INT_N, RSVD2, RSVD3, RSVD4), - PIN(CLK_32K_IN, CLK_32K_IN, RSVD2, RSVD3, RSVD4), - PIN(OWR, OWR, CEC, RSVD3, RSVD4), - PIN(DAP1_FS_PN0, I2S0, HDA, GMI, SDMMC2), - PIN(DAP1_DIN_PN1, I2S0, HDA, GMI, SDMMC2), - PIN(DAP1_DOUT_PN2, I2S0, HDA, GMI, SDMMC2), - PIN(DAP1_SCLK_PN3, I2S0, HDA, GMI, SDMMC2), - PIN(CLK1_REQ_PEE2, DAP, HDA, RSVD3, RSVD4), - PIN(CLK1_OUT_PW4, EXTPERIPH1, RSVD2, RSVD3, RSVD4), - PIN(SPDIF_IN_PK6, SPDIF, HDA, I2C1, SDMMC2), - PIN(SPDIF_OUT_PK5, SPDIF, RSVD2, I2C1, SDMMC2), - PIN(DAP2_FS_PA2, I2S1, HDA, RSVD3, GMI), - PIN(DAP2_DIN_PA4, I2S1, HDA, RSVD3, GMI), - PIN(DAP2_DOUT_PA5, I2S1, HDA, RSVD3, GMI), - PIN(DAP2_SCLK_PA3, I2S1, HDA, RSVD3, GMI), - PIN(SPI2_MOSI_PX0, SPI6, SPI2, SPI3, GMI), - PIN(SPI2_MISO_PX1, SPI6, SPI2, SPI3, GMI), - PIN(SPI2_CS0_N_PX3, SPI6, SPI2, SPI3, GMI), - PIN(SPI2_SCK_PX2, SPI6, SPI2, SPI3, GMI), - PIN(SPI1_MOSI_PX4, SPI2, SPI1, SPI2_ALT, GMI), - PIN(SPI1_SCK_PX5, SPI2, SPI1, SPI2_ALT, GMI), - PIN(SPI1_CS0_N_PX6, SPI2, SPI1, SPI2_ALT, GMI), - PIN(SPI1_MISO_PX7, SPI3, SPI1, SPI2_ALT, RSVD4), - PIN(SPI2_CS1_N_PW2, SPI3, SPI2, SPI2_ALT, I2C1), - PIN(SPI2_CS2_N_PW3, SPI3, SPI2, SPI2_ALT, I2C1), - PIN(SDMMC3_CLK_PA6, UARTA, PWM2, SDMMC3, SPI3), - PIN(SDMMC3_CMD_PA7, UARTA, PWM3, SDMMC3, SPI2), - PIN(SDMMC3_DAT0_PB7, RSVD1, RSVD2, SDMMC3, SPI3), - PIN(SDMMC3_DAT1_PB6, RSVD1, RSVD2, SDMMC3, SPI3), - PIN(SDMMC3_DAT2_PB5, RSVD1, PWM1, SDMMC3, SPI3), - PIN(SDMMC3_DAT3_PB4, RSVD1, PWM0, SDMMC3, SPI3), - PIN(SDMMC3_DAT4_PD1, PWM1, SPI4, SDMMC3, SPI2), - PIN(SDMMC3_DAT5_PD0, PWM0, SPI4, SDMMC3, SPI2), - PIN(SDMMC3_DAT6_PD3, SPDIF, SPI4, SDMMC3, SPI2), - PIN(SDMMC3_DAT7_PD4, SPDIF, SPI4, SDMMC3, SPI2), - PIN(PEX_L0_PRSNT_N_PDD0, PCIE, HDA, RSVD3, RSVD4), - PIN(PEX_L0_RST_N_PDD1, PCIE, HDA, RSVD3, RSVD4), - PIN(PEX_L0_CLKREQ_N_PDD2, PCIE, HDA, RSVD3, RSVD4), - PIN(PEX_WAKE_N_PDD3, PCIE, HDA, RSVD3, RSVD4), - PIN(PEX_L1_PRSNT_N_PDD4, PCIE, HDA, RSVD3, RSVD4), - PIN(PEX_L1_RST_N_PDD5, PCIE, HDA, RSVD3, RSVD4), - PIN(PEX_L1_CLKREQ_N_PDD6, PCIE, HDA, RSVD3, RSVD4), - PIN(PEX_L2_PRSNT_N_PDD7, PCIE, HDA, RSVD3, RSVD4), - PIN(PEX_L2_RST_N_PCC6, PCIE, HDA, RSVD3, RSVD4), - PIN(PEX_L2_CLKREQ_N_PCC7, PCIE, HDA, RSVD3, RSVD4), - PIN(HDMI_CEC_PEE3, CEC, RSVD2, RSVD3, RSVD4), -}; -const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra30_pingroups; |