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-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/cpu.h96
-rw-r--r--arch/arm/include/asm/arch-rockchip/ddr_rk3288.h2
-rw-r--r--arch/arm/include/asm/arch-rockchip/sdram_rk322x.h2
-rw-r--r--arch/arm/include/asm/arch-sunxi/i2c.h2
4 files changed, 51 insertions, 51 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 20f9671387..444b56606a 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -8,32 +8,32 @@
#define _FSL_LAYERSCAPE_CPU_H
#ifdef CONFIG_FSL_LSCH3
-#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
-#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
+#define CFG_SYS_FSL_CCSR_BASE 0x00000000
+#define CFG_SYS_FSL_CCSR_SIZE 0x10000000
#define CFG_SYS_FSL_QSPI_BASE1 0x20000000
-#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
+#define CFG_SYS_FSL_QSPI_SIZE1 0x10000000
#ifndef CONFIG_NXP_LSCH3_2
-#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
-#define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000
-#define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000
+#define CFG_SYS_FSL_IFC_BASE1 0x30000000
+#define CFG_SYS_FSL_IFC_SIZE1 0x10000000
+#define CFG_SYS_FSL_IFC_SIZE1_1 0x400000
#endif
-#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
-#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
+#define CFG_SYS_FSL_DRAM_BASE1 0x80000000
+#define CFG_SYS_FSL_DRAM_SIZE1 0x80000000
#define CFG_SYS_FSL_QSPI_BASE2 0x400000000
-#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000
+#define CFG_SYS_FSL_QSPI_SIZE2 0x100000000
#ifndef CONFIG_NXP_LSCH3_2
-#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000
-#define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000
+#define CFG_SYS_FSL_IFC_BASE2 0x500000000
+#define CFG_SYS_FSL_IFC_SIZE2 0x100000000
#endif
-#define CONFIG_SYS_FSL_DCSR_BASE 0x700000000
-#define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000
-#define CONFIG_SYS_FSL_MC_BASE 0x80c000000
-#define CONFIG_SYS_FSL_MC_SIZE 0x4000000
-#define CONFIG_SYS_FSL_NI_BASE 0x810000000
-#define CONFIG_SYS_FSL_NI_SIZE 0x8000000
-#define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000
-#define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000
-#define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000
+#define CFG_SYS_FSL_DCSR_BASE 0x700000000
+#define CFG_SYS_FSL_DCSR_SIZE 0x40000000
+#define CFG_SYS_FSL_MC_BASE 0x80c000000
+#define CFG_SYS_FSL_MC_SIZE 0x4000000
+#define CFG_SYS_FSL_NI_BASE 0x810000000
+#define CFG_SYS_FSL_NI_SIZE 0x8000000
+#define CFG_SYS_FSL_QBMAN_BASE 0x818000000
+#define CFG_SYS_FSL_QBMAN_SIZE 0x8000000
+#define CFG_SYS_FSL_QBMAN_SIZE_1 0x4000000
#ifdef CONFIG_ARCH_LS2080A
#define CFG_SYS_PCIE1_PHYS_SIZE 0x200000000
#define CFG_SYS_PCIE2_PHYS_SIZE 0x200000000
@@ -49,45 +49,45 @@
#define SYS_PCIE5_PHYS_SIZE 0x800000000
#define SYS_PCIE6_PHYS_SIZE 0x800000000
#endif
-#define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000
-#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000
-#define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000
-#define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000
+#define CFG_SYS_FSL_WRIOP1_BASE 0x4300000000
+#define CFG_SYS_FSL_WRIOP1_SIZE 0x100000000
+#define CFG_SYS_FSL_AIOP1_BASE 0x4b00000000
+#define CFG_SYS_FSL_AIOP1_SIZE 0x100000000
#if !defined(CONFIG_ARCH_LX2160A) || !defined(CONFIG_ARCH_LX2162)
-#define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000
+#define CFG_SYS_FSL_PEBUF_BASE 0x4c00000000
#else
-#define CONFIG_SYS_FSL_PEBUF_BASE 0x1c00000000
+#define CFG_SYS_FSL_PEBUF_BASE 0x1c00000000
#endif
-#define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000
+#define CFG_SYS_FSL_PEBUF_SIZE 0x400000000
#ifdef CONFIG_NXP_LSCH3_2
-#define CONFIG_SYS_FSL_DRAM_BASE2 0x2080000000
-#define CONFIG_SYS_FSL_DRAM_SIZE2 0x1F80000000
-#define CONFIG_SYS_FSL_DRAM_BASE3 0x6000000000
-#define CONFIG_SYS_FSL_DRAM_SIZE3 0x2000000000
+#define CFG_SYS_FSL_DRAM_BASE2 0x2080000000
+#define CFG_SYS_FSL_DRAM_SIZE2 0x1F80000000
+#define CFG_SYS_FSL_DRAM_BASE3 0x6000000000
+#define CFG_SYS_FSL_DRAM_SIZE3 0x2000000000
#else
-#define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000
-#define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000
+#define CFG_SYS_FSL_DRAM_BASE2 0x8080000000
+#define CFG_SYS_FSL_DRAM_SIZE2 0x7F80000000
#endif
#elif defined(CONFIG_FSL_LSCH2)
-#define CONFIG_SYS_FSL_CCSR_BASE 0x1000000
-#define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000
-#define CONFIG_SYS_FSL_DCSR_BASE 0x20000000
-#define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000
+#define CFG_SYS_FSL_CCSR_BASE 0x1000000
+#define CFG_SYS_FSL_CCSR_SIZE 0xf000000
+#define CFG_SYS_FSL_DCSR_BASE 0x20000000
+#define CFG_SYS_FSL_DCSR_SIZE 0x4000000
#define CFG_SYS_FSL_QSPI_BASE 0x40000000
-#define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000
-#define CONFIG_SYS_FSL_IFC_BASE 0x60000000
-#define CONFIG_SYS_FSL_IFC_SIZE 0x20000000
-#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
-#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
-#define CONFIG_SYS_FSL_QBMAN_BASE 0x500000000
-#define CONFIG_SYS_FSL_QBMAN_SIZE 0x10000000
-#define CONFIG_SYS_FSL_DRAM_BASE2 0x880000000
-#define CONFIG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */
+#define CFG_SYS_FSL_QSPI_SIZE 0x20000000
+#define CFG_SYS_FSL_IFC_BASE 0x60000000
+#define CFG_SYS_FSL_IFC_SIZE 0x20000000
+#define CFG_SYS_FSL_DRAM_BASE1 0x80000000
+#define CFG_SYS_FSL_DRAM_SIZE1 0x80000000
+#define CFG_SYS_FSL_QBMAN_BASE 0x500000000
+#define CFG_SYS_FSL_QBMAN_SIZE 0x10000000
+#define CFG_SYS_FSL_DRAM_BASE2 0x880000000
+#define CFG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */
#define CFG_SYS_PCIE1_PHYS_SIZE 0x800000000
#define CFG_SYS_PCIE2_PHYS_SIZE 0x800000000
#define CFG_SYS_PCIE3_PHYS_SIZE 0x800000000
-#define CONFIG_SYS_FSL_DRAM_BASE3 0x8800000000
-#define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */
+#define CFG_SYS_FSL_DRAM_BASE3 0x8800000000
+#define CFG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */
#endif
int fsl_qoriq_core_to_cluster(unsigned int core);
diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h
index 979d5470e7..43ccae10bd 100644
--- a/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h
@@ -360,7 +360,7 @@ check_member(rk3288_msch, devtodev, 0x003c);
#define PCTL_STAT_MSK 7
#define INIT_MEM 0
#define CONFIG 1
-#define CONFIG_REQ 2
+#define CFG_REQ 2
#define ACCESS 3
#define ACCESS_REQ 4
#define LOW_POWER 5
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h b/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h
index 6f6c5c9954..0d29aefb64 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h
@@ -415,7 +415,7 @@ struct rk322x_base_params {
#define PCTL_STAT_MASK 7
#define INIT_MEM 0
#define CONFIG 1
-#define CONFIG_REQ 2
+#define CFG_REQ 2
#define ACCESS 3
#define ACCESS_REQ 4
#define LOW_POWER 5
diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h
index e3dcfdf370..f0da46d863 100644
--- a/arch/arm/include/asm/arch-sunxi/i2c.h
+++ b/arch/arm/include/asm/arch-sunxi/i2c.h
@@ -14,7 +14,7 @@
#define CFG_I2C_MVTWSI_BASE1 SUNXI_TWI1_BASE
#endif
#ifdef CONFIG_R_I2C_ENABLE
-#define CONFIG_I2C_MVTWSI_BASE2 SUNXI_R_TWI_BASE
+#define CFG_I2C_MVTWSI_BASE2 SUNXI_R_TWI_BASE
#endif
/* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-16 21:41:27 +0000