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-rw-r--r--arch/arm/cpu/arm1176/start.S6
-rw-r--r--arch/arm/cpu/armv7/ls102xa/Kconfig13
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/Kconfig16
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/cpu.c166
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c7
-rw-r--r--arch/arm/cpu/armv8/u-boot.lds6
-rw-r--r--arch/arm/cpu/u-boot.lds6
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/cpu.h96
-rw-r--r--arch/arm/include/asm/arch-rockchip/ddr_rk3288.h2
-rw-r--r--arch/arm/include/asm/arch-rockchip/sdram_rk322x.h2
-rw-r--r--arch/arm/include/asm/arch-sunxi/i2c.h2
-rw-r--r--arch/arm/lib/lib1funcs.S9
-rw-r--r--arch/arm/mach-at91/include/mach/at91rm9200.h2
-rw-r--r--arch/arm/mach-omap2/fdt-common.c4
-rw-r--r--arch/arm/mach-omap2/omap5/fdt.c8
-rw-r--r--arch/arm/mach-rmobile/include/mach/rcar-mstp.h96
-rw-r--r--arch/arm/mach-rockchip/rk3036/sdram_rk3036.c2
-rw-r--r--arch/arm/mach-tegra/tegra20/warmboot_avp.c2
-rw-r--r--arch/arm/mach-tegra/tegra20/warmboot_avp.h4
19 files changed, 207 insertions, 242 deletions
diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S
index 9e76a4a9e0..78a9cc173a 100644
--- a/arch/arm/cpu/arm1176/start.S
+++ b/arch/arm/cpu/arm1176/start.S
@@ -17,10 +17,6 @@
#include <config.h>
#include <linux/linkage.h>
-#ifndef CONFIG_SYS_PHY_UBOOT_BASE
-#define CONFIG_SYS_PHY_UBOOT_BASE CFG_SYS_UBOOT_BASE
-#endif
-
/*
*************************************************************************
*
@@ -88,7 +84,7 @@ cpu_init_crit:
/* Prepare to disable the MMU */
adr r2, mmu_disable_phys
- sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_TEXT_BASE)
+ sub r2, r2, #(CFG_SYS_UBOOT_BASE - CONFIG_TEXT_BASE)
b mmu_disable
.align 5
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index a83eb7e8fd..0edcf4c5ee 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -93,19 +93,6 @@ config SYS_FSL_ERRATUM_A010315
config SYS_FSL_HAS_CCI400
bool
-config SYS_FSL_SRDS_1
- bool
-
-config SYS_FSL_SRDS_2
- bool
-
-config SYS_HAS_SERDES
- bool
-
-config SYS_FSL_IFC_BANK_COUNT
- int "Maximum banks of Integrated flash controller"
- default 8
-
config SYS_FSL_ERRATUM_A008407
bool
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 9656c52e95..a8b493e2f8 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -525,13 +525,6 @@ config SYS_CCI400_OFFSET
Offset for CCI400 base
CCI400 base addr = CCSRBAR + CCI400_OFFSET
-config SYS_FSL_IFC_BANK_COUNT
- int "Maximum banks of Integrated flash controller"
- depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
- default 4 if ARCH_LS1043A
- default 4 if ARCH_LS1046A
- default 8 if ARCH_LS2080A || ARCH_LS1088A
-
config SYS_FSL_HAS_CCI400
bool
@@ -574,18 +567,9 @@ config SYS_DP_DDR_BASE_PHY
DDR controller uses this value as the base address for binding.
It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
-config SYS_FSL_SRDS_1
- bool
-
-config SYS_FSL_SRDS_2
- bool
-
config SYS_NXP_SRDS_3
bool
-config SYS_HAS_SERDES
- bool
-
config FSL_TZASC_1
bool
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 5c45c2a5ed..b0e8678533 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -91,8 +91,8 @@ static struct cpu_type cpu_type_list[] = {
#define EARLY_PGTABLE_SIZE 0x5000
static struct mm_region early_map[] = {
#ifdef CONFIG_FSL_LSCH3
- { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
- CONFIG_SYS_FSL_CCSR_SIZE,
+ { CFG_SYS_FSL_CCSR_BASE, CFG_SYS_FSL_CCSR_BASE,
+ CFG_SYS_FSL_CCSR_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
@@ -101,26 +101,26 @@ static struct mm_region early_map[] = {
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
},
{ CFG_SYS_FSL_QSPI_BASE1, CFG_SYS_FSL_QSPI_BASE1,
- CONFIG_SYS_FSL_QSPI_SIZE1,
+ CFG_SYS_FSL_QSPI_SIZE1,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
#ifdef CONFIG_FSL_IFC
/* For IFC Region #1, only the first 4MB is cache-enabled */
- { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
- CONFIG_SYS_FSL_IFC_SIZE1_1,
+ { CFG_SYS_FSL_IFC_BASE1, CFG_SYS_FSL_IFC_BASE1,
+ CFG_SYS_FSL_IFC_SIZE1_1,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
},
- { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
- CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
- CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
+ { CFG_SYS_FSL_IFC_BASE1 + CFG_SYS_FSL_IFC_SIZE1_1,
+ CFG_SYS_FSL_IFC_BASE1 + CFG_SYS_FSL_IFC_SIZE1_1,
+ CFG_SYS_FSL_IFC_SIZE1 - CFG_SYS_FSL_IFC_SIZE1_1,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
- { CFG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
- CONFIG_SYS_FSL_IFC_SIZE1,
+ { CFG_SYS_FLASH_BASE, CFG_SYS_FSL_IFC_BASE1,
+ CFG_SYS_FSL_IFC_SIZE1,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
#endif
- { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
- CONFIG_SYS_FSL_DRAM_SIZE1,
+ { CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_BASE1,
+ CFG_SYS_FSL_DRAM_SIZE1,
#if defined(CONFIG_TFABOOT) || \
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
@@ -131,31 +131,31 @@ static struct mm_region early_map[] = {
},
#ifdef CONFIG_FSL_IFC
/* Map IFC region #2 up to CFG_SYS_FLASH_BASE for NAND boot */
- { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
- CFG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
+ { CFG_SYS_FSL_IFC_BASE2, CFG_SYS_FSL_IFC_BASE2,
+ CFG_SYS_FLASH_BASE - CFG_SYS_FSL_IFC_BASE2,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
#endif
- { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
- CONFIG_SYS_FSL_DCSR_SIZE,
+ { CFG_SYS_FSL_DCSR_BASE, CFG_SYS_FSL_DCSR_BASE,
+ CFG_SYS_FSL_DCSR_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
- CONFIG_SYS_FSL_DRAM_SIZE2,
+ { CFG_SYS_FSL_DRAM_BASE2, CFG_SYS_FSL_DRAM_BASE2,
+ CFG_SYS_FSL_DRAM_SIZE2,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
-#ifdef CONFIG_SYS_FSL_DRAM_BASE3
- { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
- CONFIG_SYS_FSL_DRAM_SIZE3,
+#ifdef CFG_SYS_FSL_DRAM_BASE3
+ { CFG_SYS_FSL_DRAM_BASE3, CFG_SYS_FSL_DRAM_BASE3,
+ CFG_SYS_FSL_DRAM_SIZE3,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
#endif
#elif defined(CONFIG_FSL_LSCH2)
- { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
- CONFIG_SYS_FSL_CCSR_SIZE,
+ { CFG_SYS_FSL_CCSR_BASE, CFG_SYS_FSL_CCSR_BASE,
+ CFG_SYS_FSL_CCSR_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
@@ -163,23 +163,23 @@ static struct mm_region early_map[] = {
SYS_FSL_OCRAM_SPACE_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
},
- { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
- CONFIG_SYS_FSL_DCSR_SIZE,
+ { CFG_SYS_FSL_DCSR_BASE, CFG_SYS_FSL_DCSR_BASE,
+ CFG_SYS_FSL_DCSR_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
{ CFG_SYS_FSL_QSPI_BASE, CFG_SYS_FSL_QSPI_BASE,
- CONFIG_SYS_FSL_QSPI_SIZE,
+ CFG_SYS_FSL_QSPI_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
#ifdef CONFIG_FSL_IFC
- { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
- CONFIG_SYS_FSL_IFC_SIZE,
+ { CFG_SYS_FSL_IFC_BASE, CFG_SYS_FSL_IFC_BASE,
+ CFG_SYS_FSL_IFC_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
#endif
- { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
- CONFIG_SYS_FSL_DRAM_SIZE1,
+ { CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_BASE1,
+ CFG_SYS_FSL_DRAM_SIZE1,
#if defined(CONFIG_TFABOOT) || \
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
@@ -188,8 +188,8 @@ static struct mm_region early_map[] = {
#endif
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
- { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
- CONFIG_SYS_FSL_DRAM_SIZE2,
+ { CFG_SYS_FSL_DRAM_BASE2, CFG_SYS_FSL_DRAM_BASE2,
+ CFG_SYS_FSL_DRAM_SIZE2,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
@@ -199,8 +199,8 @@ static struct mm_region early_map[] = {
static struct mm_region final_map[] = {
#ifdef CONFIG_FSL_LSCH3
- { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
- CONFIG_SYS_FSL_CCSR_SIZE,
+ { CFG_SYS_FSL_CCSR_BASE, CFG_SYS_FSL_CCSR_BASE,
+ CFG_SYS_FSL_CCSR_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
@@ -208,52 +208,52 @@ static struct mm_region final_map[] = {
SYS_FSL_OCRAM_SPACE_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
},
- { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
- CONFIG_SYS_FSL_DRAM_SIZE1,
+ { CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_BASE1,
+ CFG_SYS_FSL_DRAM_SIZE1,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
{ CFG_SYS_FSL_QSPI_BASE1, CFG_SYS_FSL_QSPI_BASE1,
- CONFIG_SYS_FSL_QSPI_SIZE1,
+ CFG_SYS_FSL_QSPI_SIZE1,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
{ CFG_SYS_FSL_QSPI_BASE2, CFG_SYS_FSL_QSPI_BASE2,
- CONFIG_SYS_FSL_QSPI_SIZE2,
+ CFG_SYS_FSL_QSPI_SIZE2,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
#ifdef CONFIG_FSL_IFC
- { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
- CONFIG_SYS_FSL_IFC_SIZE2,
+ { CFG_SYS_FSL_IFC_BASE2, CFG_SYS_FSL_IFC_BASE2,
+ CFG_SYS_FSL_IFC_SIZE2,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
#endif
- { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
- CONFIG_SYS_FSL_DCSR_SIZE,
+ { CFG_SYS_FSL_DCSR_BASE, CFG_SYS_FSL_DCSR_BASE,
+ CFG_SYS_FSL_DCSR_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
- CONFIG_SYS_FSL_MC_SIZE,
+ { CFG_SYS_FSL_MC_BASE, CFG_SYS_FSL_MC_BASE,
+ CFG_SYS_FSL_MC_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
- CONFIG_SYS_FSL_NI_SIZE,
+ { CFG_SYS_FSL_NI_BASE, CFG_SYS_FSL_NI_BASE,
+ CFG_SYS_FSL_NI_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
/* For QBMAN portal, only the first 64MB is cache-enabled */
- { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
- CONFIG_SYS_FSL_QBMAN_SIZE_1,
+ { CFG_SYS_FSL_QBMAN_BASE, CFG_SYS_FSL_QBMAN_BASE,
+ CFG_SYS_FSL_QBMAN_SIZE_1,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
},
- { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
- CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
- CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
+ { CFG_SYS_FSL_QBMAN_BASE + CFG_SYS_FSL_QBMAN_SIZE_1,
+ CFG_SYS_FSL_QBMAN_BASE + CFG_SYS_FSL_QBMAN_SIZE_1,
+ CFG_SYS_FSL_QBMAN_SIZE - CFG_SYS_FSL_QBMAN_SIZE_1,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
@@ -295,29 +295,29 @@ static struct mm_region final_map[] = {
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
#endif
- { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
- CONFIG_SYS_FSL_WRIOP1_SIZE,
+ { CFG_SYS_FSL_WRIOP1_BASE, CFG_SYS_FSL_WRIOP1_BASE,
+ CFG_SYS_FSL_WRIOP1_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
- CONFIG_SYS_FSL_AIOP1_SIZE,
+ { CFG_SYS_FSL_AIOP1_BASE, CFG_SYS_FSL_AIOP1_BASE,
+ CFG_SYS_FSL_AIOP1_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
- CONFIG_SYS_FSL_PEBUF_SIZE,
+ { CFG_SYS_FSL_PEBUF_BASE, CFG_SYS_FSL_PEBUF_BASE,
+ CFG_SYS_FSL_PEBUF_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
- CONFIG_SYS_FSL_DRAM_SIZE2,
+ { CFG_SYS_FSL_DRAM_BASE2, CFG_SYS_FSL_DRAM_BASE2,
+ CFG_SYS_FSL_DRAM_SIZE2,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
-#ifdef CONFIG_SYS_FSL_DRAM_BASE3
- { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
- CONFIG_SYS_FSL_DRAM_SIZE3,
+#ifdef CFG_SYS_FSL_DRAM_BASE3
+ { CFG_SYS_FSL_DRAM_BASE3, CFG_SYS_FSL_DRAM_BASE3,
+ CFG_SYS_FSL_DRAM_SIZE3,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
@@ -328,8 +328,8 @@ static struct mm_region final_map[] = {
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
- CONFIG_SYS_FSL_CCSR_SIZE,
+ { CFG_SYS_FSL_CCSR_BASE, CFG_SYS_FSL_CCSR_BASE,
+ CFG_SYS_FSL_CCSR_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
@@ -337,34 +337,34 @@ static struct mm_region final_map[] = {
SYS_FSL_OCRAM_SPACE_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
},
- { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
- CONFIG_SYS_FSL_DCSR_SIZE,
+ { CFG_SYS_FSL_DCSR_BASE, CFG_SYS_FSL_DCSR_BASE,
+ CFG_SYS_FSL_DCSR_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
{ CFG_SYS_FSL_QSPI_BASE, CFG_SYS_FSL_QSPI_BASE,
- CONFIG_SYS_FSL_QSPI_SIZE,
+ CFG_SYS_FSL_QSPI_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
#ifdef CONFIG_FSL_IFC
- { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
- CONFIG_SYS_FSL_IFC_SIZE,
+ { CFG_SYS_FSL_IFC_BASE, CFG_SYS_FSL_IFC_BASE,
+ CFG_SYS_FSL_IFC_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
#endif
- { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
- CONFIG_SYS_FSL_DRAM_SIZE1,
+ { CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_BASE1,
+ CFG_SYS_FSL_DRAM_SIZE1,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
- { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
- CONFIG_SYS_FSL_QBMAN_SIZE,
+ { CFG_SYS_FSL_QBMAN_BASE, CFG_SYS_FSL_QBMAN_BASE,
+ CFG_SYS_FSL_QBMAN_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
- CONFIG_SYS_FSL_DRAM_SIZE2,
+ { CFG_SYS_FSL_DRAM_BASE2, CFG_SYS_FSL_DRAM_BASE2,
+ CFG_SYS_FSL_DRAM_SIZE2,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
@@ -385,8 +385,8 @@ static struct mm_region final_map[] = {
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
#endif
- { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
- CONFIG_SYS_FSL_DRAM_SIZE3,
+ { CFG_SYS_FSL_DRAM_BASE3, CFG_SYS_FSL_DRAM_BASE3,
+ CFG_SYS_FSL_DRAM_SIZE3,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
@@ -536,13 +536,13 @@ static inline void final_mmu_setup(void)
* table.
*/
switch (final_map[index].virt) {
- case CONFIG_SYS_FSL_DRAM_BASE1:
+ case CFG_SYS_FSL_DRAM_BASE1:
final_map[index].virt = gd->bd->bi_dram[0].start;
final_map[index].phys = gd->bd->bi_dram[0].start;
final_map[index].size = gd->bd->bi_dram[0].size;
break;
-#ifdef CONFIG_SYS_FSL_DRAM_BASE2
- case CONFIG_SYS_FSL_DRAM_BASE2:
+#ifdef CFG_SYS_FSL_DRAM_BASE2
+ case CFG_SYS_FSL_DRAM_BASE2:
#if (CONFIG_NR_DRAM_BANKS >= 2)
final_map[index].virt = gd->bd->bi_dram[1].start;
final_map[index].phys = gd->bd->bi_dram[1].start;
@@ -552,8 +552,8 @@ static inline void final_mmu_setup(void)
#endif
break;
#endif
-#ifdef CONFIG_SYS_FSL_DRAM_BASE3
- case CONFIG_SYS_FSL_DRAM_BASE3:
+#ifdef CFG_SYS_FSL_DRAM_BASE3
+ case CFG_SYS_FSL_DRAM_BASE3:
#if (CONFIG_NR_DRAM_BANKS >= 3)
final_map[index].virt = gd->bd->bi_dram[2].start;
final_map[index].phys = gd->bd->bi_dram[2].start;
@@ -1566,7 +1566,7 @@ void update_early_mmu_table(void)
if (!gd->arch.tlb_addr)
return;
- if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
+ if (gd->ram_size <= CFG_SYS_FSL_DRAM_SIZE1) {
mmu_change_region_attr(
CFG_SYS_SDRAM_BASE,
gd->ram_size,
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index f18407b6d3..4455eb1726 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -48,10 +48,11 @@ void get_sys_info(struct sys_info *sys_info)
unsigned long cluster_clk;
sys_info->freq_systembus = sysclk;
-#ifndef CONFIG_CLUSTER_CLK_FREQ
-#define CONFIG_CLUSTER_CLK_FREQ get_board_sys_clk()
-#endif
+#ifdef CONFIG_CLUSTER_CLK_FREQ
cluster_clk = CONFIG_CLUSTER_CLK_FREQ;
+#else
+ cluster_clk = get_board_sys_clk();
+#endif
#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
sys_info->freq_ddrbus = get_board_ddr_clk();
diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds
index 8fe4682dd2..fb6a30c922 100644
--- a/arch/arm/cpu/armv8/u-boot.lds
+++ b/arch/arm/cpu/armv8/u-boot.lds
@@ -51,10 +51,12 @@ SECTIONS
}
#ifndef CONFIG_ARMV8_SECURE_BASE
-#define CONFIG_ARMV8_SECURE_BASE
+#define __ARMV8_SECURE_BASE
#define __ARMV8_PSCI_STACK_IN_RAM
+#else
+#define __ARMV8_SECURE_BASE CONFIG_ARMV8_SECURE_BASE
#endif
- .secure_text CONFIG_ARMV8_SECURE_BASE :
+ .secure_text __ARMV8_SECURE_BASE :
AT(ADDR(.__secure_start) + SIZEOF(.__secure_start))
{
*(._secure.text)
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index f25f72b2e0..fc4f63d834 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -77,11 +77,13 @@ SECTIONS
}
#ifndef CONFIG_ARMV7_SECURE_BASE
-#define CONFIG_ARMV7_SECURE_BASE
+#define __ARMV7_SECURE_BASE
#define __ARMV7_PSCI_STACK_IN_RAM
+#else
+#define __ARMV7_SECURE_BASE CONFIG_ARMV7_SECURE_BASE
#endif
- .secure_text CONFIG_ARMV7_SECURE_BASE :
+ .secure_text __ARMV7_SECURE_BASE :
AT(ADDR(.__secure_start) + SIZEOF(.__secure_start))
{
*(._secure.text)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 20f9671387..444b56606a 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -8,32 +8,32 @@
#define _FSL_LAYERSCAPE_CPU_H
#ifdef CONFIG_FSL_LSCH3
-#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
-#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
+#define CFG_SYS_FSL_CCSR_BASE 0x00000000
+#define CFG_SYS_FSL_CCSR_SIZE 0x10000000
#define CFG_SYS_FSL_QSPI_BASE1 0x20000000
-#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
+#define CFG_SYS_FSL_QSPI_SIZE1 0x10000000
#ifndef CONFIG_NXP_LSCH3_2
-#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
-#define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000
-#define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000
+#define CFG_SYS_FSL_IFC_BASE1 0x30000000
+#define CFG_SYS_FSL_IFC_SIZE1 0x10000000
+#define CFG_SYS_FSL_IFC_SIZE1_1 0x400000
#endif
-#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
-#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
+#define CFG_SYS_FSL_DRAM_BASE1 0x80000000
+#define CFG_SYS_FSL_DRAM_SIZE1 0x80000000
#define CFG_SYS_FSL_QSPI_BASE2 0x400000000
-#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000
+#define CFG_SYS_FSL_QSPI_SIZE2 0x100000000
#ifndef CONFIG_NXP_LSCH3_2
-#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000
-#define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000
+#define CFG_SYS_FSL_IFC_BASE2 0x500000000
+#define CFG_SYS_FSL_IFC_SIZE2 0x100000000
#endif
-#define CONFIG_SYS_FSL_DCSR_BASE 0x700000000
-#define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000
-#define CONFIG_SYS_FSL_MC_BASE 0x80c000000
-#define CONFIG_SYS_FSL_MC_SIZE 0x4000000
-#define CONFIG_SYS_FSL_NI_BASE 0x810000000
-#define CONFIG_SYS_FSL_NI_SIZE 0x8000000
-#define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000
-#define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000
-#define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000
+#define CFG_SYS_FSL_DCSR_BASE 0x700000000
+#define CFG_SYS_FSL_DCSR_SIZE 0x40000000
+#define CFG_SYS_FSL_MC_BASE 0x80c000000
+#define CFG_SYS_FSL_MC_SIZE 0x4000000
+#define CFG_SYS_FSL_NI_BASE 0x810000000
+#define CFG_SYS_FSL_NI_SIZE 0x8000000
+#define CFG_SYS_FSL_QBMAN_BASE 0x818000000
+#define CFG_SYS_FSL_QBMAN_SIZE 0x8000000
+#define CFG_SYS_FSL_QBMAN_SIZE_1 0x4000000
#ifdef CONFIG_ARCH_LS2080A
#define CFG_SYS_PCIE1_PHYS_SIZE 0x200000000
#define CFG_SYS_PCIE2_PHYS_SIZE 0x200000000
@@ -49,45 +49,45 @@
#define SYS_PCIE5_PHYS_SIZE 0x800000000
#define SYS_PCIE6_PHYS_SIZE 0x800000000
#endif
-#define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000
-#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000
-#define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000
-#define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000
+#define CFG_SYS_FSL_WRIOP1_BASE 0x4300000000
+#define CFG_SYS_FSL_WRIOP1_SIZE 0x100000000
+#define CFG_SYS_FSL_AIOP1_BASE 0x4b00000000
+#define CFG_SYS_FSL_AIOP1_SIZE 0x100000000
#if !defined(CONFIG_ARCH_LX2160A) || !defined(CONFIG_ARCH_LX2162)
-#define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000
+#define CFG_SYS_FSL_PEBUF_BASE 0x4c00000000
#else
-#define CONFIG_SYS_FSL_PEBUF_BASE 0x1c00000000
+#define CFG_SYS_FSL_PEBUF_BASE 0x1c00000000
#endif
-#define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000
+#define CFG_SYS_FSL_PEBUF_SIZE 0x400000000
#ifdef CONFIG_NXP_LSCH3_2
-#define CONFIG_SYS_FSL_DRAM_BASE2 0x2080000000
-#define CONFIG_SYS_FSL_DRAM_SIZE2 0x1F80000000
-#define CONFIG_SYS_FSL_DRAM_BASE3 0x6000000000
-#define CONFIG_SYS_FSL_DRAM_SIZE3 0x2000000000
+#define CFG_SYS_FSL_DRAM_BASE2 0x2080000000
+#define CFG_SYS_FSL_DRAM_SIZE2 0x1F80000000
+#define CFG_SYS_FSL_DRAM_BASE3 0x6000000000
+#define CFG_SYS_FSL_DRAM_SIZE3 0x2000000000
#else
-#define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000
-#define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000
+#define CFG_SYS_FSL_DRAM_BASE2 0x8080000000
+#define CFG_SYS_FSL_DRAM_SIZE2 0x7F80000000
#endif
#elif defined(CONFIG_FSL_LSCH2)
-#define CONFIG_SYS_FSL_CCSR_BASE 0x1000000
-#define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000
-#define CONFIG_SYS_FSL_DCSR_BASE 0x20000000
-#define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000
+#define CFG_SYS_FSL_CCSR_BASE 0x1000000
+#define CFG_SYS_FSL_CCSR_SIZE 0xf000000
+#define CFG_SYS_FSL_DCSR_BASE 0x20000000
+#define CFG_SYS_FSL_DCSR_SIZE 0x4000000
#define CFG_SYS_FSL_QSPI_BASE 0x40000000
-#define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000
-#define CONFIG_SYS_FSL_IFC_BASE 0x60000000
-#define CONFIG_SYS_FSL_IFC_SIZE 0x20000000
-#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
-#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
-#define CONFIG_SYS_FSL_QBMAN_BASE 0x500000000
-#define CONFIG_SYS_FSL_QBMAN_SIZE 0x10000000
-#define CONFIG_SYS_FSL_DRAM_BASE2 0x880000000
-#define CONFIG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */
+#define CFG_SYS_FSL_QSPI_SIZE 0x20000000
+#define CFG_SYS_FSL_IFC_BASE 0x60000000
+#define CFG_SYS_FSL_IFC_SIZE 0x20000000
+#define CFG_SYS_FSL_DRAM_BASE1 0x80000000
+#define CFG_SYS_FSL_DRAM_SIZE1 0x80000000
+#define CFG_SYS_FSL_QBMAN_BASE 0x500000000
+#define CFG_SYS_FSL_QBMAN_SIZE 0x10000000
+#define CFG_SYS_FSL_DRAM_BASE2 0x880000000
+#define CFG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */
#define CFG_SYS_PCIE1_PHYS_SIZE 0x800000000
#define CFG_SYS_PCIE2_PHYS_SIZE 0x800000000
#define CFG_SYS_PCIE3_PHYS_SIZE 0x800000000
-#define CONFIG_SYS_FSL_DRAM_BASE3 0x8800000000
-#define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */
+#define CFG_SYS_FSL_DRAM_BASE3 0x8800000000
+#define CFG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */
#endif
int fsl_qoriq_core_to_cluster(unsigned int core);
diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h
index 979d5470e7..43ccae10bd 100644
--- a/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h
@@ -360,7 +360,7 @@ check_member(rk3288_msch, devtodev, 0x003c);
#define PCTL_STAT_MSK 7
#define INIT_MEM 0
#define CONFIG 1
-#define CONFIG_REQ 2
+#define CFG_REQ 2
#define ACCESS 3
#define ACCESS_REQ 4
#define LOW_POWER 5
diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h b/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h
index 6f6c5c9954..0d29aefb64 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h
@@ -415,7 +415,7 @@ struct rk322x_base_params {
#define PCTL_STAT_MASK 7
#define INIT_MEM 0
#define CONFIG 1
-#define CONFIG_REQ 2
+#define CFG_REQ 2
#define ACCESS 3
#define ACCESS_REQ 4
#define LOW_POWER 5
diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h
index e3dcfdf370..f0da46d863 100644
--- a/arch/arm/include/asm/arch-sunxi/i2c.h
+++ b/arch/arm/include/asm/arch-sunxi/i2c.h
@@ -14,7 +14,7 @@
#define CFG_I2C_MVTWSI_BASE1 SUNXI_TWI1_BASE
#endif
#ifdef CONFIG_R_I2C_ENABLE
-#define CONFIG_I2C_MVTWSI_BASE2 SUNXI_R_TWI_BASE
+#define CFG_I2C_MVTWSI_BASE2 SUNXI_R_TWI_BASE
#endif
/* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */
diff --git a/arch/arm/lib/lib1funcs.S b/arch/arm/lib/lib1funcs.S
index 7ff4446dd6..de15d09e36 100644
--- a/arch/arm/lib/lib1funcs.S
+++ b/arch/arm/lib/lib1funcs.S
@@ -15,12 +15,11 @@
/*
* U-Boot compatibility bit, define empty UNWIND() macro as, since we
- * do not support stack unwinding and define CONFIG_AEABI to make all
- * of the functions available without diverging from Linux code.
+ * do not support stack unwinding to make all of the functions available
+ * without diverging from Linux code.
*/
#ifdef __UBOOT__
#define UNWIND(x...)
-#define CONFIG_AEABI
#endif
.macro ARM_DIV_BODY dividend, divisor, result, curbit
@@ -314,8 +313,6 @@ UNWIND(.fnend)
ENDPROC(__modsi3)
.popsection
-#ifdef CONFIG_AEABI
-
.pushsection .text.__aeabi_uidivmod, "ax"
ENTRY(__aeabi_uidivmod)
UNWIND(.fnstart)
@@ -348,8 +345,6 @@ UNWIND(.fnend)
ENDPROC(__aeabi_idivmod)
.popsection
-#endif
-
.pushsection .text.Ldiv0, "ax"
Ldiv0:
UNWIND(.fnstart)
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h
index 309039347c..24f3b4e9ba 100644
--- a/arch/arm/mach-at91/include/mach/at91rm9200.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200.h
@@ -126,6 +126,4 @@
#define ATMEL_PIO_PORTS 4 /* theese SoCs have 4 PIO */
#define ATMEL_PMC_UHP AT91RM9200_PMC_UHP
-#define CONFIG_SYS_ATMEL_CPU_NAME "AT91RM9200"
-
#endif
diff --git a/arch/arm/mach-omap2/fdt-common.c b/arch/arm/mach-omap2/fdt-common.c
index 5eb0447312..e90d577670 100644
--- a/arch/arm/mach-omap2/fdt-common.c
+++ b/arch/arm/mach-omap2/fdt-common.c
@@ -17,8 +17,8 @@
#ifndef TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ
#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ (0)
#endif
-#ifndef CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ
-#define CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ (0)
+#ifndef CFG_SECURE_RUNTIME_RESV_SRAM_SZ
+#define CFG_SECURE_RUNTIME_RESV_SRAM_SZ (0)
#endif
int ft_hs_disable_rng(void *fdt, struct bd_info *bd)
diff --git a/arch/arm/mach-omap2/omap5/fdt.c b/arch/arm/mach-omap2/omap5/fdt.c
index c4162420f3..a8c301c6c2 100644
--- a/arch/arm/mach-omap2/omap5/fdt.c
+++ b/arch/arm/mach-omap2/omap5/fdt.c
@@ -19,8 +19,8 @@
#ifndef TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ
#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ (0)
#endif
-#ifndef CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ
-#define CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ (0)
+#ifndef CFG_SECURE_RUNTIME_RESV_SRAM_SZ
+#define CFG_SECURE_RUNTIME_RESV_SRAM_SZ (0)
#endif
static u32 hs_irq_skip[] = {
@@ -92,7 +92,7 @@ static int ft_hs_fixup_crossbar(void *fdt, struct bd_info *bd)
}
#if ((TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ != 0) || \
- (CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ != 0))
+ (CFG_SECURE_RUNTIME_RESV_SRAM_SZ != 0))
static int ft_hs_fixup_sram(void *fdt, struct bd_info *bd)
{
const char *path;
@@ -116,7 +116,7 @@ static int ft_hs_fixup_sram(void *fdt, struct bd_info *bd)
temp[0] = cpu_to_fdt32(0);
/* reservation size */
temp[1] = cpu_to_fdt32(max(TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ,
- CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ));
+ CFG_SECURE_RUNTIME_RESV_SRAM_SZ));
fdt_delprop(fdt, offs, "reg");
ret = fdt_setprop(fdt, offs, "reg", temp, 2 * sizeof(u32));
if (ret < 0) {
diff --git a/arch/arm/mach-rmobile/include/mach/rcar-mstp.h b/arch/arm/mach-rmobile/include/mach/rcar-mstp.h
index f2f8ce9599..d241652641 100644
--- a/arch/arm/mach-rmobile/include/mach/rcar-mstp.h
+++ b/arch/arm/mach-rmobile/include/mach/rcar-mstp.h
@@ -22,78 +22,78 @@
#define mstp_setclrbits_le32(addr, set, clear) \
mstp_setclrbits(le32, addr, set, clear)
-#ifndef CONFIG_SMSTP0_ENA
-#define CONFIG_SMSTP0_ENA 0x00
+#ifndef CFG_SMSTP0_ENA
+#define CFG_SMSTP0_ENA 0x00
#endif
-#ifndef CONFIG_SMSTP1_ENA
-#define CONFIG_SMSTP1_ENA 0x00
+#ifndef CFG_SMSTP1_ENA
+#define CFG_SMSTP1_ENA 0x00
#endif
-#ifndef CONFIG_SMSTP2_ENA
-#define CONFIG_SMSTP2_ENA 0x00
+#ifndef CFG_SMSTP2_ENA
+#define CFG_SMSTP2_ENA 0x00
#endif
-#ifndef CONFIG_SMSTP3_ENA
-#define CONFIG_SMSTP3_ENA 0x00
+#ifndef CFG_SMSTP3_ENA
+#define CFG_SMSTP3_ENA 0x00
#endif
-#ifndef CONFIG_SMSTP4_ENA
-#define CONFIG_SMSTP4_ENA 0x00
+#ifndef CFG_SMSTP4_ENA
+#define CFG_SMSTP4_ENA 0x00
#endif
-#ifndef CONFIG_SMSTP5_ENA
-#define CONFIG_SMSTP5_ENA 0x00
+#ifndef CFG_SMSTP5_ENA
+#define CFG_SMSTP5_ENA 0x00
#endif
-#ifndef CONFIG_SMSTP6_ENA
-#define CONFIG_SMSTP6_ENA 0x00
+#ifndef CFG_SMSTP6_ENA
+#define CFG_SMSTP6_ENA 0x00
#endif
-#ifndef CONFIG_SMSTP7_ENA
-#define CONFIG_SMSTP7_ENA 0x00
+#ifndef CFG_SMSTP7_ENA
+#define CFG_SMSTP7_ENA 0x00
#endif
-#ifndef CONFIG_SMSTP8_ENA
-#define CONFIG_SMSTP8_ENA 0x00
+#ifndef CFG_SMSTP8_ENA
+#define CFG_SMSTP8_ENA 0x00
#endif
-#ifndef CONFIG_SMSTP9_ENA
-#define CONFIG_SMSTP9_ENA 0x00
+#ifndef CFG_SMSTP9_ENA
+#define CFG_SMSTP9_ENA 0x00
#endif
-#ifndef CONFIG_SMSTP10_ENA
-#define CONFIG_SMSTP10_ENA 0x00
+#ifndef CFG_SMSTP10_ENA
+#define CFG_SMSTP10_ENA 0x00
#endif
-#ifndef CONFIG_SMSTP11_ENA
-#define CONFIG_SMSTP11_ENA 0x00
+#ifndef CFG_SMSTP11_ENA
+#define CFG_SMSTP11_ENA 0x00
#endif
-#ifndef CONFIG_RMSTP0_ENA
-#define CONFIG_RMSTP0_ENA 0x00
+#ifndef CFG_RMSTP0_ENA
+#define CFG_RMSTP0_ENA 0x00
#endif
-#ifndef CONFIG_RMSTP1_ENA
-#define CONFIG_RMSTP1_ENA 0x00
+#ifndef CFG_RMSTP1_ENA
+#define CFG_RMSTP1_ENA 0x00
#endif
-#ifndef CONFIG_RMSTP2_ENA
-#define CONFIG_RMSTP2_ENA 0x00
+#ifndef CFG_RMSTP2_ENA
+#define CFG_RMSTP2_ENA 0x00
#endif
-#ifndef CONFIG_RMSTP3_ENA
-#define CONFIG_RMSTP3_ENA 0x00
+#ifndef CFG_RMSTP3_ENA
+#define CFG_RMSTP3_ENA 0x00
#endif
-#ifndef CONFIG_RMSTP4_ENA
-#define CONFIG_RMSTP4_ENA 0x00
+#ifndef CFG_RMSTP4_ENA
+#define CFG_RMSTP4_ENA 0x00
#endif
-#ifndef CONFIG_RMSTP5_ENA
-#define CONFIG_RMSTP5_ENA 0x00
+#ifndef CFG_RMSTP5_ENA
+#define CFG_RMSTP5_ENA 0x00
#endif
-#ifndef CONFIG_RMSTP6_ENA
-#define CONFIG_RMSTP6_ENA 0x00
+#ifndef CFG_RMSTP6_ENA
+#define CFG_RMSTP6_ENA 0x00
#endif
-#ifndef CONFIG_RMSTP7_ENA
-#define CONFIG_RMSTP7_ENA 0x00
+#ifndef CFG_RMSTP7_ENA
+#define CFG_RMSTP7_ENA 0x00
#endif
-#ifndef CONFIG_RMSTP8_ENA
-#define CONFIG_RMSTP8_ENA 0x00
+#ifndef CFG_RMSTP8_ENA
+#define CFG_RMSTP8_ENA 0x00
#endif
-#ifndef CONFIG_RMSTP9_ENA
-#define CONFIG_RMSTP9_ENA 0x00
+#ifndef CFG_RMSTP9_ENA
+#define CFG_RMSTP9_ENA 0x00
#endif
-#ifndef CONFIG_RMSTP10_ENA
-#define CONFIG_RMSTP10_ENA 0x00
+#ifndef CFG_RMSTP10_ENA
+#define CFG_RMSTP10_ENA 0x00
#endif
-#ifndef CONFIG_RMSTP11_ENA
-#define CONFIG_RMSTP11_ENA 0x00
+#ifndef CFG_RMSTP11_ENA
+#define CFG_RMSTP11_ENA 0x00
#endif
struct mstp_ctl {
diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
index 6ae254e99a..fcae65b2e5 100644
--- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
+++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
@@ -198,7 +198,7 @@ enum {
/* PCTL_STAT */
INIT_MEM = 0,
CONFIG,
- CONFIG_REQ,
+ CFG_REQ,
ACCESS,
ACCESS_REQ,
LOW_POWER,
diff --git a/arch/arm/mach-tegra/tegra20/warmboot_avp.c b/arch/arm/mach-tegra/tegra20/warmboot_avp.c
index be801d108e..94ce762e01 100644
--- a/arch/arm/mach-tegra/tegra20/warmboot_avp.c
+++ b/arch/arm/mach-tegra/tegra20/warmboot_avp.c
@@ -34,7 +34,7 @@ void wb_start(void)
u32 reg;
/* enable JTAG & TBE */
- writel(CONFIG_CTL_TBE | CONFIG_CTL_JTAG, &apb_misc->cfg_ctl);
+ writel(CFG_CTL_TBE | CFG_CTL_JTAG, &apb_misc->cfg_ctl);
/* Are we running where we're supposed to be? */
asm volatile (
diff --git a/arch/arm/mach-tegra/tegra20/warmboot_avp.h b/arch/arm/mach-tegra/tegra20/warmboot_avp.h
index 19a476b895..f300fe6625 100644
--- a/arch/arm/mach-tegra/tegra20/warmboot_avp.h
+++ b/arch/arm/mach-tegra/tegra20/warmboot_avp.h
@@ -19,8 +19,8 @@
#define USEC_CFG_DIVISOR_MASK 0xffff
-#define CONFIG_CTL_TBE (1 << 7)
-#define CONFIG_CTL_JTAG (1 << 6)
+#define CFG_CTL_TBE (1 << 7)
+#define CFG_CTL_JTAG (1 << 6)
#define CPU_RST (1 << 0)
#define CLK_ENB_CPU (1 << 0)
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-31 06:28:12 +0000