diff options
| author | Tom Rini <trini@konsulko.com> | 2023-07-21 09:57:59 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-07-21 09:57:59 -0400 |
| commit | e7f7e2e1e22fd719a8810ba488a9451635b13d1b (patch) | |
| tree | 0dda2ed98b772b44ae61b041d402f9618cd18670 /drivers/fpga/versalpl.c | |
| parent | e896279ac39ebb97f23e6132bf7668a61e1cd86b (diff) | |
| parent | a1190b4d6a9bf3a45038e3eba4a11de4be2b1cca (diff) | |
Merge tag 'xilinx-for-v2023.10-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2023.10-rc1 v2
axi_emac:
- Change return value if RX packet is not ready
cadence_qspi:
- Enable flash reset for Versal NET
dt:
- Various DT syncups with Linux kernel
- SOM - reserved pmufw memory location
fpga:
- Add load event
mtd:
- Add missing dependency for FLASH_CFI_MTD
spi/nand:
- Minor cleanup in Xilinx drivers
versal-net:
- Prioritize boot device in boot_targets
- Wire mini ospi/qspi/emmc configurations
watchdog:
- Use new versal-wwdt property
xilinx:
- fix sparse warnings in various places ps7_init*
- add missing headers
- consolidate code around zynqmp_mmio_read/write
- switch to amd.com email
zynqmp_clk:
- Add handling for gem rx/tsu clocks
zynq_gem:
- Configure mdio clock at run time
zynq:
- Enable fdt overlay support
zynq_sdhci:
- Call dll reset only for ZynqMP SOCs
Diffstat (limited to 'drivers/fpga/versalpl.c')
| -rw-r--r-- | drivers/fpga/versalpl.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/fpga/versalpl.c b/drivers/fpga/versalpl.c index d3876a8f54..be58db5427 100644 --- a/drivers/fpga/versalpl.c +++ b/drivers/fpga/versalpl.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * (C) Copyright 2019, Xilinx, Inc, - * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> + * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>> */ #include <common.h> |