Merge tag 'xilinx-for-v2023.10-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2023.10-rc1 v2

axi_emac:
- Change return value if RX packet is not ready

cadence_qspi:
- Enable flash reset for Versal NET

dt:
- Various DT syncups with Linux kernel
- SOM - reserved pmufw memory location

fpga:
- Add load event

mtd:
- Add missing dependency for FLASH_CFI_MTD

spi/nand:
- Minor cleanup in Xilinx drivers

versal-net:
- Prioritize boot device in boot_targets
- Wire mini ospi/qspi/emmc configurations

watchdog:
- Use new versal-wwdt property

xilinx:
- fix sparse warnings in various places ps7_init*
- add missing headers
- consolidate code around zynqmp_mmio_read/write
- switch to amd.com email

zynqmp_clk:
- Add handling for gem rx/tsu clocks

zynq_gem:
- Configure mdio clock at run time

zynq:
- Enable fdt overlay support

zynq_sdhci:
- Call dll reset only for ZynqMP SOCs

3 files changed, 23 insertions, 3 deletions

diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c
index 7f6b6bc73a..81e6d8ffc0 100644
--- a/drivers/fpga/fpga.c
+++ b/drivers/fpga/fpga.c
@@ -244,6 +244,21 @@ int fpga_loads(int devnum, const void *buf, size_t size,
 }
 #endif
 
+static int fpga_load_event_notify(const void *buf, size_t bsize, int result)
+{
+	if (CONFIG_IS_ENABLED(EVENT)) {
+		struct event_fpga_load load = {
+			.buf = buf,
+			.bsize = bsize,
+			.result = result
+		};
+
+		return event_notify(EVT_FPGA_LOAD, &load, sizeof(load));
+	}
+
+	return 0;
+}
+
 /*
  * Generic multiplexing code
  */
@@ -251,6 +266,7 @@ int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype,
 	      int flags)
 {
 	int ret_val = FPGA_FAIL;           /* assume failure */
+	int ret_notify;
 	const fpga_desc *desc = fpga_validate(devnum, buf, bsize,
 					      (char *)__func__);
 
@@ -284,6 +300,10 @@ int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype,
 		}
 	}
 
+	ret_notify = fpga_load_event_notify(buf, bsize, ret_val);
+	if (ret_notify)
+		return ret_notify;
+
 	return ret_val;
 }
 
diff --git a/drivers/fpga/versalpl.c b/drivers/fpga/versalpl.c
index d3876a8f54..be58db5427 100644
--- a/drivers/fpga/versalpl.c
+++ b/drivers/fpga/versalpl.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * (C) Copyright 2019, Xilinx, Inc,
- * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
+ * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
  */
 
 #include <common.h>
diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c
index 7b5128fe27..b1f201fb18 100644
--- a/drivers/fpga/zynqmppl.c
+++ b/drivers/fpga/zynqmppl.c
@@ -1,8 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
  * (C) Copyright 2015 - 2016, Xilinx, Inc,
- * Michal Simek <michal.simek@xilinx.com>
- * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ * Michal Simek <michal.simek@amd.com>
+ * Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
  */
 
 #include <console.h>