diff options
| author | Jacky Bai <ping.bai@nxp.com> | 2021-10-29 09:46:33 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2022-02-05 13:38:39 +0100 |
| commit | b80ec768a3b27e245dbea3e4fac0a0d154e4b729 (patch) | |
| tree | b5217ed413797208b523294cbb41cc6f26c0bff4 /drivers/ddr/imx/imx8ulp/Kconfig | |
| parent | 6293b73d0ffb90e67cf959360ca72e737290bcd7 (diff) | |
imx8ulp:ddr: saving the dram config timing data into sram
On i.MX8ULP, The dram config timing need to be saved into sram for
ddr retention when APD enter PD mode, so add this support on i.MX8ULP.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'drivers/ddr/imx/imx8ulp/Kconfig')
| -rw-r--r-- | drivers/ddr/imx/imx8ulp/Kconfig | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/ddr/imx/imx8ulp/Kconfig b/drivers/ddr/imx/imx8ulp/Kconfig index e56062a1d0..42848863aa 100644 --- a/drivers/ddr/imx/imx8ulp/Kconfig +++ b/drivers/ddr/imx/imx8ulp/Kconfig @@ -8,4 +8,11 @@ config IMX8ULP_DRAM_PHY_PLL_BYPASS bool "Enable the DDR PHY PLL bypass mode, so PHY clock is from DDR_CLK " depends on IMX8ULP_DRAM +config SAVED_DRAM_TIMING_BASE + hex "Define the base address for saved dram timing" + help + The DRAM config timing data need to be saved into sram + for low power use. + default 0x2006c000 + endmenu |