diff options
| author | Conor Dooley <conor.dooley@microchip.com> | 2022-10-25 08:58:47 +0100 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2022-11-15 15:37:17 +0800 |
| commit | 88b697fb37432b95bd87525e718726607bdb2123 (patch) | |
| tree | b406040e16430ac1a14adc107b4f518847328d28 /drivers/clk/microchip/mpfs_clk.c | |
| parent | 32cfdd51630506393ca078aa36fa70248d549109 (diff) | |
clk: microchip: mpfs: fix periph clk parentage
Not all "periph" clocks are children of the AHB clock, some have the AXI
clock as their parent & the mtimer clock is derived from the external
reference clock directly. Stop assuming the AHB clock to be the parent
of all "periph" clocks and define their correct parents instead.
Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
Diffstat (limited to 'drivers/clk/microchip/mpfs_clk.c')
| -rw-r--r-- | drivers/clk/microchip/mpfs_clk.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/drivers/clk/microchip/mpfs_clk.c b/drivers/clk/microchip/mpfs_clk.c index f16f716f00..08f8bfcecb 100644 --- a/drivers/clk/microchip/mpfs_clk.c +++ b/drivers/clk/microchip/mpfs_clk.c @@ -19,7 +19,6 @@ static int mpfs_clk_probe(struct udevice *dev) { struct clk *parent_clk = dev_get_priv(dev); - struct clk clk_ahb = { .id = CLK_AHB }; struct clk clk_msspll = { .id = CLK_MSSPLL }; void __iomem *base; void __iomem *msspll_base; @@ -56,8 +55,7 @@ static int mpfs_clk_probe(struct udevice *dev) if (ret) return ret; - clk_request(dev, &clk_ahb); - ret = mpfs_clk_register_periphs(base, &clk_ahb); + ret = mpfs_clk_register_periphs(base, dev); return ret; } |