clk: microchip: mpfs: fix reference clock handling

The original devicetrees for PolarFire SoC messed up & defined the
msspll's output as a fixed-frequency, 600 MHz clock & used that as the
input for the clock controller node. The msspll is not a fixed
frequency clock and later devicetrees handled this properly. Check the
devicetree & if it is one of the fixed ones, register the msspll.
Otherwise, skip registering it & pass the reference clock directly to
the cfg clock registration function so that existing devicetrees are
not broken by this change.

As the MSS PLL is not a "cfg" or a "periph" clock, add a new driver for
it, based on the one in Linux.

Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
Tested-by: Padmarao Begari <padmarao.begari@microchip.com>

1 files changed, 22 insertions, 1 deletions

diff --git a/drivers/clk/microchip/mpfs_clk.c b/drivers/clk/microchip/mpfs_clk.c
index 7ba1218b56..f16f716f00 100644
--- a/drivers/clk/microchip/mpfs_clk.c
+++ b/drivers/clk/microchip/mpfs_clk.c
@@ -20,10 +20,12 @@ static int mpfs_clk_probe(struct udevice *dev)
 {
 	struct clk *parent_clk = dev_get_priv(dev);
 	struct clk clk_ahb = { .id = CLK_AHB };
+	struct clk clk_msspll = { .id = CLK_MSSPLL };
 	void __iomem *base;
+	void __iomem *msspll_base;
 	int ret;
 
-	base = dev_read_addr_ptr(dev);
+	base = dev_read_addr_index_ptr(dev, 0);
 	if (!base)
 		return -EINVAL;
 
@@ -31,6 +33,25 @@ static int mpfs_clk_probe(struct udevice *dev)
 	if (ret)
 		return ret;
 
+	/*
+	 * The original devicetrees for mpfs messed up & defined the msspll's
+	 * output as a fixed-frequency, 600 MHz clock & used that as the input
+	 * for the clock controller node. The msspll is however not a fixed
+	 * frequency clock and later devicetrees handled this properly. Check
+	 * the devicetree & if it is one of the fixed ones, register the msspll.
+	 * Otherwise, skip registering it & pass the reference clock directly
+	 * to the cfg clock registration function.
+	 */
+	msspll_base = dev_read_addr_index_ptr(dev, 1);
+	if (msspll_base) {
+		ret = mpfs_clk_register_msspll(msspll_base, parent_clk);
+		if (ret)
+			return ret;
+
+		clk_request(dev, &clk_msspll);
+		parent_clk = &clk_msspll;
+	}
+
 	ret = mpfs_clk_register_cfgs(base, parent_clk);
 	if (ret)
 		return ret;