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| author | Tom Rini <trini@konsulko.com> | 2020-04-09 19:23:48 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-04-09 19:23:48 -0400 |
| commit | a7ae587f9325aa072617dae109d474f623b38a3e (patch) | |
| tree | df5fa02d7a67a07c6e833f9175998045391ac813 /arch/mips/lib/cache.c | |
| parent | 31232de07ef2bd97ff67625976eecd97eeb1bd3d (diff) | |
| parent | fb9acad30562177287d8cffec19e5dfa6f072de7 (diff) | |
Merge tag 'mips-fixes-for-2020.04' of git://git.denx.de/u-boot-mips
- doc: fix code examples in qemu-mips.rst
- mips: vcoreiii: fix memtest and cache coherency issues
- cmd/go: fix cache coherency issues on MIPS
Diffstat (limited to 'arch/mips/lib/cache.c')
| -rw-r--r-- | arch/mips/lib/cache.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c index 502956d050..1a8c87d094 100644 --- a/arch/mips/lib/cache.c +++ b/arch/mips/lib/cache.c @@ -141,7 +141,7 @@ ops_done: instruction_hazard_barrier(); } -void flush_dcache_range(ulong start_addr, ulong stop) +void __weak flush_dcache_range(ulong start_addr, ulong stop) { unsigned long lsize = dcache_line_size(); unsigned long slsize = scache_line_size(); |