Merge tag 'mips-fixes-for-2020.04' of git://git.denx.de/u-boot-mips

- doc: fix code examples in qemu-mips.rst
- mips: vcoreiii: fix memtest and cache coherency issues
- cmd/go: fix cache coherency issues on MIPS

3 files changed, 25 insertions, 1 deletions

diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index 589bc651f9..24a72d9c97 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -11,5 +11,6 @@ obj-y	+= stack.o
 obj-y	+= traps.o
 
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
+obj-$(CONFIG_CMD_GO) += boot.o
 
 lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o
diff --git a/arch/mips/lib/boot.c b/arch/mips/lib/boot.c
new file mode 100644
index 0000000000..db862f6379
--- /dev/null
+++ b/arch/mips/lib/boot.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <cpu_func.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned long do_go_exec(ulong (*entry)(int, char * const []),
+			 int argc, char * const argv[])
+{
+	/*
+	 * Flush cache before jumping to application. Let's flush the
+	 * whole SDRAM area, since we don't know the size of the image
+	 * that was loaded.
+	 */
+	flush_cache(gd->bd->bi_memstart, gd->ram_top - gd->bd->bi_memstart);
+
+	return entry(argc, argv);
+}
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index 502956d050..1a8c87d094 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -141,7 +141,7 @@ ops_done:
 	instruction_hazard_barrier();
 }
 
-void flush_dcache_range(ulong start_addr, ulong stop)
+void __weak flush_dcache_range(ulong start_addr, ulong stop)
 {
 	unsigned long lsize = dcache_line_size();
 	unsigned long slsize = scache_line_size();