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authorChee Hong Ang <chee.hong.ang@intel.com>2020-08-06 12:15:33 +0800
committerLey Foon Tan <ley.foon.tan@intel.com>2020-10-09 17:53:12 +0800
commit2473e13bb8e81cf90e89863125e85900193b01b7 (patch)
tree58bb0dfdcc53924cee9f511aa6343c4c720fcaa7 /arch/arm/mach-socfpga/spl_agilex.c
parentb3e2d9fccbe7390a859f7f46001c6312cc35455c (diff)
arm: socfpga: Use DM watchdog timer
All SoCFPGA platforms (except Cyclone V) are now switching to CONFIG_WDT (driver model for watchdog timer drivers) from CONFIG_HW_WATCHDOG. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Diffstat (limited to 'arch/arm/mach-socfpga/spl_agilex.c')
-rw-r--r--arch/arm/mach-socfpga/spl_agilex.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c
index 0121ff431f..78b5d7c8d9 100644
--- a/arch/arm/mach-socfpga/spl_agilex.c
+++ b/arch/arm/mach-socfpga/spl_agilex.c
@@ -51,11 +51,11 @@ void board_init_f(ulong dummy)
socfpga_get_managers_addr();
-#ifdef CONFIG_HW_WATCHDOG
/* Ensure watchdog is paused when debugging is happening */
writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
+#ifdef CONFIG_HW_WATCHDOG
/* Enable watchdog before initializing the HW */
socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);