diff options
author | Chee Hong Ang <chee.hong.ang@intel.com> | 2020-08-05 21:15:57 +0800 |
---|---|---|
committer | Ley Foon Tan <ley.foon.tan@intel.com> | 2020-10-09 17:53:11 +0800 |
commit | b3e2d9fccbe7390a859f7f46001c6312cc35455c (patch) | |
tree | 54fb5133a8eb0b7a9fb7d1c4377ec2c825c70764 /arch/arm/mach-socfpga/spl_agilex.c | |
parent | d7a1ff40d6006c818c9e74d3e13bec008638349f (diff) |
arm: socfpga: soc64: Show reset state in SPL
Print reset state (warm/cold) together with the
source (watchdog/MPU) which has triggered the warm
reset on S10 & Agilex.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Diffstat (limited to 'arch/arm/mach-socfpga/spl_agilex.c')
-rw-r--r-- | arch/arm/mach-socfpga/spl_agilex.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c index bd971ecbd1..0121ff431f 100644 --- a/arch/arm/mach-socfpga/spl_agilex.c +++ b/arch/arm/mach-socfpga/spl_agilex.c @@ -76,6 +76,7 @@ void board_init_f(ulong dummy) } preloader_console_init(); + print_reset_info(); cm_print_clock_quick_summary(); firewall_setup(); |