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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2022 NXP
*
* Peng Fan <peng.fan@nxp.com>
*/
#include <common.h>
#include <cpu_func.h>
#include <init.h>
#include <log.h>
#include <asm/arch/imx-regs.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/syscounter.h>
#include <asm/armv8/mmu.h>
#include <dm/uclass.h>
#include <env.h>
#include <env_internal.h>
#include <errno.h>
#include <fdt_support.h>
#include <linux/bitops.h>
#include <asm/setup.h>
#include <asm/bootm.h>
#include <asm/arch-imx/cpu.h>
DECLARE_GLOBAL_DATA_PTR;
u32 get_cpu_rev(void)
{
return (MXC_CPU_IMX93 << 12) | CHIP_REV_1_0;
}
static struct mm_region imx93_mem_map[] = {
{
/* ROM */
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0x100000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE
}, {
/* OCRAM */
.virt = 0x20480000UL,
.phys = 0x20480000UL,
.size = 0xA0000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE
}, {
/* AIPS */
.virt = 0x40000000UL,
.phys = 0x40000000UL,
.size = 0x40000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* Flexible Serial Peripheral Interface */
.virt = 0x28000000UL,
.phys = 0x28000000UL,
.size = 0x30000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* DRAM1 */
.virt = 0x80000000UL,
.phys = 0x80000000UL,
.size = PHYS_SDRAM_SIZE,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE
}, {
/* empty entrie to split table entry 5 if needed when TEEs are used */
0,
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = imx93_mem_map;
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_SIZE;
return 0;
}
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
mac[0] = 0x1;
mac[1] = 0x2;
mac[2] = 0x3;
mac[3] = 0x4;
mac[4] = 0x5;
mac[5] = 0x6;
}
int print_cpuinfo(void)
{
u32 cpurev;
cpurev = get_cpu_rev();
printf("CPU: i.MX93 rev%d.%d\n", (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0);
return 0;
}
int arch_misc_init(void)
{
return 0;
}
int ft_system_setup(void *blob, struct bd_info *bd)
{
return 0;
}
int arch_cpu_init(void)
{
if (IS_ENABLED(CONFIG_SPL_BUILD))
clock_init();
return 0;
}
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