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* reset: reset-hisilicon: also handle #reset-cells = <2>Yang Xiwen2024-01-241-2/+13
| | | | | | | It's also valid to have #reset-cells = <2> while the third arg defaults to ASSERT_SET. Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
* reset: npcm: Add support for Nuvoton NPCM BMC familyJim Liu2024-01-163-0/+153
| | | | | | | | | | Add reset controller driver for Nuvoton BMCs. The npcm reset driver not only supports reset each module reset but setting initial value of reset Control Registers. And The driver support each module reset. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
* clk/qcom: handle resets and clocks in one deviceKonrad Dybcio2024-01-163-203/+0
| | | | | | | | | | | | | | | | | | | Qualcomm's clock controller blocks actually do much more than it says on the tin.. They provide clocks, resets and power domains. Currently, U-Boot requires one to spawn 2 separate devices for controlling clocks and resets, both spanning the same register space. Refactor the code to make it work with just a single DT node, making it compatible with upstream Linux bindings and dropping the dedicated reset driver in favour of including it in the clock driver. Heavily inspired by Renesas code for a similar hw block. [caleb: moved drivers to clk/qcom, added reset driver and adjusted bind logic. Imported qcom,gcc-ipq4019.h from Linux] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
* tree-wide: Replace http:// link with https:// link for ti.comNishanth Menon2023-11-102-2/+2
| | | | | | Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
* Merge tag 'u-boot-amlogic-20231015' of ↵Tom Rini2023-10-161-6/+36
|\ | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-amlogic - add Amlogic A1 clock driver - add Amlogic A1 reset support - add USB Device support for Amlogic A1 - enable RNG on Amlogic A1 & Amlogic S4 - move Amlogic Secure Monitor to standalone driver
| * reset: add support for Amlogic A1 familyAlexey Romanov2023-10-121-6/+36
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds reset support for the Amlogic A1 family. We add the structure meson_reset_drvdata, which in the future will allow this driver to be used for other families by declaring only the correct parameters reg_count and level_offset. Signed-off-by: Alexey Romanov <avromanov@salutedevices.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231005085434.74755-3-avromanov@salutedevices.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* | scmi: refactor the code to hide a channel from devicesAKASHI Takahiro2023-10-131-16/+3
|/ | | | | | | | | | | | | The commit 85dc58289238 ("firmware: scmi: prepare uclass to pass channel reference") added an explicit parameter, channel, but it seems to make the code complex. Hiding this parameter will allow for adding a generic (protocol-agnostic) helper function, i.e. for PROTOCOL_VERSION, in a later patch. Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
* common: Drop linux/printk.h from common headerSimon Glass2023-09-241-0/+1
| | | | | | | | | This old patch was marked as deferred. Bring it back to life, to continue towards the removal of common.h Move this out of the common header and include it only where needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* reset: mediatek: check malloc return valaue before useWeijie Gao2023-08-031-0/+3
| | | | | | | | This patch add missing return value check for allocating the driver's private data. -ENOMEM will be returned if malloc() fails. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
* core: read: fix dev_read_addr_size()John Keeping2023-07-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | The behaviour of dev_read_addr_size() is surprising as it does not handle #address-cells and #size-cells but instead hardcodes the values based on sizeof(fdt_addr_t). This is different from dev_read_addr_size_index() and dev_read_addr_size_name() both of which do read the cell sizes from the device tree. Since dev_read_addr_size() is only used by a single driver and this driver is broken when CONFIG_FDT_64BIT does not match the address size in the device tree, fix the function to behave like all of the other similarly named functions. Drop the property name argument as the only caller passes "reg" and this is the expected property name matching the other similarly named functions. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # chromebook_jerry Tested-by: Simon Glass <sjg@chromium.org> # chromebook_bob
* reset: rockchip: implement rk3588 lookup tableEugen Hristev2023-05-173-12/+890
| | | | | | | | | | | | | | | | | | | | The current DT bindings for the rk3588 clock use a different ID than the one that is supposed to be written to the hardware registers. Thus, we cannot use directly the id provided in the phandle, but rather use a lookup table to correctly setup the hardware. This approach has been implemented already in Linux, by commit : f1c506d152ff ("clk: rockchip: add clock controller for the RK3588") Hence, implement a similar approach using the lookup table, and adapt the existing reset driver to work with SoCs using lookup table. The file rst-rk3588.c has been copied as much as possible from Linux. Adapt the clk rk3588 driver as well to bind the reset driver with the lookup table. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
* reset: reset-rockchip: fix trivial line spacing alignmentEugen Hristev2023-05-091-2/+2
| | | | | | | | Fix line spacing aligment in bind function Fixes: 760188c1aa5b ("rockchip: reset: support a (common) rockchip reset drivers") Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* reset: starfive: jh7110: Add reset driver for StarFive JH7110 SoCYanhong Wang2023-04-203-0/+175
| | | | | | | | | | | | Add a DM reset driver for StarFive JH7110 SoC. Note that the register base address of reset controller is the same with the clock controller. Therefore, there is no device tree node alone for reset driver.It binds device node in the clock driver Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
* reset: uniphier: Add USB glue reset supportKunihiko Hayashi2023-02-221-1/+77
| | | | | | | | | | | | | | | | | | | | | | | Add reset control support in USB glue logic. This needs to control the external clocks and resets for the logic before accessing the glue logic. The USB dm tree when using dwc3-generic is the following: USB glue +-- controller (need controller-reset) +-- controller-reset (need syscon-reset) +-- phy The controller needs to deassert "controller-reset" in USB glue before the controller registers are accessed. The glue needs to deassert "syscon-reset" before the glue registers are accessed. The glue itself doesn't have "syscon-reset", so the controller-reset controls "syscon-reset" instead. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Marek Vasut <marex@denx.de>
* reset: Allow reset_get_by_name() with NULL nameSamuel Holland2023-02-121-5/+7
| | | | | | | | | This allows devm_reset_control_get(dev, NULL) to work and get the first reset control, which is common in code ported from Linux. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20230122000252.53642-2-samuel@sholland.org
* reset: at91: Add reset driver for basic assert/deassert operationsSergiu Moga2023-01-053-0/+150
| | | | | | | | | | | | | | | Add support for at91 reset controller's basic assert/deassert operations. Since this driver conflicts with the SYSRESET driver because they both bind to the same RSTC node, implement a custom bind hook that would manually bind the sysreset driver, if enabled, to the same RSTC DT node. Furthermore, delete the no longer needed compatibles from the SYSRESET driver and rename it to make sure than any possible conflicts are avoided. Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com> Tested-by: Mihai Sain <mihai.sain@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
* reset: zynqmp: Enable reset driver for Versal NETJay Buddhabhatti2022-09-261-0/+1
| | | | | | | | Enable zynqmp reset driver for Versal NET. Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/c8c26618f87d8451c6ffa9487809a24718bff6a7.1663589964.git.michal.simek@amd.com
* reset: qcom: Add support for QCS404 SoC reset tableSumit Garg2022-08-261-0/+30
| | | | Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
* reset: Convert ipq4019 driver to a generic Qcom driverSumit Garg2022-08-263-27/+30
| | | | | | | | | Since the base functionality remains the same for a reset driver on Qcom SoCs, so leverage that to convert ipq4019 specific reset driver to a generic Qcom reset driver. With that one just need to provide SoC specific reset table. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
* reset: zynqmp: Add reset driver support for versalT Karthik Reddy2022-07-262-6/+10
| | | | | | | | | | | | | Add support for versal platform by adding "xlnx,versal-reset" compatible string in zynqmp-reset driver. Reset numbering schema for versal is not same as zynqmp, so nr_reset and reset_id are set to zero. In case of assert/dessert, required device reset id is sent from respective driver through struct reset_ctl. Signed-off-by: T Karthik Reddy <t.karthik.reddy@amd.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Link: https://lore.kernel.org/r/20220720095959.29610-2-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek <michal.simek@amd.com>
* reset: sunxi: Reuse the platform data from the clock driverSamuel Holland2022-07-181-40/+3
| | | | | | | | | | The clock and reset drivers use the exact same platform data. Simplify them by sharing the object. This is safe because the parent device (the clock device) always gets its driver model callbacks run first. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* reset: sunxi: Convert driver private data to platform dataSamuel Holland2022-07-181-18/+18
| | | | | | | | | The reason here is the same as the reason for changing the clock driver: platform data can be provided when binding the driver. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* reset: sunxi: Get the reset count from the CCU descriptorSamuel Holland2022-07-181-4/+2
| | | | | | | | | This allows all of the clock drivers to use a common bind function. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> [Andre: add F1C100s support] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* reset/aspeed: Implement status callbackJoel Stanley2022-07-062-0/+36
| | | | | | | | The I2C driver shares a reset line between buses, so allow it to test the state of the reset line before resetting it. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
* reset: scmi: support SCMI multi-channelEtienne Carriere2022-06-231-3/+22
| | | | | | | | | Update SCMI reset controller driver to get its assigned SCMI channel during initialization. This change allows SCMI reset domain protocol to use a dedicated channel when defined in the DT. The reference is saved in SCMI reset controller driver private data. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
* firmware: scmi: prepare scmi uclass API to multi-channelEtienne Carriere2022-06-231-2/+2
| | | | | | | | | | | | | | | | | | Changes SCMI driver API function devm_scmi_process_msg() to add an SCMI channel reference argument for when SCMI agent supports SCMI protocol specific channels. First argument of devm_scmi_process_msg() is also change to point to the caller SCMI protocol device rather than its parent device (the SCMI agent device). The argument is a pointer to opaque struct scmi_channel known from the SCMI transport drivers. It is currently unused and caller a pass NULL value. A later change will enable such support once SCMI protocol drivers have means to get the channel reference during initialization. Cc: Lukasz Majewski <lukma@denx.de> Cc: Sean Anderson <seanga2@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
* reset: Return 0 if ops unimplemented and remove empty functionsMarek Vasut2022-05-0525-302/+6
| | | | | | | | | | In case the ops is not implemented, return 0 in the core right away. This is better than having multiple copies of functions which just return 0 in each reset driver. Drop all those empty functions. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
* scmi: change parameter dev in devm_scmi_process_msgEtienne Carriere2022-03-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | | Changes devm_scmi_process_msg() first argument from target parent device to current SCMI device and lookup the SCMI agent device among SCMI device parents for find the SCMI agent operator needed for communication with the firmware. This change is needed in order to support CCF in clk_scmi driver unless what CCF will fail to find the right udevice related to exposed SCMI clocks. This patch allows to simplify the caller sequence, using SCMI device reference as parameter instead of knowing SCMI uclass topology. This change also adds some protection in case devm_scmi_process_msg() API function is called for an invalid device type. Cc: Lukasz Majewski <lukma@denx.de> Cc: Sean Anderson <seanga2@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
* reset: dra7: Add a reset driverKeerthy2022-02-083-0/+104
| | | | | | | | | Add a reset driver to bring IPs out of reset. Signed-off-by: Keerthy <j-keerthy@ti.com> [Amjad: reset_ops structure member "free" has been renamed to "rfree", use the latter instead] Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
* treewide: invaild -> invalidSean Anderson2022-01-131-1/+1
| | | | | | | | | Somewhere along the way, someone misspelt "invalid" and it got copied everywhere. Fix it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Alexander Dahl <ada@thorsis.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* reset: scmi: define LOG_CATEGORYPatrick Delaunay2021-11-231-0/+3
| | | | | | | Define LOG_CATEGORY to allow filtering with log command. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
* clk: sunxi: Move header out of arch directorySamuel Holland2021-10-111-1/+1
| | | | | | | | | | | The CCU header is only used by the DM drivers, not any platform code. Its current location adds an artificial dependency on CONFIG_ARM and ARCH_SUNXI, which will be problematic when adding the CCU driver for a RISC-V sunxi platform. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* WS cleanup: remove trailing white spaceWolfgang Denk2021-09-301-5/+5
| | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* WS cleanup: remove trailing empty linesWolfgang Denk2021-09-301-1/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* reset: zynqmp: Add reset controller for ZynqMP SoCMichal Simek2021-08-063-0/+110
| | | | | | | | | | Add firmware based reset controller for Xilinx ZynqMP SoC to let other drivers to call reset functions. Driver is only tested on Xilinx ZynqMP but support for Xilinx Versal can be simply added. That's why reset_id and nr_reset are assigned in probe folder. Driver is inpired by driver from Linux kernel. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* reset: ast2600: Fix missing reference operatorChia-Wei Wang2021-07-241-4/+4
| | | | | | | Fix missing reference operator '&' to correctly get HW register addresses for writel(). Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
* reset: Avoid a warning in devm_reset_bulk_get_by_node()Simon Glass2021-07-151-0/+2
| | | | | | | | | | | The devres_alloc() function is intended to avoid the need for freeing memory, although in practice it may not be enabled, thus leading to a true leak. Nevertheless this is intended. Add a comment to explain this. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Coverity (CID: 312952)
* reset: uniphier: Add PCIe reset entryKunihiko Hayashi2021-07-141-0/+3
| | | | | | Add reset control for PCIe controller on each SoC. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
* dm: define LOG_CATEGORY for all uclassPatrick Delaunay2021-07-061-0/+2
| | | | | | | | Define LOG_CATEGORY for all uclass to allow filtering with log command. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* board: sifive: add HiFive Unmatched board supportGreen Wan2021-05-311-1/+1
| | | | | | | | Add defconfig and board support for HiFive Unmatched. Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
* drivers: clk: add fu740 supportGreen Wan2021-05-311-1/+1
| | | | | | | Add fu740 support. One abstract layer is added for supporting multiple chips such as fu540 and fu740. Signed-off-by: Green Wan <green.wan@sifive.com>
* reset: stm32: Fix bank and offset computationPatrice Chotard2021-05-281-4/+4
| | | | | | | | | | | | BITS_PER_LONG is used to represent register's size which is 32. But when compiled on arch64, BITS_PER_LONG is then equal to 64. Fix bank and offset computation to make it work on arch32 and arch64 and ensure that register's size is always equal to 32. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Pankaj Dev <pankaj.dev@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
* reset: fix reset_get_by_index_nodev index handlingNeil Armstrong2021-04-271-1/+1
| | | | | | | | | | | | | | | This fixes an issue getting resets index 1 and 3+, the spurius "> 0" made it return the index 0 or 1, whatever index was passed. The dm_test_reset_base() did not catch it, but the dm_test_reset_base() extension catches it and this fixes the regression. This also fixes a reggression on Amlogic G12A/G12B SoCs, where HDMI output was disable even when Linux was booting. Fixes: ea9dc35aab ("reset: Get the RESET by index without device") Reported-by: B1oHazard <ty3uk@mail.ua> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* riscv: sifive: Rename fu540 board to unleashedBin Meng2021-04-081-1/+1
| | | | | | | | In preparation to add SiFive Unmatched board support, let's rename the existing fu540 board to unleashed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* common: Drop asm/global_data.h from common headerSimon Glass2021-02-021-0/+1
| | | | | | | | | | | | Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* reset: reset-mtmips: add DM_FLAG_PRE_RELOC flagWeijie Gao2021-01-241-0/+1
| | | | | | | | | Add DM_FLAG_PRE_RELOC flag for reset-mtmips to make sure this driver can be probed before relocation even if u-boot,dm-pre-reloc is not present in the dts. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
* reset: aspeed: Add AST2600 reset supportChia-Wei, Wang2021-01-183-0/+118
| | | | | | | | Add controller reset support through the System Control Unit (SCU) of AST2600 SoC. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
* reset: stm32-reset: migrate trace to dev and log macroPatrick Delaunay2021-01-131-4/+9
| | | | | | | | | | Change debug to dev_dbg macro and define LOG_CATEGORY. Remove the "%s:" __func__ header as it is managed by dev macro (dev->name is displayed). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
* Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into nextTom Rini2021-01-056-6/+10
|\ | | | | | | | | | | | | | | | | Driver model: make some udevice fields private Driver model: Rename U_BOOT_DEVICE et al. dtoc: Tidy up and add more tests ns16550 code clean-up x86 and sandbox minor fixes for of-platdata dtoc prepration for adding build-time instantiation
| * dm: Rename DM_GET_DRIVER() to DM_DRIVER_GET()Simon Glass2021-01-051-1/+1
| | | | | | | | | | | | | | | | In the spirit of using the same base name for all of these related macros, rename this to have the operation at the end. This is not widely used so the impact is fairly small. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-14 08:53:23 +0000