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* drivers: pci: Fix dm_pci_map_bar() to support 64b BARsMoritz Fischer2024-01-181-0/+11
| | | | | | | | This enables 64b BARs if CONFIG_SYS_PCI_64BIT is enabled. Reviewed-by: Philip Oberfichtner <pro@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Moritz Fischer <moritzf@google.com>
* global: Drop common.h inclusionTom Rini2023-12-211-2/+0
| | | | | | | | | In order to make it easier to move on to dropping common.h from code directly, remove common.h inclusion from the rest of the header file which had been including it. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* pci: xilinx: Enable MMIO regionMayuresh Chitale2023-12-131-0/+8
| | | | | | | | | | | The host bridge MMIO region is disabled by default due to which MMIO accesses cause an exception. Fix it by setting the bridge enable bit. This change is ported from the linux pcie-xilinx driver. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20231116165103.140968-3-mchitale@ventanamicro.com Signed-off-by: Michal Simek <michal.simek@amd.com>
* pci: xilinx: Fix "reg" not found errorMayuresh Chitale2023-12-131-17/+12
| | | | | | | | | Fix the driver to use the dev_read_addr_size API to fetch the reg property from the DT. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Link: https://lore.kernel.org/r/20231116165103.140968-2-mchitale@ventanamicro.com Signed-off-by: Michal Simek <michal.simek@amd.com>
* Merge tag 'u-boot-rockchip-20231007' of ↵Tom Rini2023-10-081-8/+50
|\ | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-rockchip - Add Board: rk3568 Bananapi R2Pro; - Update pcie bifurcation support; - dwc_eth_qos controller support for rk3568 and rk3588; - Compressed binary support for U-Boot on rockchip platform; - dts and config updates for different board and soc; [ trini: Fix conflict on include/spl.h ] Signed-off-by: Tom Rini <trini@konsulko.com>
| * pci: pcie_dw_rockchip: Configure number of lanes and link width speedJonas Karlman2023-10-071-8/+50
| | | | | | | | | | | | | | | | | | | | Set number of lanes and link width speed control register based on the num-lanes property. Code imported almost 1:1 from dw_pcie_setup in mainline linux. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | pci: serial: Support reading PCI-register size with baseSimon Glass2023-10-064-5/+6
|/ | | | | | | | | | | | | | The PCI helpers read only the base address for a PCI region. In some cases the size is needed as well, e.g. to pass along to a driver which needs to know the size of its register area. Update the functions to allow the size to be returned. For serial, record the information and provided it with the serial_info() call. A limitation still exists in that the size is not available when OF_LIVE is enabled, so take account of that in the tests. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop linux/printk.h from common headerSimon Glass2023-09-248-0/+8
| | | | | | | | | This old patch was marked as deferred. Bring it back to life, to continue towards the removal of common.h Move this out of the common header and include it only where needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* pci: pcie-brcmstb: do not rely on CLKREQ# signalSam Edwards2023-08-301-5/+13
| | | | | | | | | | | | | | | | | | | | | | When the Broadcom STB PCIe controller is initialized, it must be set into one of three CLKREQ# modes: "none"/"aspm"/"l1ss". The Linux driver, through today, hard-codes "aspm" since the vast majority of boards using this driver have a fixed PCIe bus with the CLKREQ# signal wired up. The Raspberry Pi CM4, however, can be connected to a plethora of PCIe devices, some of which do not connect the CLKREQ# line (they just leave it floating). So "aspm" mode is no longer appropriate in all cases. In Linux, there is a proposed patchset [1] to determine the proper mode. This doesn't really make sense in U-Boot's case, so we just change the assumption from "aspm" to "none" (which is always safe). This patch DOES resolve a real-world crash that occurs when U-Boot is running on a Raspberry Pi CM4 installed in slot 3 of a Turing Pi 2 cluster board. [1]: https://lore.kernel.org/all/20230428223500.23337-1-jim2101024@gmail.com/ Signed-off-by: Sam Edwards <CFSworks@gmail.com>
* pci: pcie-brcmstb: bring over some robustness improvements from LinuxSam Edwards2023-08-301-0/+10
| | | | | | | | | | | | | | | | Since the initial U-Boot driver was ported here from Linux, the latter has had a few changes for robustness/stability. This patch brings over two of them: - Do not attempt to access the configuration space of a PCIe device if the link has gone down, as that will result in an asynchronous SError interrupt which will crash U-Boot. - Wait for the recommended 100ms after PERST# is deasserted. I sent this patch while debugging a crash involving PCIe, but these are unrelated improvements. I do not believe that this patch fixes any real-world bug. Signed-off-by: Sam Edwards <CFSworks@gmail.com>
* Merge tag 'v2023.10-rc3' into nextTom Rini2023-08-212-53/+60
|\ | | | | | | | | | | Prepare v2023.10-rc3 Signed-off-by: Tom Rini <trini@konsulko.com>
| * pci: rockchip: Release resources on failing probeJonas Karlman2023-08-121-51/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PCIe driver for RK3399 is affected by a similar issue that was fixed for RK35xx in the commit e04b67a7f4c1 ("pci: pcie_dw_rockchip: release resources on failing probe"). Resources are not released on failing probe, e.g. regulators may be left enabled and the ep-gpio may be left in a requested state. Change to use regulator_set_enable_if_allowed and disable regulators after failure to keep regulator enable count balanced, ep-gpio is also released on regulator failure. Also add support for the vpcie12v-supply, remove unused include and check return value from dev_read_addr_name. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * pci: plda: Get correct ECAM offset in multiple PCIe RC caseMinda Chen2023-08-101-2/+3
| | | | | | | | | | | | | | | | Get the correct ECAM offset and record the secondary bus number in Multiple RC case. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* | pci: ftpci100: add new driver implementationSergei Antonov2023-08-143-0/+102
| | | | | | | | | | | | | | | | | | | | Add a new DM driver supporting FTPCI100 IP used in SoC designs. This implementation is not based on the old non-DM ftpci100 code dropped from U-Boot. Enable the driver in sandbox_defconfig to test compilability. Signed-off-by: Sergei Antonov <saproj@gmail.com>
* | pci: Fix device_find_first_child() return value handlingMarek Vasut2023-08-141-4/+3
| | | | | | | | | | | | | | | | | | | | This function only ever returns 0, but may not assign the second parameter. Same thing for device_find_next_child(). Do not assign ret to stop proliferation of this misuse. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* | pci: apple: Enable CONFIG_SYS_PCI_64BITMark Kettenis2023-08-141-0/+1
| | | | | | | | | | | | | | | | The Apple hardware supports 64-bit prefetchable memory windows so enable CONFIG_SYS_PCI_64BIT. This fixes BAR assignments for the Broadcom Ethernet controller used in some of the desktop machines. Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
* | pci: correct function name in messageHeinrich Schuchardt2023-08-081-2/+2
|/ | | | | | | | | If an error message contains a function name, it should match the name of the function throwing the message. Fixes: 7739d93d8288 ("pci: Match region flags using a mask") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* starfive: pci: Add StarFive JH7110 pcie driverMason Huo2023-08-025-0/+566
| | | | | | | | | | | | | | Add pcie driver for StarFive JH7110, Also add PLDA PCIe controller common driver functions. Several devices are tested: a) M.2 NVMe SSD b) Realtek 8169 Ethernet adapter. Signed-off-by: Mason Huo <mason.huo@starfivetech.com> Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Acked-by: Pali Rohár <pali@kernel.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* spl: CONFIG_SPL_PCI_PNP should depend on CONFIG_SPL_PCIHeinrich Schuchardt2023-07-301-1/+2
| | | | | | | | CONFIG_SPL_PCI_PNP=y without CONFIG_SPL_PCI=y makes no sense. Fixes: 32f5e9e5c1a7 ("nvme: pci: Enable for SPL") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* pci: pcie_dw_rockchip: Disable unused BARs of the root complexJon Lin2023-07-281-0/+8
| | | | | | | | | | | | The Root Complex BARs default to claim the full 1 GiB memory region on RK3568, leaving no space for any attached device. Fix this by disable the unused BAR 0 and BAR 1 of the RC. Signed-off-by: Jon Lin <jon.lin@rock-chips.com> [jonas@kwiboo.se: Move to rk_pcie_configure and use PCI_BASE_ADDRESS_0/1 const] Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* pci: pcie_dw_rockchip: Speed up link probeJonas Karlman2023-07-281-31/+37
| | | | | | | | | | | Use a similar pattern and delay values as the linux mainline driver to speed up failing when nothing is connected. Reduce fail speed from around 5+ seconds down to around one second on a Radxa ROCK 3 Model A, where pcie2x1 is probed before pcie3x2 M2 slot. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* pci: pcie_dw_rockchip: Use regulator_set_enable_if_allowedJonas Karlman2023-07-281-10/+7
| | | | | | | | | | | | | | The vpcie3v3 regulator is typically a fixed regulator controlled using gpio. Change to use enable and disable calls on the regulator instead of trying to set a voltage value. Also remove the delay to match linux driver, for a fixed regulator the startup-delay-us prop can be used in case a startup delay is needed. Limited testing on ROCK 3A, ROCK 5B, Quartz64, Odroid-M1 has shown that this delay was not needed. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* pci: pcie_dw_rockchip: Get config region from reg propJonas Karlman2023-07-282-4/+13
| | | | | | | | Get the config region to use from the reg prop. Also update the referenced region index used in comment. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* pci: Mask the ROM address in case it is already enabledSimon Glass2023-07-171-0/+1
| | | | | | | | In some cases the video ROM may have been enabled previously, such as by a previous firmware stage. Use the correct address in that case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: Adjust video BIOS debugging to be SPL-friendlySimon Glass2023-07-171-2/+2
| | | | | | | | | A hex value is expected for the VGA mode. Add a 0x prefix, since the # construct is not supported in SPL. We don't want to add it, due to code-size constraints. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Pass video settings from SPL to U-Boot properSimon Glass2023-07-171-21/+57
| | | | | | | | | | | When video is set up in SPL, U-Boot proper needs to use the correct parameters so it can write to the display. Put these in a bloblist so they are available to U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Nikhil M Jain <n-jain1@ti.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Allow video-BIOS code to be built for SPLSimon Glass2023-07-171-14/+14
| | | | | | | | | With qemu-x86_64 we need to run the video BIOS while in 32-bit mode, i.e. SPL. Add a Kconfig option for this, adjust the Makefile rules and use CONFIG_IS_ENABLED() where needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: Tidy up logging and reporting for video BIOSSimon Glass2023-07-171-3/+9
| | | | | | | | | When running the ROM the code is not very helpful when something goes wrong. Add a little more debugging and some logging of return values to improve this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: Support autoconfig in SPLSimon Glass2023-07-172-1/+14
| | | | | | | | | | Allow PCI autoconfig to be handled in SPL, so that we can set it up correctly for boards which need to do this before U-Boot proper. This includes qemu-x64_64 which needs to set up the video device while in 32-bit mode. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* nvme: pci: Enable for SPLMayuresh Chitale2023-06-191-0/+6
| | | | | | | Enable NVME and PCI NVMe drivers for SPL builds. Also enable PCI_PNP for SPL which is required to auto configure the PCIe devices. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
* PCI: zynqmp: Add ZynqMP NWL PCIe root port driverStefan Roese2023-06-123-0/+360
| | | | | | | | | | | | | | | | | | This patch adds the PCIe controller driver for the Xilinx / AMD ZynqMP NWL PCIe Bridge as root port. The driver source is partly copied from the Linux PCI driver and modified to enable usage in U-Boot (e.g. simplified and interrupt support removed). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Pali Rohár <pali@kernel.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> Acked-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Pali Rohár <pali@kernel.org> Link: https://lore.kernel.org/r/20230525094918.111949-1-sr@denx.de Signed-off-by: Michal Simek <michal.simek@amd.com>
* pci: apple: Add support for M2 Pro/MaxMark Kettenis2023-05-301-29/+71
| | | | | | | | | The PCIe controller on the M2 Pro/Max is different from the one found on earlier Apple SoCs. Some registers moved and te meaning of the bits in some other registers changed. But they are still similar enough to handle both controllers in the same driver. Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
* pci: pcie_dw_rockchip: Support max_link_speed dts propertyJon Lin2023-05-171-1/+5
| | | | | | | | | | | | Add support for max_link_speed specified in the PCI DT binding. Signed-off-by: Jon Lin <jon.lin@rock-chips.com> [eugen.hristev@collabora.com: port to latest API, set default correctly, align to 80 chars] Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> [jonas@kwiboo.se: switch to dev_read_u32_default] Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* pci: pcie_dw_rockchip: Add rk3588 compatibleJon Lin2023-05-171-0/+1
| | | | | | | Add compatible for RK3588 SoC. Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* pci: coreboot: Don't read regions when bootingSimon Glass2023-05-111-0/+4
| | | | | | | | | | | | | When U-Boot is the second-stage bootloader, PCI is already set up. We cannot read the regions from the device tree. There is no point anyway, since PCI devices have already been allocated according to the regions and it is not safe for U-Boot to make any changes. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Fixes: f2ebaaa9f38d ("pci: Handle failed calloc in decode_regions()") Tested-by: Christian Gmeiner <christian.gmeiner@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* pci: pcie_dw_rockchip: release resources on failing probeEugen Hristev2023-05-091-11/+30
| | | | | | | | | | | | | | | | Implement a resource release mechanism on failing probe. Without this, a strange situation can happen e.g. when init port fails, or attempting to get the PHY fails, because the gpios have been requested first, and if the user tries to do 'pci enum' again, the driver will fail with 'can't find reset gpios' even if the gpios are there, just because they were blocked by a previous probe attempt. It is only natural to release the acquired resources if the probe fails, just for consistency if nothing else. This way on subsequent probe attempts, the user will get the same error message, and not something different that doesn't make sense. Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* drivers: use devfdt_get_addr_index_ptr when cast to pointerJohan Jonker2023-05-063-8/+8
| | | | | | | | | | | The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use devfdt_get_addr_index_ptr instead of the devfdt_get_addr_index function in the various files in the drivers directory that cast to a pointer. As we are there also streamline the error response to -EINVAL on return. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* drivers: use devfdt_get_addr_size_index_ptr when cast to pointerJohan Jonker2023-05-061-3/+3
| | | | | | | | | | | | The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use devfdt_get_addr_size_index_ptr instead of the devfdt_get_addr_size_index function in the various files in the drivers directory that cast to a pointer. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* drivers: use dev_read_addr_ptr when cast to pointerJohan Jonker2023-05-061-2/+2
| | | | | | | | | | | The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use dev_read_addr_ptr instead of the dev_read_addr function in the various files in the drivers directory that cast to a pointer. As we are there also streamline the error response to -EINVAL on return. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* drivers: use dev_read_addr_index_ptr when cast to pointerJohan Jonker2023-05-062-8/+8
| | | | | | | | | | | | The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use dev_read_addr_index_ptr instead of the dev_read_addr_index function in the various files in the drivers directory that cast to a pointer. As we are there also streamline the error response to -EINVAL on return. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* pci: layerscape: add support for kernel/official fsl, ls1088a-pcie bindingMathew McBride2023-05-051-0/+1
| | | | | | | | | | | | | | | This allows the Layerscape PCIe RC driver to use the upstream style binding (two "reg" entries instead of four). It is similar to the previous commit e10da1f985ad ("pci: layerscape: add official ls1028a binding support") which implemented this for the LS1028A. Signed-off-by: Mathew McBride <matt@traverse.com.au> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com> Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
* pci: fsl: Do not access PCI BAR0 register of PCIe Root PortPali Rohár2023-05-031-0/+14
| | | | | | | | Freescale PCIe Root Port has PEXCSRBAR register at position of PCI BAR0. PCIe Root Port does not have any PCIe memory, so returns zero when trying to read from PCIe Root Port BAR0 and ignore any writes. Signed-off-by: Pali Rohár <pali@kernel.org>
* pci: auto: Remove PCI_CLASS_PROCESSOR_POWERPC autoconfig casePali Rohár2023-05-021-4/+0
| | | | | | | | | | PCI autoconfig case for PCI_CLASS_PROCESSOR_POWERPC just prints debug message and then calls autoconfig setup code like for any other standard endpoint device. We do not need special debug message for it, so remove this case and handle PCI_CLASS_PROCESSOR_POWERPC via default code path. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Heiko Schocher <hs@denx.de>
* pci: mpc85xx: Do not access PCI BARs registers of BDF address 00:00.0Pali Rohár2023-05-011-0/+12
| | | | | | | | | | | | | | | | | | | At BDF address 00:00.0 is fictional device which PCI configuration header is for configuring mpc85xx PCI controller itself. PCI config space of this device has ATMU inbound registers on position of PCI BARs. Trying to do PCI auto configuration of this device cause rewriting ATMU inbound registers. To avoid it, do not allow overwriting registers at BARs positions. And because this device does not have any PCI memory, return zeros when trying to read PCI BARs config space registers. It signals to auto configuration tool to not allocate any PCI memory for this device. This information is taken from MPC8544E Reference Manual, sections 17.3.1.3, 17.3.1.1.1, 17.3.2 and 17.3.2.11. Available at NXP website: https://www.nxp.com/docs/en/reference-manual/MPC8544ERM.pdf Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Heiko Schocher <hs@denx.de> Tested-by: Heiko Schocher <hs@denx.de>
* pci: mpc85xx: Do not try to access extended PCIe registersPali Rohár2023-05-011-2/+10
| | | | | | | | | | | | Driver pci_mpc85xx.c is PCI controller driver for old PCI Local Bus, which does not support access to extended PCIe registers (above 0xff), as opposite of the PCIe driver pcie_fsl.c for the same platform. So do not try to access extended PCIe registers as it cannot work. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Heiko Schocher <hs@denx.de> Tested-by: Heiko Schocher <hs@denx.de>
* pci: mpc85xx: Allow 8/16-bit access to PCI config spacePali Rohár2023-05-011-2/+24
| | | | | | | | | | | | | This Freescale mpc85xx PCI controller should support 8-bit and 16-bit read and write access to PCI config space as described in more Freescale reference manuals. This change fixes issue that 8-bit and 16-bit write to PCI config space caused to clear adjacent bits of 32-bit PCI register. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Heiko Schocher <hs@denx.de> Tested-by: Heiko Schocher <hs@denx.de>
* pci: mpc85xx: Add missing sync() after writing to PCI config spacePali Rohár2023-05-011-0/+1
| | | | | | | | On PowerPC we should use barrier after store operation to HW register. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Heiko Schocher <hs@denx.de> Tested-by: Heiko Schocher <hs@denx.de>
* pci: apple: Initialize only enabled portsJanne Grunau2023-03-291-0/+2
| | | | | | | | | The Linux devicetrees for Apple silicon devices are after review feedback switching from deleting unused PCIe ports to disabling them. Link: https://lore.kernel.org/asahi/1ea2107a-bb86-8c22-0bbc-82c453ab08ce@linaro.org/ Signed-off-by: Janne Grunau <j@jannau.net> Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
* efi: Support a 64-bit frame buffer addressSimon Glass2023-03-131-4/+6
| | | | | | | | | | | | The current vesa structure only provides a 32-bit value for the frame buffer. Many modern machines use an address outside the range. It is still useful to have this common struct, but add a separate frame-buffer address as well. Add a comment for vesa_setup_video_priv() while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
* sh4: Drop unused pci_sh7780 driverSimon Glass2023-02-072-93/+0
| | | | | | This is not used. Drop the driver and Kconfig option. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-11 21:28:19 +0000