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* mtd: spi-nor-ids: Add support for ESMT/EON EN25Q80BFrieder Schrempf2024-02-191-0/+1
| | | | | | | | The datasheet can be found here: https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/EN25Q80B_Ver.E.pdf Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
* Merge tag 'u-boot-at91-2024.04-a' of ↵Tom Rini2024-01-311-3/+0
|\ | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-at91 First set of u-boot-at91 features for the 2024.04 cycle: This set includes some DT alignments and solves a compile issue for custom nand defconfigs.
| * mtd: nand: raw: atmel: Remove duplicate definitionsAlexander Dahl2024-01-221-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These removed definitions were specific to some sam9 SoCs, but not generic over all at91 SoCs. The correct SoC specific definitions for ATMEL_BASE_PMECC are spread over different header files in arch/arm/mach-at91/include/mach directory. Fixes a build error on a custon board based on SAMA5D2: Building current source for 73 boards (16 threads, 1 job per thread) arm: + vera2 +drivers/mtd/nand/raw/atmel/pmecc.c:819: warning: "ATMEL_BASE_PMECC" redefined + 819 | #define ATMEL_BASE_PMECC 0xffffe000 + | +In file included from include/configs/vera2.h:11, + from include/config.h:3, + from include/linux/mtd/rawnand.h:16, + from drivers/mtd/nand/raw/atmel/pmecc.c:44: +include/asm/arch/sama5d2.h:171: note: this is the location of the previous definition + 171 | #define ATMEL_BASE_PMECC (ATMEL_BASE_HSMC + 0x70) +drivers/mtd/nand/raw/atmel/pmecc.c:820: warning: "ATMEL_BASE_PMERRLOC" redefined + 820 | #define ATMEL_BASE_PMERRLOC 0xffffe600 +include/asm/arch/sama5d2.h:172: note: this is the location of the previous definition + 172 | #define ATMEL_BASE_PMERRLOC (ATMEL_BASE_HSMC + 0x500) Fixes: a490e1b7c017 ("nand: atmel: Add pmecc driver") Signed-off-by: Alexander Dahl <ada@thorsis.com>
* | treewide: Remove clk_freeSean Anderson2024-01-292-4/+1
| | | | | | | | | | | | | | This function is a no-op. Remove it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20231216193843.2463779-3-seanga2@gmail.com
* | mtd: spi-nor-ids: Add Infineon(Cypress) s28hs02gt IDTakahiro Kuwano2024-01-291-0/+1
| | | | | | | | | | | | | | | | | | | | Infineon(Cypress) S28HS02GT is 1.8V, 2Gb (256MB) NOR Flash memory with Octal interface. It is a dual-die package parts and has same features with existing S28 series. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Dhruva Gole <d-gole@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | mtd: spi-nor-core: Rework spi_nor_cypress_octal_dtr_enable()Takahiro Kuwano2024-01-291-27/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | Enabling Octal DTR mode in multi-die package parts requires reister setup for each die. That can be done by simple for-loop. write_enable() takes effect to all die at once so we can call it before the loop. Besides we can replace spi_mem_exec_op() calls with spansion_read/write_any_reg(). And finally, we must mask CFR2V[7:4] when changing dummy cycles, as CFR2V[7] indicates current addressing mode and that should be 1 (4-byte address mode) for multi-die package parts. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | mtd: spi-nor-core: Consolidate post_bfpt_fixup() for Infineon(Cypress) S25 ↵Takahiro Kuwano2024-01-291-46/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and S28 s28hx_t_post_bfpt_fixup() fixes erase opcode, erase size, and page size. s25_post_bfpt_fixup() is doing same thing including multi-die support. We can consolidate s28hx_t_post_bfpt_fixup() and s25_post_bfpt_fixup() into one named s25_s28_post_bfpt_fixup(). In s25_s28_post_bfpt_fixup(), set_4byte() is called to force the device to be 4-byte addressing mode. In S28HS02GT datasheet, the B7 opcode is missing but it works actually (confirmed). Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | mtd: spi-nor-core: Consolidate setup() hook for Infineon(Cypress) S25 and S28Takahiro Kuwano2024-01-291-37/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | s28hx_t_setup() only checks sector layout setting. To support multi-die package parts like S28HS02GT, it needs to check device size and assign ready() hook for multi-die package parts. These are covered in s25_setup() so we can consolidate s28hx_t_setup() and s25_setup() into one named s25_s28_setup(). spi_nor_wait_till_ready() at the beginning of s28hx_t_setup() can be removed since there is no op that makes device busy state before setup. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | mtd: spi-nor-core: Rework s25_mdp_ready() to support Octal DTR modeTakahiro Kuwano2024-01-291-3/+3
| | | | | | | | | | | | | | | | | | | | s25_mdp_ready() handles status polling for multi-die package parts that requires to read and check status register for each die. To support S28HS02GT(dual-die package with Octal DTR support), rename function and use nor->rdsr_dummy in octal DTR mode. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | mtd: spi-nor-core: Use CLPEF(0x82) as alternative to CLSR(0x30) for S25 and S28Takahiro Kuwano2024-01-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Infineon(Cypress) S28Hx-T family does not support legacy CLSR(0x30) opcode. Instead, it supports CLPEF(0x82) which has the same functionality as CLSR. spansion_sr_ready() is for multi-die package parts including S28HS02GT, so we need to use CLPEF instead of CLSR. This change does not affect to S25x02GT which uses spansion_sr_ready() as S25Hx-T family also supports CLPEF(0x82) as well as CLSR(0x30). Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | mtd: spi-nor-core: Rework spansion_read_any_reg() to support Octal DTR modeTakahiro Kuwano2024-01-291-5/+29
| | | | | | | | | | | | | | | | | | | | | | In Infineon multi-die package parts, we need to use Read Any Register op to read status register in 2nd or further die. Infineon S28HS02GT is dual-die package and supports Octal DTR interface. To support this, spansion_read_any_reg() needs to be reworked. Implementation is similar to existing read_sr() that already supports Octal DTR mode. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | mtd: spi-nor-core: Consolidate non-uniform erase helpers for S25 and S28Takahiro Kuwano2024-01-291-10/+3
| | | | | | | | | | | | | | | | | | s25_erase_non_uniform() and s28hx_t_erase_uniform() support hybrid sector layout (32 x 4KB sectors overlaid at bottom address) and doing same thing. Consolidate them into single helper named s25_s28_erase_non_uniform(). Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | mtd: spi-nor-core: Clean up macros for Infineon(Cypress) S25 and S28Takahiro Kuwano2024-01-291-12/+14
| | | | | | | | | | | | | | | | | | Some macro definitions used in Infineon(Cypress) S25 and S28 series are redundant and some have inconsistent prefix. This patch removes redundant ones and renames some to have same prefix as others. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | mtd: spi: spi-nor-ids: Add more XM25Q series chipsSsunk2024-01-291-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | - XM25QH128C - XM25QH256C - XM25QU256C - XM25QH512C - XM25QU512C Signed-off-by: Kankan Sun <ssunkkan@gmail.com> [jagan: update the commit message] Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | mtd: spi-nor-ids: Add is25lx512 chipTejas Bhumkar2024-01-291-0/+2
| | | | | | | | | | | | | | | | | | Added support for the ISSI OSPI flash part IS25LX512M. Initial testing was performed on the Tenzing-se1 board using SDR mode, covering basic erase, write, and readback operations. Signed-off-by: Tejas Bhumkar <tejas.arvind.bhumkar@amd.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | mtd: Make CONFIG_MTD be the gate symbol for the menuTom Rini2024-01-221-2/+4
|/ | | | | | | | | | | | | The help for CONFIG_MTD explains that it needs to be enabled for various things like NAND, etc to be available. It however then doesn't enforce this dependency and so if you have none of these systems present you still need to disable a number of options. Fix this by making places that select/imply one type of flash, but did not do the same, also do this for "MTD". Make boards which hadn't been enabling MTD already but need it now, do so. In a few places, disable CONFIG_CMD_MTDPARTS as it wasn't previously enabled but was now being implied. Signed-off-by: Tom Rini <trini@konsulko.com>
* mtd: rawnand: omap_gpmc: fix OF based partition parsing for NANDRoger Quadros2024-01-151-0/+2
| | | | | | | | | Set NAND chip ofnode and device so OF based partition parsing can work. Signed-off-by: Roger Quadros <rogerq@kernel.org> Link: https://www.mail-archive.com/u-boot@lists.denx.de/msg499178.html Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
* mtd: rawnand: omap_gpmc: Use DT provided IO addressRoger Quadros2024-01-151-5/+14
| | | | | | | | | | For DM case we can get the NAND chip's IO address from DT so we don't need to rely on CFG_SYS_NAND_BASE. Signed-off-by: Roger Quadros <rogerq@kernel.org> Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Link: https://www.mail-archive.com/u-boot@lists.denx.de/msg499177.html Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
* mtd: rawnand: omap_elm: Fix elm_init definitionRoger Quadros2024-01-152-8/+2
| | | | | | | | | | | | The macro ELM_BASE is defined in mach/hardware.h and is not visible at the omap_elm.h header file. Avoid using it in omap_elm.h. Reported-by: Hong Guan <hguan@ti.com> Fixes: 7363cf0581a3 ("mtd: rawnand: omap_elm: u-boot driver model support") Signed-off-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/all/20231211114600.4414-3-rogerq@kernel.org Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
* mtd: nand: omap_gpmc: Fix NAND in SPL for AM335xRoger Quadros2024-01-151-66/+29
| | | | | | | | | | | | | | | | | | | | AM335x uses a special driver "am335x_spl_bch.c" as SPL NAND loader. This driver expects 1 sector at a time ECC and doesn't work well with multi-sector ECC that was implemented in commit 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction") Additionally, the omap_elm driver does not support multi sector ECC and will need more work and tests to get multi sector working correctly on all platforms. Switch back to 1 sector at a time read/ECC. Fixes: 04fcd2587321 ("mtd: rawnand: omap_gpmc: Fix BCH6/16 HW based correction") Signed-off-by: Roger Quadros <rogerq@kernel.org> Tested-by: Enrico Leto <enrico.leto@siemens.com> Tested-by: Heiko Schocher <hs@denx.de> Link: https://lore.kernel.org/all/20231211114600.4414-2-rogerq@kernel.org/ Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
* mtd: nand: check nand_mtd_to_devnum() argumentDario Binacchi2024-01-151-1/+4
| | | | | | | | | If the "mtd" parameter is NULL, the search will definitely yield a negative result. In that case, it's better to exit immediately. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Link: https://lore.kernel.org/all/20231102113829.58852-1-dario.binacchi@amarulasolutions.com
* mtd: nand: complete nand_register() arguments checkDario Binacchi2024-01-151-1/+1
| | | | | | | | | The patch checks that the "mtd" parameter is accessible before proceeding. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Link: https://lore.kernel.org/all/20231102112743.57420-1-dario.binacchi@amarulasolutions.com
* Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-spi ↵Tom Rini2023-12-186-3/+200
|\ | | | | | | | | | | | | into next - spi_nor_read_sfdp_dma_unsafe (Vaishnav) - w25q01/02 (Jim)
| * mtd: spi-nor-ids: add support for xtx XT55Q02GBruce Suen2023-12-141-0/+2
| | | | | | | | | | | | | | Add support for XTX XT55Q02G(1.8V,2Gbit). Signed-off-by: Bruce Suen <bruce_suen@163.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * mtd: spinand: add support for ESMT F50x1G41LBIgor Prusov2023-12-143-1/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adaptation of Linux commit d74c36480a67 This patch adds support for ESMT F50L1G41LB and F50D1G41LB. It seems that ESMT likes to use random JEDEC ID from other vendors. Their 1G chips uses 0xc8 from GigaDevice and 2G/4G chips uses 0x2c from Micron. For this reason, the ESMT entry is named esmt_c8 with explicit JEDEC ID in variable name. Datasheets: https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/F50L1G41LB(2M).pdf https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/F50D1G41LB(2M).pdf Signed-off-by: Igor Prusov <ivprusov@salutedevices.com> Signed-off-by: Chuanhong Guo <gch981213@gmail.com> Signed-off-by: Martin Kurbanov <mmkurbanov@sberdevices.ru> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Tested-by: Martin Kurbanov <mmkurbanov@sberdevices.ru> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * mtd: spi-nor-core: Implement spi_nor_read_sfdp_dma_unsafe() for sfdp parseVaishnav Achath2023-12-141-2/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | During SFDP header parse and BFPT parse, structures in stack are used to perform spi_nor_read_sfdp() which expects a dma-safe buffer. This commit introduces spi_nor_read_sfdp_dma_unsafe() to wrap spi_nor_read_sfdp() using a kmalloc'ed bounce buffer which is the same implementation in Linux (drivers/mtd/spi-nor/sfdp.c). Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * mtd: spi-nor: add flash model w25q01/02 supportJim Liu2023-12-091-0/+10
| | | | | | | | | | | | | | add flash w25q01jv, w25q01jvfim and w25q02jv support Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * mtd: spi-nor: Add MT25QU128AB paramsGodfrey Mwangi2023-12-091-0/+1
| | | | | | | | | | | | | | | | | | Add Micron MT25QU128AB flash. Signed-off-by: Godfrey Mwangi <godmwan@microsoft.com> [jagan: fix the commit head] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * mtd: spi-nor: Add MT25U01G part number for SPI NOR FlashJit Loon Lim2023-12-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | MT25QU01 OPN with 4B OPCODE support is currently not supported in source code and the driver reuses the definition for "n25q00a" which has the same silicon ID but is a slower part. Adding mt25u01g definition to the source code to support a faster read response for MT25QU01 QSPI NOR Flash device. Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> [jagan: fix the id position and commit head] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * drivers: mtd: spi: Add support for GD55LB02GEBIR SPI NOR flashTeik Heng Chong2023-12-091-0/+5
| | | | | | | | | | | | | | | | Add Support for GigaDevice GD55LB02GEBIR SPI NOR flash as QSPI configuration flash Signed-off-by: Teik Heng Chong <teik.heng.chong@intel.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * mtd: spi-nor: Add support for Silicon Kaiser sk25lp128Jonas Karlman2023-12-062-0/+9
| | | | | | | | | | | | | | Add support for Silicon Kaiser sk25lp128 SPI NOR flash found in Pine64 PinePhone Pro and PineTab2. Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
* | Merge tag 'v2024.01-rc5' into nextTom Rini2023-12-182-0/+10
|\ \ | | | | | | | | | Prepare v2024.01-rc5
| * | mtd: spi-nor: Add support for zBIT ZB25VQ128Andre Przywara2023-12-062-0/+10
| |/ | | | | | | | | | | | | | | Add support for the zBIT ZB25VQ128 (128M-bit) SPI NOR flash memory chip, as used on the Xunlong Orange Pi Zero 3 board. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Dragan Simic <dsimic@manjaro.org>
* | Merge patch series "Import "string" I/O functions from Linux"Tom Rini2023-11-282-67/+0
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | To quote the author: This series imports generic versions of ioread_rep/iowrite_rep and reads/writes from Linux. Some cleanup is done to make sure that all platforms have proper defines for implemented functions and there are no redefinitions.
| * | asm-generic: Import functions from LinuxIgor Prusov2023-11-282-67/+0
| |/ | | | | | | | | | | | | | | | | | | | | | | Currently {read,write}s{b,w,lq}() functions are available only on some architectures, and there are no io{read,write}{8,16,32,64}_rep() functions in u-boot. This patch adds generic versions that may be used without arch-specific implementation. Since some of added functions were already added locally in some files, remove them to avoid redeclaration errors. Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
* | Merge tag 'v2024.01-rc3' into nextTom Rini2023-11-204-3/+16
|\| | | | | | | Prepare v2024.01-rc3
| * tree-wide: Replace http:// link with https:// link for ti.comNishanth Menon2023-11-102-2/+2
| | | | | | | | | | | | Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
| * mtd: spi-nor: Add spi flash lock config optionVenkatesh Yadav Abbarapu2023-11-072-1/+14
| | | | | | | | | | | | | | | | | | | | | | Provide an explicit configuration option to disable default "lock" of any flash chip which supports locking. By disabling the lock config will save some amount of memory and also don't expose the lock functionality to the users i.e., via sf protect command. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Link: https://lore.kernel.org/r/20231003031715.5343-2-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
* | Merge branch '2023-11-16-assorted-updates' into nextTom Rini2023-11-174-8/+5
|\ \ | | | | | | | | | | | | | | | | | | - squashfs improvements, remove common.h in some places, assorted code fixes, fix a few CONFIG symbol names in Kconfig files, bring in linux's <linux/time.h> conversion functions, poplar updates, bcb improvements.
| * | treewide: use linux/time.h for time conversion definesIgor Prusov2023-11-164-8/+5
| |/ | | | | | | | | | | | | | | | | | | | | | | Now that we have time conversion defines from in time.h there is no need for each driver to define their own version. Signed-off-by: Igor Prusov <ivprusov@salutedevices.com> Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com> # tegra Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com> #at91 Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> #qcom geni Reviewed-by: Stefan Bosch <stefan_b@posteo.net> #nanopi2 Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
* | test: spl: Add a test for NANDSean Anderson2023-11-162-1/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a SPL test for the NAND load method. We use some different functions to do the writing from the main test since things like nand_write_skip_bad aren't available in SPL. We disable BBT scanning, since scan_bbt is only populated when not in SPL. We use nand_spl_loaders.c as it seems to be common to at least a few boards already. However, we do not use nand_spl_simple.c because it would require us to implement cmd_ctrl. The various nand load functions are adapted from omap_gpmc. However, they have been modified for simplicity/correctness. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* | nand: Add sandbox driverSean Anderson2023-11-163-0/+693
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a sandbox NAND flash driver to facilitate testing. This driver supports any number of devices, each using a single chip-select. The OOB data is stored in-band, with the separation enforced through the API. For now, create two devices to test with. The first is a very small device with basic ECC. The second is an 8G device (chosen to be larger than 32 bits). It uses ONFI, with the values copied from the datasheet. It also doesn't need too strong ECC, which speeds things up. Although the nand subsystem determines the parameters of a chip based on the ID, the driver itself requires devicetree properties for each parameter. We do not derive parameters from the ID because parsing the ID is non-trivial. We do not just use the parameters that the nand subsystem has calculated since that is something we should be testing. An exception is made for the ECC layout, since that is difficult to encode in the device tree and is not a property of the device itself. Despite using file I/O to access the backing data, we do not support using external files. In my experience, these are unnecessary for testing since tests can generally be written to write their expected data beforehand. Additionally, we would need to store the "programmed" information somewhere (complicating the format and the programming process) or try to detect whether block are erased at runtime (degrading probe speeds). Information about whether each page has been programmed is stored in an in-memory buffer. To simplify the implementation, we only support a single program per erase. While this is accurate for many larger flashes, some smaller flashes (512 byte) support multiple programs and/or subpage programs. Support for this could be added later as I believe some filesystems expect this. To test ECC, we support error-injection. Surprisingly, only ECC bytes in the OOB area are protected, even though all bytes are equally susceptible to error. Because of this, we take care to only corrupt ECC bytes. Similarly, because ECC covers "steps" and not the whole page, we must take care to corrupt data in the same way. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* | nand: Allow reinitializationSean Anderson2023-11-161-7/+33
| | | | | | | | | | | | | | | | NAND devices are destroyed in between unit tests. Provide a function to reinitialize the subsystem at the beginning of each test. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
* | nand: Add function to unregister NAND devicesSean Anderson2023-11-161-0/+17
| | | | | | | | | | | | | | | | | | | | This performs the opposite of nand_register, allowing drivers to unregister nand devices. This is probably unnecessary for most regular drivers, but we expect sandbox drivers to get repeatedly bound/unbound, so this will help avoid dangling pointers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
* | mtd: Add some fallbacks for add/del_mtd_deviceSean Anderson2023-11-162-4/+0
| | | | | | | | | | | | | | | | This allows using these functions without ifdefs. OneNAND depends on MTD, so this ifdef was redundant in the first place. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
* | mtd: Rename SPL_MTD_SUPPORT to SPL_MTDSean Anderson2023-11-161-1/+1
| | | | | | | | | | | | | | Rename SPL_MTD_SUPPORT to SPL_MTD in order to match MTD. This allows using CONFIG_IS_ENABLED to test for MTD support. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* | spl: nand: Set bl_len to page sizeSean Anderson2023-11-1611-1/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 34793598c83 ("mtd: nand: mxs_nand_spl: Remove the page aligned access") there are no longer any users of nand_get_mtd. However, it is still important to know what the page size is so we can allocate a large-enough buffer. If the image size is not page-aligned, we will go off the end of the buffer and clobber some memory. Introduce a new function nand_page_size which returns the page size. For most drivers it is easy to determine the page size. However, a few need to be modified since they only keep the page size around temporarily. It's possible that this patch could cause a regression on some platforms if the offset is non-aligned and there is invalid address space immediately before the load address. spl_load_legacy_img does not (except when compressing) respect bl_len, so only boards with SPL_LOAD_FIT (8 boards) or SPL_LOAD_IMX_CONTAINER (none in tree) would be affected. defconfig CONFIG_TEXT_BASE ======================= ================ am335x_evm 0x80800000 am43xx_evm 0x80800000 am43xx_evm_rtconly 0x80800000 am43xx_evm_usbhost_boot 0x80800000 am43xx_hs_evm 0x80800000 dra7xx_evm 0x80800000 gwventana_nand 0x17800000 imx8mn_bsh_smm_s2 0x40200000 All the sitara boards have DDR mapped at 0x80000000. gwventana is an i.MX6Q which has DDR at 0x10000000. I don't have the IMX8MNRM handy, but on the i.MX8M DDR starts at 0x40000000. Therefore all of these boards can handle a little underflow. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* | nand: spl_loaders: Only read enough pages to load the imageSean Anderson2023-11-161-1/+4
| | | | | | | | | | | | | | | | | | | | All other implementations of nand_spl_load_image only read as many pages as are necessary to load the image. However, nand_spl_loaders.c loads the full block. Align it with other load functions so that it is easier to determine how large of a load buffer we need. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
* | nand: Calculate SYS_NAND_BLOCK_PAGES (neé SYS_NAND_PAGE_COUNT) automaticallySean Anderson2023-11-167-17/+14
| | | | | | | | | | | | | | | | | | Contrary to what the help message says, this is the number of pages per block. Calculate it automatically based on SYS_NAND_BLOCK_SIZE and SYS_NAND_PAGE_SIZE. To better reflect its semantics, rename it to SYS_NAND_BLOCK_PAGES. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* | nand: Don't dereference NULL manufacturer_descSean Anderson2023-11-161-5/+2
|/ | | | | | | | | When no manufacturer is matched, manufacturer_desc is NULL. Avoid dereferencing it in that case. Fixes: 4e67c571252 ("mtd,ubi,ubifs: sync with linux v3.15") Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
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