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* ddr: imx9: update the rank setting for multi fsp supportJacky Bai2023-05-211-62/+116
| | | | | | | | | The rank setting flow should be updated to support multi fsp config. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* ddr: imx93: update the ddr init to support mult setpointsJacky Bai2023-05-212-5/+113
| | | | | | | | | | Update the DDR init flow for multi-setpoint support on i.MX93. A new fsp_cfg struct need to be added in the timing file to store the diff part of the DDRC and DRAM MR register for each setpoint. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* ddr: imx93: Add 625M bypass clock supportJacky Bai2023-05-211-0/+3
| | | | | | | | | Add 625M bypass clock that may be used DRAM 625M bypass mode support. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* ddr: imx9: Change the saved ddr data base to 0x2051c000Jacky Bai2023-05-211-1/+1
| | | | | | | | | change the ddr saved info to the last 16KB of the OCRAM. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* ddr: imx9: Add workaround for DDRPHY rank-to-rank errataYe Li2023-05-211-0/+122
| | | | | | | | | | | | | | According to DDRPHY errata, the Rank-to-Rank Spacing and tphy_rdcsgap specification does not include the Critical Delay Difference (CDD) to properly define the required rank-to-rank read command spacing after executing PHY training firmware. Following the errata workaround, at the end of data training, we get all CDD values through the MessageBlock, then re-configure the DDRC timing of WWT/WRT/RRT/RWT with comparing MAX CDD values. Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com>
* drivers: use devfdt_get_addr_index_ptr when cast to pointerJohan Jonker2023-05-061-2/+2
| | | | | | | | | | | The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use devfdt_get_addr_index_ptr instead of the devfdt_get_addr_index function in the various files in the drivers directory that cast to a pointer. As we are there also streamline the error response to -EINVAL on return. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ddr: marvell: a38x: Perform DDR training sequence again for 2nd bootTony Dinh2023-04-131-7/+0
| | | | | | | | | | | | | | - DDR Training sequence happens very fast. The speedup in boot time is negligible by skipping the training sequence during 2nd boot or after. So remove the check and skip. - This change improves the robustness of DDR training. If u-boot crashed during DDR training, the training could be left in a limbo state, where the BootROM has recorded that it is already in a 2nd boot. The training must be repeated in this scenario to get out of this limbo state, but due to the check it cannot be performed. Signed-off-by: Tony Dinh <mibodhi@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
* ddr: imx: Update the ddr init flow on imx8ulpJacky Bai2023-03-291-12/+43
| | | | | | | Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
* ddr: imx8ulp: Change DRAM timing save area to 0x20055000Ye Li2023-03-291-1/+1
| | | | | | | | | To align with ARM trusted firmware's change, adjust DRAM timing save area to new position 0x20055000. So we can release the space since 0x2006c000 for the NOBITS region of ARM trusted firmware Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
* ddr: marvell: a38x: Remove unused file seq_exec.hPali Rohár2023-03-242-65/+0
| | | | | | DDR code does not use seq_exec.h, so remove it. Signed-off-by: Pali Rohár <pali@kernel.org>
* ddr: imx: Handle both 3733 and 3732 MTps ratesMarek Vasut2023-01-301-0/+1
| | | | | | | | The DDR calibration tool for i.MX8M currently produces 3732 MTps rate in lpddr4_timing.c , while the PHY code expects 3733 MTps rate. Support both variants to avoid surprises where the system fails to boot. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: marvell: a38x: Add support for DDR4 from Marvell mv-ddr-marvell repositoryTony Dinh2023-01-2627-0/+5991
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This syncs drivers/ddr/marvell/a38x/ with the master branch of repository https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git up to the commit "mv_ddr: a3700: Use the right size for memset to not overflow" d5acc10c287e40cc2feeb28710b92e45c93c702c This patch was created by following steps: 1. Replace all a38x files in U-Boot tree by files from upstream github Marvell mv-ddr-marvell repository. 2. Run following command to omit portions not relevant for a38x, ddr3, and ddr4: files=drivers/ddr/marvell/a38x/* unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_APN806 \ -UCONFIG_MC_STATIC -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \ -UCONFIG_PHY_STATIC_PRINT -UCONFIG_CUSTOMER_BOARD_SUPPORT \ -UCONFIG_A3700 -UA3900 -UA80X0 -UA70X0 -DCONFIG_ARMADA_38X -UCONFIG_ARMADA_39X \ -UCONFIG_64BIT $files 3. Manually change license to SPDX-License-Identifier (upstream license in upstream github repository contains long license texts and U-Boot is using just SPDX-License-Identifier. After applying this patch, a38x, ddr3, and ddr4 code in upstream Marvell github repository and in U-Boot would be fully identical. So in future applying above steps could be used to sync code again. The only change in this patch are: 1. Some fixes with include files. 2. Some function return and basic type defines changes in mv_ddr_plat.c (to correct Marvell bug). 3. Remove of dead code in newly copied files (as a result of the filter script stripping out everything other than a38x, dd3, and ddr4). Reference: "ddr: marvell: a38x: Sync code with Marvell mv-ddr-marvell repository" https://source.denx.de/u-boot/u-boot/-/commit/107c3391b95bcc2ba09a876da4fa0c31b6c1e460 Signed-off-by: Tony Dinh <mibodhi@gmail.com> Reviewed-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
* global: Finish CONFIG -> CFG migrationTom Rini2023-01-202-8/+8
| | | | | | | | | | | | | At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* global: Migrate CONFIG_MAX_MEM_MAPPED to CFGTom Rini2022-12-231-3/+3
| | | | | | Perform a simple rename of CONFIG_MAX_MEM_MAPPED to CFG_MAX_MEM_MAPPED Signed-off-by: Tom Rini <trini@konsulko.com>
* global: Remove undef CONFIG_... for unused valuesTom Rini2022-12-231-2/+0
| | | | | | | We have a number of places that undef CONFIG_... while we never reference CONFIG_... in the first place. Remove these lines. Signed-off-by: Tom Rini <trini@konsulko.com>
* ddr: fsl: Remove CONFIG_MEM_INIT_VALUETom Rini2022-12-222-16/+3
| | | | | | | | | | The way all of the memory init code here works is that we pass 0xDEADBEEF around for the initial value (as it's a well known 'poison' value and so easily recognized in debuggers, etc). The only point of this CONFIG symbol was to pass in a different value for that purpose. Drop this symbol and cleanup the code slightly. Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_SPD_EEPROM to KconfigTom Rini2022-12-051-0/+8
| | | | | | | | This converts the following to Kconfig: CONFIG_SPD_EEPROM Cc: Stefan Roese <sr@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com>
* global: Move remaining CONFIG_SYS_* to CFG_SYS_*Tom Rini2022-12-051-2/+2
| | | | | | | | | | The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_*Tom Rini2022-12-055-6/+6
| | | | | | | | | | The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespaceTom Rini2022-11-109-39/+39
| | | | | | | Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* global: Migrate CONFIG_SYS_MPC8* symbols to the CFG_SYS namespaceTom Rini2022-11-102-2/+2
| | | | | | Migrate all of COFIG_SYS_MPC* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com>
* treewide: Remove the unnecessary space before semicolonBin Meng2022-11-021-1/+1
| | | | | | %s/return ;/return; Signed-off-by: Bin Meng <bmeng@tinylab.org>
* imx8m: fix reading of DDR4 MR registers [again]Rasmus Villemoes2022-10-241-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | Commit 290ffe5788 (imx8m: fix reading of DDR4 MR registers) lifted a private definition of lpddr4_mr_read() from imx8mm-cl-iot-gate board code to drivers/ddr/imx/imx8m/ddrphy_utils.c, because that version actually seems to work in practice. However, commit 99c7cc58e1 (ddr: imx: Add i.MX9 DDR controller driver) reintroduced the broken version in drivers/ddr/imx/imx8m/ddr_init.c, copied most of the rest of ddrphy_utils.c to drivers/ddr/imx/phy/ddrphy_utils.c, and stopped building drivers/ddr/imx/imx8m/ddrphy_utils.c [and that file was then finally completely removed with 7e9bd84883 (imx8m: ddrphy_utils: Remove unused file)]. I assume this must have broken the imx8mm-cl-iot-gate board, at least those that have not had their eeprom programmed with the proper information. It certainly did break our out-of-tree board which always reads back the ID register and uses that for a sanity check. So apply the fix from 290ffe5788 once again. Fixes: 99c7cc58e1 (ddr: imx: Add i.MX9 DDR controller driver) Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Fabio Estevam <festevam@denx.de>
* ddr: fsl: Fix re-align of verbose DRAM information for non-SPL buildsPali Rohár2022-09-231-0/+3
| | | | | | | | During init_dram() is called also compute_lowest_common_dimm_parameters() function which prints multi-line detailed output. So print also re-aligning filler after "Detected ?DIMM" line to have "DRAM: " output aligned. Signed-off-by: Pali Rohár <pali@kernel.org>
* ddr: fsl: Allow to detect 4 GB DDR modules in 32-bit modePali Rohár2022-09-231-4/+10
| | | | | | | | | | | U-Boot core code already handles the case when RAM size is bigger than CONFIG_MAX_MEM_MAPPED. So there is no need to do duplicate check in fsl ddr driver for CONFIG_MAX_MEM_MAPPED. Instead simplify code to just check if RAM size can be representable in phys_size_t type. And avoid printing warning if phys_size_t is just 1 byte smaller than RAM size, which is the typical situation with 4 GB DDR module. Signed-off-by: Pali Rohár <pali@kernel.org>
* ddr: fsl: Fix fsl_ddr_sdram_size() for 4GB modules with 32-bit phys_size_tPali Rohár2022-09-231-0/+4
| | | | | | | | | | | | | | | | | Function fsl_ddr_compute() always return size in unsigned long long type, but function fsl_ddr_sdram_size() returns size in phys_size_t type. When 36-bit addressing mode is not enabled then phys_size_t type is only 32-bit and thus it cannot store value 4GB (0x100000000). Function fsl_ddr_sdram_size() in this case returns truncated value 0x0. Fix this issue by returning the highest representable value, which is 0xffffffff (4GB - 1 byte). This change fixes crashing of proper U-Boot because it detected 4 GB module as RAM with zero size. Signed-off-by: Pali Rohár <pali@kernel.org>
* ddr: fsl: Fix checking for maximal mappable memoryPali Rohár2022-09-231-5/+14
| | | | | | | | | Check needs to be done against CONFIG_MAX_MEM_MAPPED macro and not fixed size 4GB (as CONFIG_MAX_MEM_MAPPED can be lower and for example for e500 cores it is just 2GB). Also fix printf re-align, which should be applied only for non-SPL builds, during init_dram() call. Signed-off-by: Pali Rohár <pali@kernel.org>
* Merge branch 'master' into nextTom Rini2022-09-194-374/+5
|\ | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com>
| * imx8m: ddrphy_utils: Remove unused fileMarek Vasut2022-09-181-369/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ddrphy_utils.c is now deduplicated in drivers/ddr/imx/phy/ddrphy_utils.c , this drivers/ddr/imx/imx8m/ddrphy_utils.c is a remnant from when the deduplication was implemented and was not removed. Remove it as it is unused. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com> Reviewed-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
| * ddr: fsl: Make bank_addr_bits reflect actual bitsSean Anderson2022-09-062-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In both the Freescale DDR controller and the SPD spec, bank address bits are stored as the number of bank address bits minus 2. For example, if a chip had 8 banks (3 total bank address bits), the value of bank_addr_bits would be 1. This is rather surprising for users configuring their memory manually, since they can't set bank_addr_bits to the actual number of bank address bits. Rectify this. There is at least one example of this kind of mistake already, in board/freescale/t102xrdb/ddr.c. The documented MT40A512M8HX has two bank address bits, but bank_addr_bits was set to 2, implying 4 bank address bits. Such a value is reserved in BA_BITS_CS, but I suspect the controller simply ignores the top bit, making this kind of mistake harmless, if misleading. Fixes: e8a7f1c32b5 ("powerpc/t1023rdb: Add T1023 RDB board support") Signed-off-by: Sean Anderson <sean.anderson@seco.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * ddr: fsl: Reduce the size of interactive optionsSean Anderson2022-09-061-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The interactive mode uses large several tables of options which can be configured. However, much of the contents of these tables are repetetive. For example, no struct is larger than half a kilobyte, so the offset only takes up 9 bits. Similarly, the size is only ever 4 or 8, and printhex is a boolean. Reduce the size of these fields. This reduces the size of the options tables by around 10 KiB. However, the largest contributor to the size of the options tables is the use of a pointer for the strings. A better approach would be to use a separate array of strings, and store an integer index in the options tables. However, this would require a large re-architecting of this file. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | cyclic: Use schedule() instead of WATCHDOG_RESET()Stefan Roese2022-09-183-5/+5
|/ | | | | | | | | | Globally replace all occurances of WATCHDOG_RESET() with schedule(), which handles the HW_WATCHDOG functionality and the cyclic infrastructure. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm]
* Convert CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS et al to KconfigTom Rini2022-08-121-0/+7
| | | | | | | | | | | This converts the following to Kconfig: CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS And we remove the entries from the README for a number of already converted items. Signed-off-by: Tom Rini <trini@konsulko.com>
* common: Drop display_options.h from common headerSimon Glass2022-08-101-0/+1
| | | | | | Move this out of the common header and include it only where needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_SYS_FSL_DDR_INTLV_256B to KconfigTom Rini2022-08-041-0/+7
| | | | | | | This converts the following to Kconfig: CONFIG_SYS_FSL_DDR_INTLV_256B Signed-off-by: Tom Rini <trini@konsulko.com>
* ddr: imx8m: helper: load ddr firmware according to binman symbolsPeng Fan2022-07-261-6/+41
| | | | | | | | | | | | | By reading binman symbols, we no need hard coded IMEM_LEN/DMEM_LEN after we update the binman dtsi to drop 0x8000/0x4000 length for the firmware. And that could save binary size for many KBs. Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8m[m,n,p]-venice Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> [Alper: Check BINMAN_SYMS_OK instead] Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
* ddr: imx9: enable Performance monitor counterYe Li2022-07-262-0/+10
| | | | | | | | Add Kconfig for enabling reference events counter in DDRC performance monitor by default Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* ddr: imx: Add i.MX9 DDR controller driverYe Li2022-07-2613-23/+946
| | | | | | | | | | | | | Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* Convert CONFIG_SYS_DDR_RAW_TIMING to KconfigTom Rini2022-07-051-0/+7
| | | | | | | This converts the following to Kconfig: CONFIG_SYS_DDR_RAW_TIMING Signed-off-by: Tom Rini <trini@konsulko.com>
* Convert CONFIG_SYS_SPD_BUS_NUM to KconfigTom Rini2022-07-051-0/+5
| | | | | | | This converts the following to Kconfig: CONFIG_SYS_SPD_BUS_NUM Signed-off-by: Tom Rini <trini@konsulko.com>
* nxp: Cleanup some emulator related options.Tom Rini2022-07-051-0/+6
| | | | | | | | - Drop the emulator CONFIG test from include/configs/ls1088ardb.h - Migrate CONFIG_SYS_FSL_DDR_EMU to a select'able option in drivers/ddr/fsl/Kconfig Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' into nextTom Rini2022-06-204-7/+8
|\ | | | | | | Merge in v2022.07-rc5.
| * ddr: altera: soc64: Integer fix overflow that caused DDR size mismatchedDinesh Maniyam2022-06-171-2/+3
| | | | | | | | | | | | | | | | Convert the constant integer to 'phys_size_t' to avoid overflow when calculating the SDRAM size. Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
| * ddr: altera: Stratix10: Use phys_size_t for memory sizeTien Fong Chee2022-06-161-2/+2
| | | | | | | | | | | | | | | | Replace with phys_size_t for all memory size variables declaration for the sake of scalability. phys_size_t is defined in /arch/arm/include/asm/types.h. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
| * ddr: altera: Ignore bit[7-4] for both seq2core & core2seq handshake in HPSTien Fong Chee2022-06-161-1/+1
| | | | | | | | | | | | | | | | Bit[7-4] for both register seq2core and core2seq handshake in HPS are not required for triggering DDR re-calibration or resetting EMIF. So, ignoring these bits just for playing it safe. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
| * intel: n5x: ddr: update licenseTien Fong Chee2022-06-151-2/+2
| | | | | | | | | | | | | | | | All the source code of sdram_n5x.c are from Intel, update the license to use both GPL2.0 and BSD-3 Clause because this copy of code may used for open source and internal project. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
* | Convert CONFIG_SPL_COMMON_INIT_DDR to KconfigTom Rini2022-06-061-0/+14
|/ | | | | | | This converts the following to Kconfig: CONFIG_SPL_COMMON_INIT_DDR Signed-off-by: Tom Rini <trini@konsulko.com>
* imx8m: fix reading of DDR4 MR registersRasmus Villemoes2022-05-201-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I was trying to employ lpddr4_mr_read() to something similar to what the imx8mm-cl-iot-gate board is doing for auto-detecting the RAM type. However, the version in drivers/ddr/imx/imx8m/ddrphy_utils.c differs from the private one used by that board in how it extracts the byte value, and I was only getting zeroes. Adding a bit of debug printf'ing gives me tmp = 0x00ffff00 tmp = 0x00070700 tmp = 0x00000000 tmp = 0x00101000 and indeed I was expecting a (combined) value of 0xff070010 (0xff being Manufacturer ID for Micron). I can't find any documentation that says how the values are supposed to be read, but clearly the iot-gate definition is the right one, both for its use case as well as my imx8mp-based board. So lift the private definition of lpddr4_mr_read() from the imx8mm-cl-iot-gate board code to ddrphy_utils.c, and add a declaration in the ddr.h header where e.g. get_trained_CDD() is already declared. This has only been compile-tested for the imx8mm-cl-iot-gate board (since I don't have the hardware), but since I've merely moved its definition of lpddr4_mr_read(), I'd be surprised if it changed anything for that board. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Tested-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Reviewed-by: Fabio Estevam <festevam@denx.de>
* ddr: fsl: Allow to compile it without env supportPali Rohár2022-04-261-0/+4
| | | | | | | | | When env support is disabled then usage of env_get_f() generates linker errors. So do not compile env_get_f() when env support is disabled (for example when disabled only in SPL). Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* imx8m: ddrphy_utils: Add 3732 MT/s modeMarek Vasut2022-04-121-0/+4
| | | | | | | | | | | Add entry for 3732 MT/s mode of operation of the LPDDR4, in which case the DDR PLL has to be configured in 933 MHz mode. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <festevam@denx.de>
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