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| author | Tom Rini <trini@konsulko.com> | 2022-06-15 12:03:55 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-07-05 17:03:01 -0400 |
| commit | c24e8e2bb34da1fa17d19acf2b542dba5dfb7e47 (patch) | |
| tree | a57357ea1e5c3ddc9fdc7ec43ff079606218af86 /drivers/ddr | |
| parent | bca4509d575912e0521ce8448d41aabfc1c5e964 (diff) | |
Convert CONFIG_SYS_DDR_RAW_TIMING to Kconfig
This converts the following to Kconfig:
CONFIG_SYS_DDR_RAW_TIMING
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'drivers/ddr')
| -rw-r--r-- | drivers/ddr/fsl/Kconfig | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig index 6a29b23bab..d93ed8d2fe 100644 --- a/drivers/ddr/fsl/Kconfig +++ b/drivers/ddr/fsl/Kconfig @@ -175,6 +175,13 @@ config ECC_INIT_VIA_DDRCONTROLLER Use the DDR controller to auto initialize memory. If not enabled, the DMA controller is responsible for doing this. +config SYS_DDR_RAW_TIMING + bool "Get DDR timing information from something other than SPD" + help + This is common with soldered DDR chips onboard without SPD. DDR raw + timing parameters are extracted from datasheet and hard-coded into + header files or board specific files. + endif menu "PowerPC / M68K initial memory controller definitions (FLASH, SDRAM, etc)" |