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path: root/drivers/ddr/imx/phy
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* Merge tag 'v2024.01-rc5' into nextTom Rini2023-12-181-0/+5
|\ | | | | | | Prepare v2024.01-rc5
| * ddr: imx: Add 3600 MTps rate supportMarek Vasut2023-12-141-0/+4
| | | | | | | | | | | | | | | | Add PLL settings for DDR 3600 MTps . This is very similar to 3200 MTps PLL setting, except the divider is not 9 but 8 . Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
| * ddr: imx: Handle 3734 in addition to 3733 and 3732 MTps ratesMarek Vasut2023-12-141-0/+1
| | | | | | | | | | | | | | | | The new MX8M DDR tool 3.31 now generates a programming file which uses data rate 3734 instead of 3733 or 3732 . Handle another rounding option . Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
* | ddr: imx: Save the FW loading if it hasn't changedShawn Guo2023-12-131-0/+7
|/ | | | | | | | | | | Function ddr_load_train_firmware() is called 4 times in a loop by ddr_cfg_phy(). The first 3 calls are all '1D' type and just loading the same FWs. Let's add a type check and save 2 of them. This helps to reduce DDRPHY training time from 269 ms down to 212 ms, and thus speed up boot time ~ 50 ms. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Fabio Estevam <festevam@denx.de>
* treewide: unify the linker symbol reference formatShiji Yang2023-08-091-2/+2
| | | | | | | | | | | Now all linker symbols are declared as type char[]. Though we can reference the address via both the array name 'var' and its address '&var'. It's better to unify them to avoid confusing developers. This patch converts all '&var' linker symbol refrences to the most commonly used format 'var'. Signed-off-by: Shiji Yang <yangshiji66@outlook.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ddr: imx93: update the ddr init to support mult setpointsJacky Bai2023-05-211-2/+3
| | | | | | | | | | Update the DDR init flow for multi-setpoint support on i.MX93. A new fsp_cfg struct need to be added in the timing file to store the diff part of the DDRC and DRAM MR register for each setpoint. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* ddr: imx93: Add 625M bypass clock supportJacky Bai2023-05-211-0/+3
| | | | | | | | | Add 625M bypass clock that may be used DRAM 625M bypass mode support. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* ddr: imx: Handle both 3733 and 3732 MTps ratesMarek Vasut2023-01-301-0/+1
| | | | | | | | The DDR calibration tool for i.MX8M currently produces 3732 MTps rate in lpddr4_timing.c , while the PHY code expects 3733 MTps rate. Support both variants to avoid surprises where the system fails to boot. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: imx8m: helper: load ddr firmware according to binman symbolsPeng Fan2022-07-261-6/+41
| | | | | | | | | | | | | By reading binman symbols, we no need hard coded IMEM_LEN/DMEM_LEN after we update the binman dtsi to drop 0x8000/0x4000 length for the firmware. And that could save binary size for many KBs. Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8m[m,n,p]-venice Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> [Alper: Check BINMAN_SYMS_OK instead] Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
* ddr: imx: Add i.MX9 DDR controller driverYe Li2022-07-266-0/+1197
Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
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