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* riscv: dts: jh7110: Enable PLL node in SPLBo Gan2024-03-121-0/+4
| | | | | | | | | | Previously PLL node was missing from SPL dts. This caused BUS_ROOT to stay on OSC clock (24Mhz). As a result, all peripherals have to run at a much lower frequency, and loading from sdcard/emmc is slow. Thus, enabling PLL node in dts to fix this. Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* riscv: cpu: improve multi-letter extension detection in supports_extension()Conor Dooley2024-03-121-6/+16
| | | | | | | | | | | | | | | | | The first multi-letter extension after the single-letter extensions does not have to be preceded by an underscore, which could cause the parser to mistakenly find a single-letter extension after the start of the multi-letter portion of the string. Three letters precede multi-letter extensions (s, x & z), none of which are valid single-letter extensions. The dt-binding also allows multi-letter extensions starting with h, but no such extension have been frozen or ratified, and the unprivileged spec no longer uses "h" as a prefix for multi-letter hypervisor extensions, having moved to "sh" instead. For that reason, modify the parser to stop at s, x & z to prevent this overrun, ignoring h. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
* riscv: dts: jh7110: fix indentationLeon M. Busch-George2024-03-121-1/+1
| | | | | Signed-off-by: Leon M. Busch-George <leon@georgemail.eu> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* riscv: sifive: fu740: reduce DDR speed from 1866MT/s to 1600MT/sThomas Perrot2024-03-121-1/+1
| | | | | | | | | | | | | | | | | | It appears that there is some timing marginality either in the board layout or the SoC that results in occasional data corruption on some boards. We observed this issue on some of the new HiFive Unmatched RevB boards during volume production as well as some of the original HiFive Unmatched boards from 2021 in our possession. This means that there are other boards out there that might have the issue too. We have done some limited testing with DDR4 at 1600MT/s and faulty boards (failing at 1866MT/s) passed. We plan further testing after we procure a temperature chamber. Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* riscv: dts: starfive: add regulator deviceNam Cao2024-01-311-0/+5
| | | | | | | | Add the axp15060 regulator device. OpenSBI uses this device to perform board reset and shutdown. Signed-off-by: Nam Cao <namcao@linutronix.de> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* riscv: dts: jh7110: add power management unit controller nodeNam Cao2024-01-311-0/+6
| | | | | | | | | JH7110 has a power management unit controller node. Add this node. This device is used by OpenSBI during board reset/shutdown. Signed-off-by: Nam Cao <namcao@linutronix.de> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* riscv: sophgo: milkv_duo: initial support addedKongyang Liu2024-01-311-0/+4
| | | | | | | | | Add support for Sophgo's Milk-V Duo board, only minimal device tree and serial console are enabled, and it can boot via vendor first stage bootloader. Signed-off-by: Kongyang Liu <seashell11234455@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* riscv: dts: sophgo: add basic device tree for Milk-V Duo boardKongyang Liu2024-01-314-0/+249
| | | | | | | | | Import device tree from Linux kernel to add basic support for CPU, PLIC, UART and Timer. The name cv1800b in the filename represent the chip used on Milk-V Duo board. Signed-off-by: Kongyang Liu <seashell11234455@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* riscv: Support building with Clangkleines Filmröllchen2024-01-311-1/+1
| | | | | | | | The -ffixed-gp option of GCC has an exact equivalent of -ffixed-x3 in Clang. Signed-off-by: kleines Filmröllchen <filmroellchen@serenityos.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* cmd: sbi: add support for Debug Trigger ExtensionHeinrich Schuchardt2024-01-311-0/+1
| | | | | | | Detect and show if the SBI implements the Debug Trigger Extension. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* board: sifive: spl: Initialized the PWM setting in the SPL stageVincent Chen2024-01-311-0/+15
| | | | | | | | | | | | | LEDs and multiple fans can be controlled by SPL. This patch ensures that all fans have been enabled in the SPL stage. In addition, the LED's color will be set to yellow. Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Co-developed-by: Nylon Chen <nylon.chen@sifive.com> Signed-off-by: Nylon Chen <nylon.chen@sifive.com> Co-developed-by: Zong Li <zong.li@sifve.com> Signed-off-by: Zong Li <zong.li@sifve.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* riscv: separate .data and .text sections of EFI binariesHeinrich Schuchardt2024-01-293-23/+58
| | | | | | | EFI binaries should not contain sections that are both writable and executable. Separate the RX .text section from the RW .data section Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
* riscv: page align EFI binary sectionHeinrich Schuchardt2024-01-291-1/+1
| | | | | | | Change the alignment of the relocation code in EFI binaries to match page boundaries. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
* riscv: conflicting SPDX license linker scriptsHeinrich Schuchardt2024-01-292-6/+2
| | | | | | | | | | Fix conflicting SPDX license information in linker scripts introduced by commit 7215787c4ea4 ("SPDX: Convert single license tags to Linux Kernel style"). Fixes: 7215787c4ea4 ("SPDX: Convert single license tags to Linux Kernel style") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* riscv: add ACPI fields to global dataHeinrich Schuchardt2024-01-071-0/+6
| | | | | | | | Add fields for the location of ACPI tables to the global data. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* andes: cpu: Enable cache and TLB ECC supportLeo Yu-Chi Liang2023-12-272-1/+5
| | | | | | | | Andes CPU supports cache and TLB ECC. Enable them by default. Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
* andes: cpu: Enable memboost featureLeo Yu-Chi Liang2023-12-272-1/+14
| | | | | | | | Andes CPU has memboost feature including prefetch, write-around and non-blocking load. Enable them by default. Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
* andes: ae350: Implement cache switch via KconfigLeo Yu-Chi Liang2023-12-271-9/+16
| | | | | | | | Kconfig provides SYS_[I|D]CACHE_OFF config options to switch off caches. Provide the corresponding implementation to the options. Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
* andes: csr.h: Clean up CSR definitionLeo Yu-Chi Liang2023-12-272-12/+9
| | | | | Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
* riscv: Extend board compatible string with "qemu,mbv"Michal Simek2023-12-271-1/+1
| | | | | | | | Extend compatible string to match the latest change in dt binding. Fixes: 7576ab2facae ("riscv: Add support for AMD/Xilinx MicroBlaze V") Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* riscv: cache: support cache enable in SPL stageZong Li2023-12-271-0/+21
| | | | | | | | The power gating feature of pl2 should be enabled as early as possible, it would be better to put it in SPL stage. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* Merge patch series "Complete decoupling of bootm logic from commands"Tom Rini2023-12-213-10/+21
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Simon Glass <sjg@chromium.org> says: This series continues refactoring the bootm code to allow it to be used with CONFIG_COMMAND disabled. The OS-handling code is refactored and a new bootm_run() function is created to run through the bootm stages. This completes the work. A booti_go() function is created also, in case it proves useful, but at last for now standard boot does not use this. This is cmdd (part d of CMDLINE refactoring) It depends on dm/bootstda-working which depends on dm/cmdc-working
| * bootm: Adjust arguments of boot_os_fnSimon Glass2023-12-211-5/+6
| | | | | | | | | | | | | | | | | | | | Adjust boot_os_fn to use struct bootm_info instead of the separate argc, argv and image parameters. Update the handlers accordingly. Few of the functions make use of the arguments, so this improves code size slightly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
| * riscv: Add a reset_cpu() functionSimon Glass2023-12-212-5/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | The current do_reset() is called from a command context. Add a function which can be used from anywhere, as is done on ARM. Adjust do_reset() to call it. Note that reset_cpu() is normally provided by SYSRESET so make this declaration conditional on that being disabled. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Chanho Park <chanho61.park@samsung.com> Tested-by: Chanho Park <chanho61.park@samsung.com>
* | global: Rework architecture global_data.h to include <linux/types.h>Tom Rini2023-12-211-0/+1
| | | | | | | | | | | | | | | | | | In most cases, the architecture global data currently makes use of assorted linux types, but does not include <linux/types.h> to provide them. Add <linux/types.h> instead of relying on indirect inclusion. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* | Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-riscv ↵Tom Rini2023-12-184-0/+117
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | into next - VisionFive2: Enable CONFIG_SYSRESET - StarFive: Modify starfive timer driver - AMD/Xilinx: Add MicroBlaze V support - Unmatched: Migrate to text environment
| * | riscv: Add support for AMD/Xilinx MicroBlaze VMichal Simek2023-12-183-0/+112
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP. It is hardware compatible with classic MicroBlaze processor. The patch contains initial wiring and configuration for initial HW design with memory, cpu, interrupt controller, timers and uartlite console (interrupt controller is listed but U-Boot is not using it). Provided DT is just describing one configuration and should be taken only as example. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
| * | riscv: dts: jh7110: Add a gpio-restart nodeJaehoon Chung2023-12-181-0/+5
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add gpio-restart node to do reset. Before applied this patch, System Reset Extension doesn't appear with sbi command. OpenSBI 1.3 Machine: Vendor ID 489 Architecture ID 8000000000000007 Implementation ID 4210427 Extensions: sbi_set_timer sbi_console_putchar ...[snip]... IPI Extension RFENCE Extension Hart State Management Extension Performance Monitoring Unit Extension After applied this patch, System Reset Extension is supported from SBI. OpenSBI 1.3 Machine: Vendor ID 489 Architecture ID 8000000000000007 Implementation ID 4210427 Extensions: sbi_set_timer sbi_console_putchar ...[snip]... IPI Extension RFENCE Extension Hart State Management Extension System Reset Extension Performance Monitoring Unit Extension Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* | Merge tag 'v2024.01-rc5' into nextTom Rini2023-12-183-28/+29
|\ \ | |/ |/| | | Prepare v2024.01-rc5
| * riscv: binman: fix the load field formatRandolph2023-12-061-10/+4
| | | | | | | | | | | | | | Using /bits/ 64 prefix for 64 bits address Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * riscv: andes: Fix enable register settings of PLICSWYu Chien Peter Lin2023-12-061-18/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On 32-core platform, hart31 gets stuck at secondary_hart_loop as the corresponding enable bit is not set in enable_ipi(). We should program the next word (0x2f84) which is assigned as the enable register of hart31. It should be done in the same way when we invoke riscv_send_ipi() to trigger software interrupt on hart31. The following diagram shows the enable bits of the fixed PLICSW scheme. Pending regs: 0x1000 x---0---0---0---0------0---0 Pending hart ID: 0 1 2 3 ... 30 31 Interrupt ID: 0 1 2 3 4 ... 31 32 | | | | | | | Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0 | | | | | | | 0x2080 x---0---1---0---0-...--0---0---> hart1 | | | | | | | 0x2100 x---0---0---1---0-...--0---0---> hart2 | | | | | | | 0x2180 x---0---0---0---1-...--0---0---> hart3 . . . . . . . . . . . . . . . . . . . . . 0x2f00 x---0---0---0---0-...--1---0---> hart30 | | | | | | | 0x2f80 x---0---0---0---0-...--0---1---> hart31 <-------- word 0 -------><--- word 1 ---> This patch includes some cleanups to macros/functions. Fixes: ebf11273220a ("riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy") Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Randolph <randolph@andestech.com>
| * riscv: dts: jh7110: Add watchdog device tree nodeChanho Park2023-12-051-0/+10
| | | | | | | | | | | | | | Adds jh7110 watchdog device tree node. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* | riscv: io.h: Fix signatures of reads/writes functionsIgor Prusov2023-11-281-6/+12
| | | | | | | | | | | | | | | | | | Change type of address parameter from int* to volatile void* for {read,write}s{b,w,l}() functions and add const qualifier for reads. This is done to keep function signatures in sync with asm-generic/io.h and other platforms. Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
* | riscv: io.h: Add defines for reads/writes functionsIgor Prusov2023-11-281-0/+8
|/ | | | | | | Add defines for {read,write}s{b,w,l} functions to make asm-generic/io.h aware of them. Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
* riscv: dts: jh7110: Add rng device tree nodeChanho Park2023-11-021-0/+10
| | | | | | | Adds jh7110 trng device tree node. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* riscv: import read/write_relaxed functionsChanho Park2023-11-021-0/+45
| | | | | | | | This imports mmio functions from Linux's arch/riscv/include/asm/mmio.h to use read/write[b|w|l|q]_relaxed functions. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* riscv: allow resume after exceptionHeinrich Schuchardt2023-11-021-0/+13
| | | | | | | | | If CSRs like seed are readable by S-mode, may not be determinable by S-mode. For safe driver probing allow to resume via a longjmp after an exception. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* riscv: cpu: jh7110: Add gpio helper macrosChanho Park2023-11-021-0/+85
| | | | | | | | | | Add gpio.h header file that includes JH7110 helper macros. The file is imported from StarFive github[1] with small changes such as alignment. [1]: https://github.com/starfive-tech/u-boot Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* riscv: Weakly define invalidate_icache_range()Samuel Holland2023-11-021-1/+1
| | | | | | | | | Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a vendor-specific way to invalidate a portion of the instruction cache. Allow them to override invalidate_icache_range(). Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* riscv: Align the trap handler to 64 bytesSamuel Holland2023-11-021-1/+1
| | | | | | | | | | | This is required on CPUs which always operate in CLIC mode, such as the T-HEAD E906 and E907. Per the CLIC specification: "In this mode, the trap vector base address held in mtvec is constrained to be aligned on a 64-byte or larger power-of-two boundary." Reported-by: Madushan Nishantha <jlmadushan@gmail.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* riscv: Sort target configs alphabeticallySamuel Holland2023-11-021-9/+9
| | | | | | | Clean things up for the next time somebody adds a target. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* Kconfig: Remove all default n/no optionsMichal Simek2023-10-301-1/+0
| | | | | | | | | | | | Similar change was done by commit b4c2c151b14b ("Kconfig: Remove all default n/no options") and again sync is required. default n/no doesn't need to be specified. It is default option anyway. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com> # tegra Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Angelo Dureghello <angelo@kernel-space.org>
* riscv: Remove common.h usageTom Rini2023-10-2431-29/+8
| | | | | | | | We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
* sunxi: dts: arm: add T113s/D1 DT files from Linux-v6.6-rc6Andre Przywara2023-10-222-0/+942
| | | | | | | | | | | | | This copies in some devicetree files from the official Linux kernel tree, v6.6-rc6. It covers a board with the Allwinner T113s SoC, which shares many devices with its RISC-V sibling, the Allwinner D1(s). This is the reason for the core .dtsi files landing in the arch/riscv directory. We are only adjusting the include path to accommodate for the differences in the U-Boot build system. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
* riscv: Add Zbb support for building U-BootYu Chien Peter Lin2023-10-197-1/+392
| | | | | | | | | This patch adds ISA string to the -march to generate zbb instructions for U-Boot binaries, along with optimized string functions introduced from Linux kernel. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* riscv: dts: binman: add condition for opensbi os bootRandolph2023-10-191-0/+24
| | | | | | | | | | Add condition for OpenSBI OS boot mode, by default it is not enabled. By default, binman creates the output file u-boot.itb. If SPL_OPENSBI_OS_BOOT is enabled, linux.itb will be created after compilation instead of the default u-boot.itb. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* riscv: kconfig: introduce SPL_LOAD_FIT_OPENSBI_OS_BOOT symbolRandolph2023-10-191-0/+8
| | | | | | | | | | | | | | | | | | Introduce common Kconfig symbol for riscv architecture. This symbol SPL_LOAD_FIT_OPENSBI_OS_BOOT is like falcon mode on ARM, the Falcon boot is a shortcut boot method for SD/eMMC targets. It skips the loading the RAM version U-Boot. Instead, it will loads the FIT image and boots directly to Linux. When SPL_OPENSBI_OS_BOOT is enabled, linux.itb is created after compilation instead of the default u-boot.itb. It initialises memory with the U-Boot SPL at the first stage, just as a normal boot process does at the beginning. Instead of jumping to the U-Boot proper from OpenSBI before booting the Linux kernel, the RISC-V falcon mode process jumps directly to the Linux kernel to gain shorter booting time. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategyRandolph2023-10-191-13/+11
| | | | | | | | | | | | Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* riscv: binman: Fix compilation errorMayuresh Chitale2023-10-191-4/+10
| | | | | | | | | | | | | | | | | | | | Some platforms may not have any DDR memory below 4G and for such platforms the TEXT_BASE and LOAD addresses etc are all 64 bit addresses due to which the u-boot build fails with below error: u-boot/arch/riscv/dts/binman.dtsi:30.14-25 Value out of range for 32-bit array element u-boot/arch/riscv/dts/binman.dtsi:43.14-25 Value out of range for 32-bit array element u-boot/arch/riscv/dts/binman.dtsi:44.15-26 Value out of range for 32-bit array element FATAL ERROR: Syntax error parsing input tree Fix by setting the address-cells property to 2 and converting load addresses to 64 bit values. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* riscv: remove dram_init_banksize()Heinrich Schuchardt2023-10-191-16/+0
| | | | | | | | | | | | | | | | | Remove dram_init_banksize() on the architecture level. Limiting used RAM to under 4 GiB is only necessary for CPUs which have a DMA issue. SoC specific code already exists for FU540, FU740, JH7110. Not all RISC-V boards will have memory below 4 GiB. A weak implementation of dram_init_banksize() exists in common/board_f.c. See the discussion in https://lore.kernel.org/u-boot/545fe813-cb1e-469c-a131-0025c77aeaa2@canonical.com/T/ Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Anup Patel <anup@brainfault.org>
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