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* mips: fix change_k0_cca()Daniel Schwierzeck2024-03-131-2/+2
| | | | | | | | | | | | | | | | | | | The intention of change_k0_cca() is to read the C0.Config register into register $t0, update $t0 with the new cache coherency mode passed in $a0 and write back $t0 to C0.Config. With MIPS32 R2 or later instruction sets, this can be achieved with a single instruction with INS. The source and destination register of the INS instruction is passed as first parameter. In case of change_k0_cca() it is register $t0. But for writing back the updated value to C0.Config, the incorrect $a0 register is used. This is only correct in the MIPS32 R1 code path. Fix the `mtc0` instruction to write back the value of the $t0 register. Fix the MIPS32 R1 code path to also store the updated value in $t0. Reported by user ddqxy138 on Github. https://github.com/u-boot/u-boot/commit/b838586086af3278bcaead3720c7a18813cf4619 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* mips: implement __udivdi3Linus Walleij2024-03-132-1/+18
| | | | | | | | | | | Squashfs wasn't compiling because the lldiv() directives turn into __udivdi3 and we are using private libgcc. After this squashfs compiles for MIPS. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Tested-by: Bartel Eerdekens <barteleerdekens@gmail.com>
* bootm: Rename do_bootm_states() to bootm_run_states()Simon Glass2023-12-211-1/+1
| | | | | | | | | Rename the function to bootm_run_states() to better indicate ts purpose. The 'do_' prefix is used to indicate a command processor, which this is now not. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* bootm: Adjust arguments of boot_os_fnSimon Glass2023-12-211-2/+4
| | | | | | | | | | Adjust boot_os_fn to use struct bootm_info instead of the separate argc, argv and image parameters. Update the handlers accordingly. Few of the functions make use of the arguments, so this improves code size slightly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* boot: Drop size parameter from image_setup_libfdt()Simon Glass2023-12-131-2/+2
| | | | | | | The of_size parameter is not used, so remove it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* mips: Remove common.h usageTom Rini2023-10-247-7/+2
| | | | | | | We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com>
* treewide: unify the linker symbol reference formatShiji Yang2023-08-091-1/+1
| | | | | | | | | | | Now all linker symbols are declared as type char[]. Though we can reference the address via both the array name 'var' and its address '&var'. It's better to unify them to avoid confusing developers. This patch converts all '&var' linker symbol refrences to the most commonly used format 'var'. Signed-off-by: Shiji Yang <yangshiji66@outlook.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* Correct SPL uses of BOOTSTAGE_REPORTSimon Glass2023-02-091-1/+1
| | | | | | | This converts 2 usages of this option to the non-SPL form, since there is no SPL_BOOTSTAGE_REPORT defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org>
* Correct SPL use of BOOTSTAGE_FDTSimon Glass2023-02-091-1/+1
| | | | | | | This converts 1 usage of this option to the non-SPL form, since there is no SPL_BOOTSTAGE_FDT defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org>
* global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_*Tom Rini2022-12-051-1/+1
| | | | | | | | | | The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* treewide: Drop bootm_headers_t typedefSimon Glass2022-09-291-8/+8
| | | | | | This is not needed and we should avoid typedefs. Use the struct instead. Signed-off-by: Simon Glass <sjg@chromium.org>
* mips: add support for noncached_alloc()Weijie Gao2022-07-131-0/+43
| | | | | | | | | | | | | | This patch adds support for noncached_alloc() which was only supported by ARM platform. Unlike the ARM platform, MMU is not used in u-boot for MIPS. Instead, KSEG is provided to access uncached memory. So most code of this patch is copied from cache.c of ARM platform, with only two differences: 1. MMU is untouched in noncached_set_region() 2. Address returned by noncached_alloc() is converted using KSEG1ADDR() Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
* mips: Avoid using config_enabled() directlySimon Glass2022-02-081-1/+1
| | | | | | | Use IS_ENABLED() instead, which is the correct macro for checking a CONFIG option. Signed-off-by: Simon Glass <sjg@chromium.org>
* lmb: Switch to generic arch_lmb_reserve_generic()Marek Vasut2021-09-231-8/+1
| | | | | | | | | | | | | | | | | Switch arc/arm/m68k/microblaze/mips/ppc arch_lmb_reserve() to arch_lmb_reserve_generic(). Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Alexey Brodkin <alexey.brodkin@synopsys.com> Cc: Angelo Dureghello <angelo@sysam.it> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Cc: Hai Pham <hai.pham.ud@renesas.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tom Rini <trini@konsulko.com> Cc: Wolfgang Denk <wd@denx.de>
* common: Drop asm/global_data.h from common headerSimon Glass2021-02-025-0/+5
| | | | | | | | | | | | Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* common: board_r: Drop arch-specific ifdefs around initr_trapOvidiu Panait2021-01-151-1/+8
| | | | | | | | | | | | In order to remove the arch-specific ifdefs around initr_trap, introduce arch_initr_trap weak initcall. Implementations for ppc/m68k/mips have been moved to arch/<arch>/lib/traps.c Default implementation is a nop stub. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* global: Move from bi_memstart/memsize -> gd->ram_base/ram_sizeStefan Roese2020-08-262-2/+2
| | | | | | | | | With the planned removal of bi_memstart & bi_memsize, this patch now moves the references to the better suiting gd->ram_base/ram_size variables. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* mips: sync asm/mipsregs.h with Linux 5.7Daniel Schwierzeck2020-07-181-1/+1
| | | | | | | | | | Sync asm/mipsregs.h with Linux 5.7. Also replace the custom symbols EBASE_CPUNUM and EBASE_WG with the according symbols from Linux. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
* mips: remove deprecated UNCACHED_SDRAM() macroDaniel Schwierzeck2020-07-181-2/+2
| | | | | | | | | | | | This macro only served as a wrapper for CKSEG1ADDR() with an exception for CONFIG_TB0229. CONFIG_TB0229 doesn't exist, thus use CKSEG1ADDR() directly. This also prepares for an upcoming asm header sync with Linux. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
* mips: refactor disabling of cachesDaniel Schwierzeck2020-07-181-0/+6
| | | | | | | | | | | Logically this code belongs to cache_init.S. If a complex SoC needs to replace the generic cache init, mips_cache_disable() can now be called from custom start.S files. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
* mips: add KSEG1 wrapper for change_k0_ccaDaniel Schwierzeck2020-07-181-14/+18
| | | | | | | | | | | change_k0_cca() is called multiple times. Move the code for changing to KSEG1 to a macro to avoid code duplication. Also fix missing change to KSEG1 when changing to CONF_CM_CACHABLE_COW. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
* mips: cache: Make invalidate_dcache_range() weak to enable overwriteStefan Roese2020-07-181-1/+1
| | | | | | | | This patch adds __weak to invalidate_dcache_range() in lib/cache.c. This makes it possible to overwrite this function by a platforms specific version, which will be done for Octeon. Signed-off-by: Stefan Roese <sr@denx.de>
* mips: cache: Make flush_cache() weak to enable overwriteStefan Roese2020-07-181-1/+1
| | | | | | | | This patch adds __weak to flush_cache() in lib/cache.c. This makes it possible to overwrite this function by a platforms specific version, like done with the Octeon base port. Signed-off-by: Stefan Roese <sr@denx.de>
* mips: cache: Allow using CONFIG_MIPS_L2_CACHE without CONFIG_MIPS_CMStefan Roese2020-07-181-2/+0
| | | | | | | | This patch enables the usage of CONFIG_MIPS_L2_CACHE without CONFIG_MIPS_CM, which is what is needed for the newly added Octeon platform. Signed-off-by: Stefan Roese <sr@denx.de>
* mips: reloc: Change R_MIPS_NONE to catch pre-reloc BSS usageStefan Roese2020-07-181-3/+4
| | | | | | | | | | | | | | | | | | | | This patch changes the R_MIPS_NONE define from 0 to a magic value. This makes it possible to better detect any forbidden pre-relocation usage of BSS variables, as they are often zero'ed and then relocation is stopped too early. Additionally the error message is improved to also print the faulting address. This helps finding the root-cause for this breakage by comparing this address with the values in System.map. This patch helps a lot when working on pre-relocation code, like the Octeon DDR init code, where such variables have hit me multiple times now. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
* mips: traps: Set WG bit in EBase register on OcteonStefan Roese2020-07-181-0/+4
| | | | | | | WG (bit 11) needs to be set on Octeon to enable writing bits 63:30 of the exception base register. Signed-off-by: Stefan Roese <sr@denx.de>
* common: Drop linux/bitops.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop linux/bug.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop asm/ptrace.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop log.h from common headerSimon Glass2020-05-184-0/+4
| | | | | | Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* command: Remove the cmd_tbl_t typedefSimon Glass2020-05-181-2/+2
| | | | | | | | | | | | | We should not use typedefs in U-Boot. They cannot be used as forward declarations which means that header files must include the full header to access them. Drop the typedef and rename the struct to remove the _s suffix which is now not useful. This requires quite a few header-file additions. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop init.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop image.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop bootstage.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this fairly uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop net.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | | | | | | Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
* mips: spl: Flush cache before jumping to U-Boot properStefan Roese2020-04-272-0/+22
| | | | | | | | | | | | | | | This patch adds a MIPS specific jump_to_image_no_args() implementation, which flushes the U-Boot proper image loaded from the boot device in SPL before jumping to it. It has been noticed on MT76x8, that this cache flush is needed. Other MIPS platforms might need it as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Weijie Gao <weijie.gao@mediatek.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* mips: add support to restore exception vector base before booting linuxWeijie Gao2020-04-272-0/+22
| | | | | | | | | | | | | | In U-Boot the exception vector base will be moved to top of memory, to be used to display register dump when exception occurs. But some old linux kernel does not honor the base set in CP0_EBASE. A modified exception vector base will cause kernel crash. This patch adds an option to enable reset exception vector base to its previous value, or a user configured value before booting linux kernel. Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
* mips: cmd: go: Flush cache before jumping to app/imageStefan Roese2020-04-092-0/+24
| | | | | | | | | | | | | | | | | | | It has been noticed on MT7628/88 platforms, that booting the RAM image does not work reliably. Sometimes it works and sometimes not. Debugging showed that this "might" be a cache related issue as very strange errors occurred (e.g. output corrupted etc). This patch adds a cache flush for the complete SDRAM area to the go cmd before jumping to the entry point for the MIPS architecture. The complete area is flushed as we don't know at this point, how big the area of the "application" really is. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Tested-by: Mauro Condarelli <mc5686@mclink.it> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Mauro Condarelli <mc5686@mclink.it> Cc: Weijie Gao <weijie.gao@mediatek.com>
* MIPS: allow override of flush_dcache_range()Alex Nemirovsky2020-04-091-1/+1
| | | | | | | Useful in custom HW designs which have a need to flush dcache range in a completely non standard way. Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
* common: Move hang() to the same header as panic()Simon Glass2020-01-171-0/+1
| | | | | | | | | | At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com>
* common: Move relocate_code() to init.hSimon Glass2020-01-171-0/+1
| | | | | | | | | This is an init function so move it out of the common header. Avoid using the typedef so that we don't have to include the global_data header file. Also tidy up the function style in comments while we are here. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Move trap_init() out of common.hSimon Glass2019-12-021-0/+1
| | | | | | | | Move this function into the init.h header file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* common: Move ARM cache operations out of common.hSimon Glass2019-12-022-0/+2
| | | | | | | | | These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* common: Move some cache and MMU functions out of common.hSimon Glass2019-12-021-0/+1
| | | | | | | | | | | | These functions belong in cpu_func.h. Another option would be cache.h but that code uses driver model and we have not moved these cache functions to use driver model. Since they are CPU-related it seems reasonable to put them here. Move them over. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* MIPS: add compile time definition of L2 cache sizeRamon Fried2019-10-251-1/+1
| | | | | | | | | | If configuration is set to skip low level init, automatic probe of L2 cache size is not performed and the size is set to 0. Flushing or invalidating the L2 cache will fail in this case. Add a static configuration (SYS_DCACHE_LINE_SIZE) with default set to 0. Signed-off-by: Ramon Fried <rfried.dev@gmail.com>
* env: Move env_init() to env.hSimon Glass2019-08-111-0/+1
| | | | | | | Move env_init() over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* arch: mips: Update initrd_start and initrd_endHoratiu Vultur2019-05-031-0/+2
| | | | | | | | | | | | | | | | | Microsemi SoC defines CONFIG_SYS_SDRAM_BASE to be 0x80000000, which represents the start of kseg0 and represents a virtual address. Meaning that the initrd_start and initrd_end point somewhere kseg0. When these parameters are passed to linux kernel through DT they are pointing somewhere in kseg0 which is a virtual address but linux kernel expects the addresses to be physical addresses(in kuseg) because it is converting the physical address to a virtual one. Therefore update the uboot to pass the physical address of initrd_start and initrd_end by converting them using the function virt_to_phys before setting up the DT. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* bootm: mips: Remove boot_reloc_ramdiskHoratiu Vultur2019-04-121-19/+0
| | | | | | | | | | | | | Remove the function boot_reloc_ramdisk in the file arch/mips/lib/bootm because it is relocating again the ramdisk. The function do_bootm_states() already relocates the ramdisk even if it is a legacy uImage or a FIT image. The relocation in the function do_bootm_states() was introduce in the commit c2e7e72bb9f0cb47d024997b381cb64786eb5402 ("bootm: relocate ramdisk if CONFIG_SYS_BOOT_RAMDISK_HIGH set") Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: cache: remove config option CONFIG_SYS_MIPS_CACHE_MODEDaniel Schwierzeck2018-09-221-5/+1
| | | | | | | | Caches should be configured to mode CONF_CM_CACHABLE_NONCOHERENT (or CONF_CM_CACHABLE_COW when a CM is available). There is no need to make this configurable. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: cache: make index base address configurableDaniel Schwierzeck2018-09-221-10/+8
| | | | | | | | The index base address used for the cache initialisation is currently hard-coded to CKSEG0. Make this value configurable if a MIPS system needs to have a different address (e.g. in SRAM or ScratchPad RAM). Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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