u-boot.git - "Das U-Boot" Source Tree

	Commit message (Collapse)	Author	Age	Files	Lines
*	ddr: altera: Add SDRAM driver for Intel N5X device	Tien Fong Chee	2021-08-25	1	-0/+6
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	The DDR subsystem in Diamond Mesa is consisted of controller, PHY, memory reset manager and memory clock manager. Configuration settings of controller, PHY and memory reset manager is come from DDR handoff data in bitstream, which contain the register base addresses and user settings from tool. Configuration settings of memory clock manager is come from the HPS handoff data in bitstream, however the register base address is defined in device tree. The calibration is fully done in HPS, which requires IMEM and DMEM binaries loading to PHY SRAM for running this calibration, both IMEM and DMEM binaries are also part of bitstream, this bitstream would be loaded to OCRAM by SDM, and configured by DDR driver. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
*	common: Drop linux/bitops.h from common header	Simon Glass	2020-05-18	1	-0/+2
\| \| \| \| \| \|	Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
*	arm: socfpga: stratix10: Enable SMMU access	Thor Thayer	2020-01-07	1	-0/+7
\| \| \| \| \| \| \| \|	Enable TCU access through the Stratix10 CCU so that the SMMU can access the SDRAM. Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
*	arm: socfpga: Move firewall code to firewall file	Ley Foon Tan	2020-01-07	1	-0/+122
	Move firewall related code to new firewall.c, to share code in Stratix 10 and Agilex. SDMMC will transfer data to OCRAM in SPL. So, enable privilege for SDMMC to allow DMA transfer to OCRAM. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>