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* arm: spl: Use separate fault handlers instead of a single common oneCsókás Bence2024-01-111-0/+18
| | | | | | | It may be necessary to set breakpoints etc. on a specific fault handler in SPL. Add a Kconfig option to separate the different handlers into their own individual infinite loops. Signed-off-by: Csókás Bence <csokas.bence@prolan.hu>
* bootm: Adjust arguments of boot_os_fnSimon Glass2023-12-211-2/+4
| | | | | | | | | | Adjust boot_os_fn to use struct bootm_info instead of the separate argc, argv and image parameters. Update the handlers accordingly. Few of the functions make use of the arguments, so this improves code size slightly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: semihosting: Support semihosting fallback on 32-bit ARMSean Anderson2023-11-102-0/+38
| | | | | | | | | Add support for a semihosting fallback on 32-bit ARM. The assembly is lightly adapted from the irq return code, except there is no offset since lr already points to the correct instruction. The C side is mostly like ARM64, except we have fewer cases to deal with. Signed-off-by: Sean Anderson <sean.anderson@seco.com>
* arm: semihosting: Fix returning from traps on ARMv6 and lowerSean Anderson2023-11-101-0/+6
| | | | | | | | | | | | U-Boot runs in supervisor mode. On ARMv6 and lower, software interrupts are taken in supervisor mode. When entering an interrupt, the link register is set to the address of the next instruction. However, if we are already in supervisor mode, this clobbers the link register. The debugger can't help us, since by the time it notices we've taken a software interrupt, the link register is already gone. Work around this by moving the return address to another register. Signed-off-by: Sean Anderson <sean.anderson@seco.com>
* arm: Fix software interrupt handlerSean Anderson2023-11-101-1/+13
| | | | | | | | | | | When we take a software interrupt, we are already in supervisor mode. get_bad_stack assumes we are not in supervisor mode so it can clobber the stack pointer. This causes us to have an invalid stack once that macro finishes. Revert back to the get_bad_stack_swi macro which was previously removed. Fixes: 41623c91b09 ("arm: move exception handling out of start.S files") Signed-off-by: Sean Anderson <sean.anderson@seco.com>
* spl: Use SYS_MALLOC_F instead of SYS_MALLOC_F_LENSimon Glass2023-10-061-1/+1
| | | | | | | | Use the new SPL/TPL/VPL_SYS_MALLOC_F symbols to determine whether the malloc pool exists. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Sean Anderson <sean.anderson@seco.com>
* common: Drop linux/printk.h from common headerSimon Glass2023-09-241-0/+1
| | | | | | | | | This old patch was marked as deferred. Bring it back to life, to continue towards the removal of common.h Move this out of the common header and include it only where needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge tag 'v2023.10-rc3' into nextTom Rini2023-08-211-0/+16
|\ | | | | | | | | | | Prepare v2023.10-rc3 Signed-off-by: Tom Rini <trini@konsulko.com>
| * arm64: smccc: add support for SMCCCv1.2 x0-x17 registersAbdellatif El Khlifi2023-08-081-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add support for x0-x17 registers used by the SMC calls In SMCCC v1.2 [1] arguments are passed in registers x1-x17. Results are returned in x0-x17. This work is inspired from the following kernel commit: arm64: smccc: Add support for SMCCCv1.2 extended input/output registers [1]: https://documentation-service.arm.com/static/5f8edaeff86e16515cdbe4c6?token= Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
* | arm: Use builtins for ffs/flsSean Anderson2023-08-172-0/+50
|/ | | | | | | | | | | | | | | Since ARMv5, the clz instruction allows for efficient implementation of ffs/fls with builtins. Until ARMv7 (with Thumb-2), this instruction is only available in ARM mode. LTO makes it difficult to force specific functions to be in ARM mode, as it is effectively a form of very aggressive inlining. To work around this, fls/ffs are implemented in assembly for ARMv5 and ARMv6 when compiling U-Boot in Thumb mode. Overall, this saves around 75 bytes per call. This code is synced with v5.15 of the Linux kernel. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* Revert "Merge branch '2023-07-24-introduce-FF-A-suppport'"Tom Rini2023-07-241-16/+0
| | | | | | | | | This reverts commit d927d1a80843e1c3e2a3f0b8f6150790bef83da1, reversing changes made to c07ad9520c6190070513016fdb495d4703a4a853. These changes do not pass CI currently. Signed-off-by: Tom Rini <trini@konsulko.com>
* arm64: smccc: add support for SMCCCv1.2 x0-x17 registersAbdellatif El Khlifi2023-07-241-0/+16
| | | | | | | | | | | | | | | | | | | add support for x0-x17 registers used by the SMC calls In SMCCC v1.2 [1] arguments are passed in registers x1-x17. Results are returned in x0-x17. This work is inspired from the following kernel commit: arm64: smccc: Add support for SMCCCv1.2 extended input/output registers [1]: https://documentation-service.arm.com/static/5f8edaeff86e16515cdbe4c6?token= Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
* arm64: interrupts: print FAR_ELx on sync exceptionsPavel Skripkin2023-04-251-1/+37
| | | | | | | | | | | | | | | Default synchronous exceptions handler prints only esr and register dump. Sometimes it requiers to see an address which caused exceptions to understand what's going on ARM ARM in section D13.2.41 states that FAR_EL2 will contain meanfull value in case of ESR.EC holds 0x20, 0x21, 0x24, 0x25, 0x22, 0x34 or 0x35. Same applies for EL1. This patch adds function whivh determine current EL, gets correct FAR register and prints it on panic. Signed-off-by: Pavel Skripkin <paskripkin@gmail.com>
* arm: lib: add __gnu_thumb1_case_siFrancis Laniel2023-04-061-0/+17
| | | | | | | | | | | The assembly for __gnu_thumb1_case_si was taken from upstream gcc and adapted as width suffix was removed for the add instruction [1]. Signed-off-by: Francis Laniel <francis.laniel@amarulasolutions.com> Tested-by: Tony Dinh <mibodhi@gmail.com> [1] https://github.com/gcc-mirror/gcc/blob/4f181f9c7ee3efc509d185fdfda33be9018f1611/libgcc/config/arm/lib1funcs.S#L2156 Acked-by: Pali Rohár <pali@kernel.org> Acked-by: Tony Dinh <mibodhi@gmail.com>
* Merge branch 'master' into nextTom Rini2023-03-271-2/+2
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| * console: Use flush() before panic and resetTony Dinh2023-03-221-2/+2
| | | | | | | | | | | | | | | | | | | | | | To make sure the panic and the reset messages will go out, console flush() should be used. Sleep periods do not work in early u-boot phase when timer driver is not initialized yet. Reference: https://lists.denx.de/pipermail/u-boot/2023-March/512233.html Signed-off-by: Tony Dinh <mibodhi@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
* | arm: semihosting: replace inline assembly with assembly fileAndre Przywara2023-03-062-47/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far we used inline assembly to inject the actual instruction that triggers the semihosting service. While this sounds elegant, as it's really only about one instruction, it has some serious downsides: - We need some barriers in place to force the compiler to issue writes to a data structure before issuing the trap instruction. - We need to convince the compiler to actually fill the structures that we use pointers to. - We need a memory clobber to avoid the compiler caching the data in those structures, when semihosting writes data back. - We need register arguments to make sure the function ID and the pointer land in the right registers. This is all doable, but fragile and somewhat cumbersome. Since we now have a separate function in an extra file anyway, we can do away with all the magic and just write that in an actual assembly file. This is much more readable and robust. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Sean Anderson <sean.anderson@seco.com>
* | arm64: Initialize TLB memory if CMO_BY_VA_ONLYPierre-Clément Tosi2023-03-061-0/+9
|/ | | | | | | | | | | | | | | | Memory used to hold the page tables is allocated from the top of RAM with no prior initialization and could therefore hold invalid data. As invalidate_dcache_all() will be called before the MMU has been initialized and as that function relies indirectly on the page tables when using CMO_BY_VA_ONLY, these must be in a valid state from their allocation. Signed-off-by: Pierre-Clément Tosi <ptosi@google.com> [ Paul: pick from the Android tree. Fix checkpatch warnings, and rebased to the upstream. ] Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: Tom Rini <trini@konsulko.com> Link: https://android.googlesource.com/platform/external/u-boot/+/e3ceef4230b772186c6853cace4a676a407e6ab7
* Correct SPL uses of SAVE_PREV_BL_INITRAMFS_START_ADDRSimon Glass2023-02-101-1/+1
| | | | | | | This converts 2 usages of this option to the non-SPL form, since there is no SPL_SAVE_PREV_BL_INITRAMFS_START_ADDR defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org>
* Correct SPL uses of SAVE_PREV_BL_FDT_ADDRSimon Glass2023-02-101-1/+1
| | | | | | | This converts 2 usages of this option to the non-SPL form, since there is no SPL_SAVE_PREV_BL_FDT_ADDR defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org>
* Correct SPL uses of LMBSimon Glass2023-02-101-1/+1
| | | | | | | This converts 9 usages of this option to the non-SPL form, since there is no SPL_LMB defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org>
* arm: Drop CONFIG_MMUSimon Glass2023-02-071-21/+0
| | | | | | This option does not exist, so the #ifdefs do nothing. Drop this code. Signed-off-by: Simon Glass <sjg@chromium.org>
* arm: lib1funcs.S: Update compatibility with Linux comment slightlyTom Rini2023-01-201-7/+2
| | | | | | | | | At this point, the Linux code for "lib1funcs" has changed rather dramatically. While a resync would be beneficial, it's outside the scope of what we need here. Simply remove the define for CONFIG_AEABI and tests for it. Signed-off-by: Tom Rini <trini@konsulko.com>
* efi_loader: add .rela sections to .text on arm64Heinrich Schuchardt2023-01-131-4/+4
| | | | | | | | _relocate() needs the information in .rela* for self relocation of the EFI binary. Fixes: d7ddeb66a6ce ("efi_loader: fix building aarch64 EFI binaries") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
* Merge branch 'next'Tom Rini2023-01-096-35/+7
|\ | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com>
| * Merge tag 'v2023.01-rc4' into nextTom Rini2022-12-211-180/+1
| |\ | | | | | | | | | | | | | | | Prepare v2023.01-rc4 Signed-off-by: Tom Rini <trini@konsulko.com>
| * | arm: Use the WEAK assembly entry point consistentlyTom Rini2022-12-061-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is a bad idea, and more modern toolchains will fail, if you declare an assembly function to be global and then weak, instead of declaring it weak to start with. Update assorted assembly files to use the WEAK macro directly. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Pali Rohár <pali@kernel.org>
| * | arm: Remove unused mx27 codeTom Rini2022-12-051-28/+1
| | | | | | | | | | | | | | | | | | | | | We no longer have any i.MX27 platforms, remove the remaining support code. Signed-off-by: Tom Rini <trini@konsulko.com>
| * | global: Move remaining CONFIG_SYS_* to CFG_SYS_*Tom Rini2022-12-054-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | efi_loader: make .data section of *_efi.so files RWHeinrich Schuchardt2023-01-061-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When building with binutils 2.39 warnings *_efi.so has a LOAD segment with RWX permissions occur. Use SHF_WRITE | SHF_ALLOC as section flags for the .data section. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
* | | efi_loader: fix building aarch64 EFI binariesHeinrich Schuchardt2023-01-042-15/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While our EFI binaries execute without problems on EDK II they crash on a Lenovo X13s. Let our binaries look more like what EDK II produces: * move all writable data to a .data section * align sections to 4 KiB boundaries (matching EFI page size) * remove IMAGE_SCN_LNK_NRELOC_OVFL from .reloc section flags Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
* | | efi_loader: set IMAGE_FILE_LARGE_ADDRESS_AWAREHeinrich Schuchardt2022-12-291-0/+1
| |/ |/| | | | | | | | | | | | | For the 64bit EFI binaries that we create set the IMAGE_FILE_LARGE_ADDRESS_AWARE characteristic in the PE-COFF header to indicate that they can handle addresses above 2 GiB. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
* | lib: Add common semihosting libraryKautuk Consul2022-12-081-180/+1
|/ | | | | | | | | We factor out the arch-independent parts of the ARM semihosting implementation as a common library so that it can be shared with RISC-V. Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* arm32: Fix relocation of env_addr if POSITION_INDEPENDENT=yPali Rohár2022-11-211-0/+5
| | | | | | | | | | | | | | | | | | Apply commit 534f0fbd6520 ("arm64: Fix relocation of env_addr if POSITION_INDEPENDENT=y") also for 32-bit ARM. This change fixes crashing of U-Boot on ARMv7 (Omap3 / Cortex-A8) Nokia N900 phone (real HW). Note that qemu emulator of this board with same u-boot.bin binary has not triggered this crash. Crash happened after U-Boot printed following debug lines to serial console: initcall: 0001ea8c (relocated to 8fe0aa8c) Loading Environment from <NULL>... Using default environment Destroy Hash Table: 8fe25a98 table = 00000000 Create Hash Table: N=387 Signed-off-by: Pali Rohár <pali@kernel.org>
* arm: smh: Allow semihosting trap calls to be inlinedAndre Przywara2022-11-021-2/+3
| | | | | | | | | | | | | | | Currently our semihosting trap function is somewhat fragile: we rely on the current compiler behaviour to assign the second inline assembly argument to the next free register (r1/x1), which happens to be the "addr" argument to the smh_trap() function (per the calling convention). I guess this is also the reason for the noinline attribute. Make it explicit what we want: the "addr" argument needs to go into r1, so we add another register variable. This allows to drop the "noinline" attribute, so now the compiler beautifully inlines just the trap instruction directly into the calling function. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* arm: smh: Make semihosting trap calls more robustAndre Przywara2022-11-021-1/+15
| | | | | | | | | | | | | | | | | | Commit f4b540e25c5c("arm: smh: Fix uninitialized parameters with newer GCCs") added a memory clobber to the semihosting inline assembly trap calls, to avoid too eager GCC optimisation: when passing a pointer, newer compilers couldn't be bothered to actually fill in the structure that it pointed to, as this data would seemingly never be used (at least from the compiler's point of view). But instead of the memory clobber we need to tell the compiler that we are passing an *array* instead of some generic pointer, this forces the compiler to actually populate the data structure. This involves some rather hideous cast, which is best hidden in a macro. But regardless of that, we actually need the memory clobber, but for two different reasons: explain them in comments. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* arm: smh: specify Thumb trap instructionAndre Przywara2022-11-021-13/+16
| | | | | | | | | | | | | | | | | | | | | | The ARM semihosting interface uses different trap instructions for different architectures and instruction sets. So far we were using AArch64 and ARMv7-M, and had an untested v7-A entry. The latter does not work when building for Thumb, as can be verified by using qemu_arm_defconfig, then enabling SEMIHOSTING and SYS_THUMB_BUILD: ========== {standard input}:35: Error: invalid swi expression {standard input}:35: Error: value of 1193046 too large for field of 2 bytes at 0 ========== Fix this by providing the recommended instruction[1] for Thumb, and using the ARM instruction only when not building for Thumb. This also removes some comment, as QEMU for ARM allows to now test this case. Also use the opportunity to clean up the inline assembly, and just define the actual trap instruction inside #ifdef's, to improve readability. [1] https://developer.arm.com/documentation/dui0471/g/Semihosting/The-semihosting-interface?lang=en Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* Rename CONFIG_SYS_TEXT_BASE to CONFIG_TEXT_BASESimon Glass2022-10-312-2/+2
| | | | | | | | | The current name is inconsistent with SPL which uses CONFIG_SPL_TEXT_BASE and this makes it imposible to use CONFIG_VAL(). Rename it to resolve this problem. Signed-off-by: Simon Glass <sjg@chromium.org>
* common/board_f: move CONFIG_MACH_TYPE logic to arch/arm/lib/bdinfo.cOvidiu Panait2022-10-061-0/+12
| | | | | | | | asm/mach_type.h header and CONFIG_MACH_TYPE macro are arm-specific, so move related bdinfo logic to arch_setup_bdinfo() in arch/arm/lib/bdinfo.c. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
* treewide: Drop bootm_headers_t typedefSimon Glass2022-09-291-6/+7
| | | | | | This is not needed and we should avoid typedefs. Use the struct instead. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' into nextTom Rini2022-09-191-3/+3
|\ | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com>
| * arm: smh: Fix uninitialized parameters with newer GCCsSean Anderson2022-08-311-3/+3
| | | | | | | | | | | | | | | | | | Newer versions of GCC won't initialize parts of structures which don't appear to be used. This results in uninitialized semihosting parameters passed via R1. Fix this by marking the inline assembly as clobbering memory. Signed-off-by: Sean Anderson <sean.anderson@seco.com>
* | Add in the ability to load and boot an uncompressed kernel image during the ↵Nathan Barrett-Morrison2022-09-141-1/+4
| | | | | | | | | | | | | | | | | | | | Falcon Mode boot sequence. This is required for architectures which do not support compressed kernel images (i.e. ARM64). This is only used while not booting via FIT image. Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm: ARMv4 assembly compatibilitySergei Antonov2022-09-024-17/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is currently a problem that U-Boot can not work on ARMv4 because assembly imlementations of memcpy() and some other functions use "bx lr" instruction that is not available on ARMv4 ("mov pc, lr" should be used instead). A working preprocessor-based solution to this problem is found in arch/arm/lib/relocate.S. Move it to the "ret" macro in arch/arm/include/asm/assembler.h and change all "bx lr" code to "ret lr" in functions that may run on ARMv4. Linux source code deals with this problem in the same manner. v1 -> v2: Comment update. Pointed out by Andre Przywara. Signed-off-by: Sergei Antonov <saproj@gmail.com> CC: Samuel Holland <samuel@sholland.org> CC: Ye Li <ye.li@nxp.com> CC: Simon Glass <sjg@chromium.org> CC: Andre Przywara <andre.przywara@arm.com> CC: Marek Vasut <marex@denx.de> CC: Sean Anderson <sean.anderson@seco.com> CC: Tom Rini <trini@konsulko.com>
* | ARM: cache: Allow SPL to build cache-pl310.cPhilip Oberfichtner2022-09-011-1/+1
|/ | | | | | | | | | | | | | | | Introduce the new Kconfig symbol CONFIG_SPL_SYS_L2_PL310 to allow the SPL to build cache-pl310.c. Before this commit, the SPL could enable the PL310 L2 cache [1], but the cache maintenance functions from cache-pl310.c were only useable for non-SPL builds. After enabling the cache one must be able to flush it, too. Thus this commit allows cache-pl310.c to be included in the SPL build. [1] See for example arch/arm/mach-imx/cache.c: v7_outer_cache_enable() Signed-off-by: Philip Oberfichtner <pro@denx.de>
* ARM: relocate: Fix Thumb code by using proper label typeAndre Przywara2022-07-261-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | The generic ARM relocate_code function was using its own function entry point as a relocation base, and it was obtaining that address by using the "adr" instruction on that entry point label. However that label is not just an ordinary label, instead we explicitly mark it as a function start address. Normally that doesn't change much (other than for debugging), but when assembled in Thumb mode, newer versions of the GNU assembler prepare everything for this address being used as the argument to a "bx" call, so make sure bit 0 is set in there to mark this function as Thumb code. Of course this doesn't end up very well when we use this address for the ensuing memcpy operation. To avoid this problem, and to solve it in a robust way, add an extra label, which is not marked as a function entry, and use that for the adr instruction. This lets all assemblers generate the right immediate offset in the "adr" instruction. This fixes in particular ARMv7-M ports when using GNU binutils v2.37 or newer (commit d3e52e120b68 seems to trigger the change in behaviour). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reported-by: Jesse Taube <mr.bossman075@gmail.com>
* zynqmp: Run board_get_usable_ram_top() only on main U-BootAshok Reddy Soma2022-07-261-1/+1
| | | | | | | | | | | | | | | | With commit ce39ee28ec31 ("zynqmp: Do not place u-boot to reserved memory location"), the function board_get_usable_ram_top() is allocating MMU_SECTION_SIZE of about 2MB using lmb_alloc(). But we dont have this much memory in case of mini U-Boot. Keep these functions which use lmb under CONFIG_LMB so that they are compiled and used only when LMB is enabled. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/75e52def75f573e554a6b177a78504c128cb0c4a.1657183534.git.michal.simek@amd.com
* arm: riscv: Remove additional ifdef from code guarded by CONFIG_IS_ENABLEDMichal Simek2022-07-261-2/+0
| | | | | | | | | | CONFIG_OF_LIBFDT is used twice for guarding the same code. It is enough to do it once that's why remove additional ifdefs from arm and risc-v code. Fixes: 0c303f9a6628 ("image: Drop IMAGE_ENABLE_OF_LIBFDT") Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Link: https://lore.kernel.org/r/f8e3ff9124195cbd957874de9a65ef79760ef5e7.1657183634.git.michal.simek@amd.com
* Migrate CUSTOM_SYS_INIT_SP_ADDR to Kconfig using system-constants.hTom Rini2022-06-063-3/+6
| | | | | | | | | | | | | | - Make all users of CUSTOM_SYS_INIT_SP_ADDR reference SYS_INIT_SP_ADDR - Introduce HAS_CUSTOM_SYS_INIT_SP_ADDR to allow for setting the stack pointer directly, otherwise we use the common calculation. - On some platforms that were using the standard calculation but did not set CONFIG_SYS_INIT_RAM_SIZE / CONFIG_SYS_INIT_RAM_ADDR, set them. - On a small number of platforms that were not subtracting GENERATED_GBL_DATA_SIZE do so now via the standard calculation. - CONFIG_SYS_INIT_SP_OFFSET is now widely unused, so remove it from most board config header files. Signed-off-by: Tom Rini <trini@konsulko.com>
* arm: gic_v2: Skip gic_init_secure when cpu is not in el3Sai Pavan Boddu2022-05-231-0/+5
| | | | | | | | This would prevent configuring non-secure regs in case gic security extensions are not emulated in Qemu. Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-14 22:46:12 +0000