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* fsl-layerscape/soc.c: do not destroy bootcmd environmentMike Looijmans2024-02-081-0/+5
| | | | | | | | | When an XXX_BOOTCOMMAND isn't defined, the result is that bootcmd is set to some random memory content. Fix it so that the function does nothing in that case and leaves the bootcmd environment unmodified. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Reviewed-by: Dan Carpenter <dan.carpenter@linaro.org>
* mxs: Fix VDDx brownout interrupt disable/enableCody Green2023-12-201-3/+5
| | | | | | | | | | | | | | Incorrect registers HW_POWER_VDDIOCTRL, HW_POWER_VDDACTRL and HW_POWER_VDDDCTRL are used in the current code to disable/enable brownout interrupts in 'mxs_power_set_vddx()'. Change register to HW_POWER_CTRL which contains brownout interrupt enable bits ENIRQ_VDDIO_BO, ENIRQ_VDDA_BO and ENIRQ_VDDD_BO. Signed-off-by: Cody Green <cody@londelec.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Lukasz Majewski <lukma@denx.de>
* Merge tag 'u-boot-imx-next-20231214' of ↵Tom Rini2023-12-142-1/+11
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next - Add TPM support for venice boards - Add networking support for imx93-evk - Enable TCP, IPv6, wget for DHCOM and Data Modul boards - Enable fastboot support for Toradex boards - Allow pico-imx7d to boot from SD - Enable fastboot for beacon imx8m beacon boards, disabled SYS_CONSOLE_IS_IN_ENV - Fix mxsboot to prevent NAND blocks being reported as bad - Add imx8mm PWM clock support - Several devicetree syncs with the kernel - Add support for i.MX8MP Polyhex Debix Model A SBC - Reworked ddr_load_train_firmware() to get a 50ms boot time improvement
| * arm: mxs: Clear CPSR V bit to activate low vectorsMarek Vasut2023-12-132-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | The MXS starts with CPSR V bit set, which makes the CPU jump to high vectors in case of an exception. Those high vectors are located at 0xffff0000, which is where the BootROM exception table is located as well. U-Boot should handle exceptions on its own using its own exception handling code, which is located at 0x0, i.e. at low vectors. Clear the CPSR V bit, so that the CPU would jump to low vectors on exception instead, and therefore run the U-Boot exception handling code. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
* | Merge patch series "bootm: Refactoring to reduce reliance on CMDLINE (part A)"Tom Rini2023-12-131-3/+0
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To quote the author: It would be useful to be able to boot an OS when CONFIG_CMDLINE is disabled. This could allow reduced code size. Standard boot provides a way to handle programmatic boot, without scripts, so such a feature is possible. The main impediment is the inability to use the booting features of U-Boot without a command line. So the solution is to avoid passing command arguments and the like to code in boot/ A similar process has taken place with filesystems, for example, where we have (somewhat) separate Kconfig options for the filesystem commands and the filesystems themselves. This series starts the process of refactoring the bootm logic so that it can be called from standard boot without using the command line. Mostly it removes the use of argc, argv and cmdtbl from the internal logic. Some limited tidy-up is included, but this is kept to smaller patches, rather than trying to remove all #ifdefs etc. Some function comments are added, however. A simple programmatic boot is provided as a starting point. This work will likely take many series, so this is just the start. Size growth with this series for firefly-rk3288 (Thumb2) is: arm: (for 1/1 boards) all +23.0 rodata -49.0 text +72.0 This should be removed by: https://source.denx.de/u-boot/custodians/u-boot-dm/-/issues/11 but it is not included in this series as it is already large enough. No functional change is intended in this series. Changes in v3: - Add a panic if programmatic boot fails - Drop RFC tag Changes in v2: - Add new patch to adjust position of unmap_sysmem() in boot_get_kernel() - Add new patch to obtain command arguments - Fix 'boot_find_os' typo - Pass in the command name - Use the command table to provide the command name, instead of "bootm"
| * arm: x86: Drop discarding of command linker-listsSimon Glass2023-12-131-3/+0
| | | | | | | | | | | | | | | | | | | | Since we can now cleanly disable CMDLINE when needed, drop the rules which discard the command code. It will not be built in the first place. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
* | Revert "arm64: Use FEAT_HAFDBS to track dirty pages when available"Chris Packham2023-11-171-15/+1
| | | | | | | | | | | | | | | | | | | | This reverts commit 6cdf6b7a340db4ddd008516181de7e08e3f8c213. This is part of a series trying to make use of the arm64 hardware features for tracking dirty pages. Unfortunately this series causes problems for the AC5/AC5X SoCs. Having exhausted other options the consensus seems to be reverting this series is the best course of action. Signed-off-by: Chris Packham <judge.packham@gmail.com>
* | Revert "arm64: Use level-2 for largest block mappings when FEAT_HAFDBS is ↵Chris Packham2023-11-171-10/+4
| | | | | | | | | | | | | | | | | | | | | | | | present" This reverts commit 836b8d4b205d2175b57cb9ef271e638b0c116e89. This is part of a series trying to make use of the arm64 hardware features for tracking dirty pages. Unfortunately this series causes problems for the AC5/AC5X SoCs. Having exhausted other options the consensus seems to be reverting this series is the best course of action. Signed-off-by: Chris Packham <judge.packham@gmail.com>
* | Revert "armv8: enable HAFDBS for other ELx when FEAT_HAFDBS is present"Chris Packham2023-11-171-5/+1
| | | | | | | | | | | | | | | | | | | | This reverts commit c1da6fdb5c239b432440721772d993e63cfdeb20. This is part of a series trying to make use of the arm64 hardware features for tracking dirty pages. Unfortunately this series causes problems for the AC5/AC5X SoCs. Having exhausted other options the consensus seems to be reverting this series is the best course of action. Signed-off-by: Chris Packham <judge.packham@gmail.com>
* | tree-wide: Replace http:// link with https:// link for ti.comNishanth Menon2023-11-101-1/+1
|/ | | | | | Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
* sunxi: psci: implement PSCI on R528Sam Edwards2023-10-222-2/+53
| | | | | | | | | | This patch adds the necessary code to make nonsec booting and PSCI secondary core management functional on the R528/T113. Signed-off-by: Sam Edwards <CFSworks@gmail.com> Tested-by: Maksim Kiselev <bigunclemax@gmail.com> Tested-by: Kevin Amadiva <kevin.amadiva@mec.at> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
* sunxi: psci: stop modeling register layout with C structsSam Edwards2023-10-221-34/+23
| | | | | | | | | | | | | Since the sunxi support nowadays generally prefers #defined register offsets instead of modeling register layouts using C structs, now is a good time to do this for PSCI as well. This patch moves away from using the structs `sunxi_cpucfg_reg` and `sunxi_prcm_reg` in psci.c. The former struct and its associated header file existed only to support PSCI code, so also delete them altogether. Signed-off-by: Sam Edwards <CFSworks@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
* sunxi: psci: refactor register access to separate functionsSam Edwards2023-10-221-19/+47
| | | | | | | | | | | | This is to prepare for R528, which does not have the typical "CPUCFG" block; it has a "CPUX" block which provides these same functions but is organized differently. Moving the hardware-access bits to their own functions separates the logic from the hardware so we can reuse the same logic. Signed-off-by: Sam Edwards <CFSworks@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
* sunxi: psci: clean away preprocessor macrosSam Edwards2023-10-221-60/+43
| | | | | | | | | | | | This patch restructures psci.c to get away from the "many different function definitions switched by #ifdef" paradigm to the preferred style of having a single function definition with `if (IS_ENABLED(...))` to make the optimizer include only the appropriate function bodies instead. There are no functional changes here. Signed-off-by: Sam Edwards <CFSworks@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
* sunxi: refactor serial base addresses to avoid asm/arch/cpu.hAndre Przywara2023-10-222-0/+2
| | | | | | | | | | | | | | | | At the moment we have each SoC's memory map defined in its own cpu.h, which is included in include/configs/sunxi_common.h. This will be a problem with the introduction of Allwinner RISC-V support. Remove the inclusion of that header file from the common config header, instead move the required serial base addresses (for the SPL) into a separate header file. Then include the original cpu.h file only where we really need it, which is only under arch/arm now. This disentangles the architecture specific header files from the generic code. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* ARM: psci: move GIC address override to KconfigAndre Przywara2023-10-113-4/+14
| | | | | | | | | | | | | | | | | As the code to switch an ARM core from secure to the non-secure state needs to know the base address of the Generic Interrupt Controller (GIC), we read an Arm Cortex defined system register that is supposed to hold that base address. However there are SoCs out there that get this wrong, and this CBAR register either reads as 0 or points to the wrong address. To accommodate those systems, so far we use a macro defined in some platform specific header files, for affected boards. To simplify future extensions, replace that macro with a Kconfig variable that holds this override address, and define a default value for SoCs that need it. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Sam Edwards <CFSworks@gmail.com>
* armv8: fsl-layerscape: make some functions staticLaurentiu Tudor2023-10-101-6/+6
| | | | | | | Some functions are not used outside this file, so make them static. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* fsl-layerscape: drop obsolete PPA secure firmware supportLaurentiu Tudor2023-10-104-379/+0
| | | | | | | | | PPA was a secure firmware developed in-house which is no longer supported and replaced by TF-A quite some years ago. Drop support for it. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* spl: Rename SYS_SPL_ARGS_ADDR to SPL_PAYLOAD_ARGS_ADDRSimon Glass2023-10-061-1/+1
| | | | | | | | Rename this so that SPL is first, as per U-Boot convention. Also add PAYLOAD_ since this is where in memory the parameters for the payload have been stored. Signed-off-by: Simon Glass <sjg@chromium.org>
* spl: Use CONFIG_SPL... instead of CONFIG_..._SPL_...Simon Glass2023-10-061-1/+1
| | | | | | | | | | | We like to put the SPL first so it is clear that it relates to SPL. Rename various malloc-related options which have crept in, to stick to this convention. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Martyn Welch <martyn.welch@collabora.com> Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com>
* freescale: Drop call to init_func_vid() in the init sequenceSimon Glass2023-08-311-0/+5
| | | | | | | | Use the misc_init_f event instead, which is designed for this purpose. All boards with CONFIG_VID already enable CONFIG_EVENT. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge tag 'v2023.10-rc3' into nextTom Rini2023-08-212-6/+56
|\ | | | | | | | | | | Prepare v2023.10-rc3 Signed-off-by: Tom Rini <trini@konsulko.com>
| * arm64: fsl: layerscape: Remove unused functionsShenlin Liang2023-08-091-5/+0
| | | | | | | | | | | | | | | | Function board_switch_core_volt has not been used since it was defined Signed-off-by: Shenlin Liang <liangshenlin@eswincomputing.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * arm64: smccc: add support for SMCCCv1.2 x0-x17 registersAbdellatif El Khlifi2023-08-081-1/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add support for x0-x17 registers used by the SMC calls In SMCCC v1.2 [1] arguments are passed in registers x1-x17. Results are returned in x0-x17. This work is inspired from the following kernel commit: arm64: smccc: Add support for SMCCCv1.2 extended input/output registers [1]: https://documentation-service.arm.com/static/5f8edaeff86e16515cdbe4c6?token= Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
* | armv8: Skip PIE in SPL due to load alignment fault.Kevin Chen2023-08-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When PIE is enabled in start.S, u-boot/-spl use __rel_dyn_start and _rel_dyn_end symbol to be loaded to and executed at a different address than it was linked at. u-boot-spl.lds is used in SPL build, but relocation information section(.rela*) were discarded. In line number 80 in arch/arm/cpu/armv8/u-boot-spl.lds /DISCARD/ : { *(.rela*) } If PIE enabled in SPL, __rel_dyn_start which is defined as .rel_dyn_start in sections.c will be apended to the end of .bss section. In our ASPEED case, size of .bss section would let .rel_dyn_start without 8-byte alignment, leading to alignment fault when executing ldp instuction in pie_fix_loop. Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>
* | treewide: unify the linker symbol reference formatShiji Yang2023-08-092-2/+2
| | | | | | | | | | | | | | | | | | | | | | Now all linker symbols are declared as type char[]. Though we can reference the address via both the array name 'var' and its address '&var'. It's better to unify them to avoid confusing developers. This patch converts all '&var' linker symbol refrences to the most commonly used format 'var'. Signed-off-by: Shiji Yang <yangshiji66@outlook.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | Kconfigs: Correct default of "0" on hex type entriesTom Rini2023-08-092-2/+1
|/ | | | | | | | | | | | | | It is not a parse error to have a default value of "0" for a "hex" type entry, instead of "0x0". However, "0" and "0x0" are not treated the same even by the tools themselves. Correct this by changing the default value from "0" to "0x0" for all hex type questions that had the incorrect default. Fix one instance (in two configs) of a default of "0" being used on a hex question to be "0x0". Remove the cases where a defconfig had set a value of "0x0" to be used as the default had been "0". Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arch: arm: fsl-layerscape: allow "opt-out" of fsl_setenv_bootcmdMathew McBride2023-08-031-1/+1
| | | | | | | | | | | | | | | | | | | Allow individual Layerscape boards to opt-out of fsl_setenv_bootcmd by declaring the original function as weak. fsl_setenv_bootcmd is used to change the bootcmd based on the TF-A boot source (e.g QSPI vs SD/MMC) for reasons including secure boot / integrity measurements and DPAA2 configuration loading. See previous discussion at [1]. On the Ten64 board, our bootcmd is the same across all TF-A boot sources so we don't want this behaviour. Signed-off-by: Mathew McBride <matt@traverse.com.au> [1] https://patchwork.ozlabs.org/project/uboot/patch/20211110044639.7070-3-matt@traverse.com.au/#2790037 Reviewed-by: Peng Fan <peng.fan@nxp.com>
* Revert "Merge branch '2023-07-24-introduce-FF-A-suppport'"Tom Rini2023-07-241-56/+1
| | | | | | | | | This reverts commit d927d1a80843e1c3e2a3f0b8f6150790bef83da1, reversing changes made to c07ad9520c6190070513016fdb495d4703a4a853. These changes do not pass CI currently. Signed-off-by: Tom Rini <trini@konsulko.com>
* arm64: smccc: add support for SMCCCv1.2 x0-x17 registersAbdellatif El Khlifi2023-07-241-1/+56
| | | | | | | | | | | | | | | | | | | add support for x0-x17 registers used by the SMC calls In SMCCC v1.2 [1] arguments are passed in registers x1-x17. Results are returned in x0-x17. This work is inspired from the following kernel commit: arm64: smccc: Add support for SMCCCv1.2 extended input/output registers [1]: https://documentation-service.arm.com/static/5f8edaeff86e16515cdbe4c6?token= Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
* arm: mxs: Prevent serial console init when in very early SPL boot codeLukasz Majewski2023-07-111-2/+4
| | | | | | | | When DM_SERIAL is enabled on mxs (i.e. imx28) platform, the console early initialization must be postponed until the driver model is correctly setup. Signed-off-by: Lukasz Majewski <lukma@denx.de>
* arm: mxs: Add function to dump PMU registersLukasz Majewski2023-07-111-0/+24
| | | | | | | This commit provides function, which when debugging output is enabled dumps the IMX28 PMU registers. Signed-off-by: Lukasz Majewski <lukma@denx.de>
* arm: mxs: Provide Kconfig option to not enable 4P2 regulator in IMX28 PMULukasz Majewski2023-07-111-1/+2
| | | | | | | | | | | | | | | | | | | | The IMX28 PMU (Power Management Unit) has a dedicated Linear Regulator to produce (by default) 4.2V output - available outside the chip as VDD_4P2. When system is supposed to not use VDD5V as a main power source - instead the DCDC_BATT is used; it is safe to disable this regulator. As the in-PMU DCDC switching regulator (from which DCDC_VDDA, DCDC_VDDIO and DCDC_VDDD are generated) can be driven from DCDC_BATT or output of this 4P2 regulator - by disabling the latter the use of the DCDC_BATT is forced. To be more specific - according to NXP's AN4199 the DCDC_BATT source is preferred (over VDD5V), as more efficient and stable source for industrial applications. Signed-off-by: Lukasz Majewski <lukma@denx.de>
* arm: mxs: Provide Kconfig option to disable battery charging at IMX28 PMULukasz Majewski2023-07-111-0/+7
| | | | | | | | This new Kconfig option allows disabling the in-PMU battery charging block. This may be required when DCDC_BAT source is powered not from battery, but from already regulated, good quality source. Signed-off-by: Lukasz Majewski <lukma@denx.de>
* arm: mxs: Provide Kconfig option to to not use VDD5V as IMX28 PMU sourceLukasz Majewski2023-07-111-0/+4
| | | | | | | | | | | | This option sets the current limit for 5V source to zero, so all the PMU outputs are primarily powered from battery source (DCDC_BAT). This option may be set on systems, where the 5V is NOT supposed to be in any scenario powering the system - for example on systems where DCDC_BAT is connected to fixed and regulated 4.2V source (so the "battery" is not present). Signed-off-by: Lukasz Majewski <lukma@denx.de>
* Merge tag 'v2023.07-rc6' into nextTom Rini2023-07-056-6/+19
|\ | | | | | | Prepare v2023.07-rc6
| * sunxi: u-boot-spl.lds: Pass _image_binary_endFabio Estevam2023-07-032-0/+2
| | | | | | | | | | | | | | | | | | | | | | Pass _image_binary_end to make a standard way to indicate the end of the text section in SPL. The motivation for this is to have a uniform way to handle the SPL boundary checks. Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Marek Vasut <marex@denx.de>
| * ARM: arm11: Add C wrapper for allow_unaligned()Marek Vasut2023-07-012-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename current assembler implementation of allow_unaligned() to arm11_arch_cp15_allow_unaligned() and add it into arm11.h header, then add C wrapper of allow_unaligned(). This fixes misbehavior when linking U-Boot, where the CPU specific allow_unaligned() implementation was ignored and instead the __weak allow_unaligned() implementation from lib/efi_loader/efi_setup.c was used, which led to "data abort" just before booting Linux via tftp, in efi_dp_from_file() -> path_to_uefi() -> utf16_put() . The problem is triggerd by c7c0ca37673 ("efi_loader: fix efi_dp_from_file()") . Adding the wrapper fixes the problem. Fixes: d47a774680d ("arm: arm11: allow unaligned memory access") Signed-off-by: Marek Vasut <marex@denx.de>
| * ARM: armv7: Add C wrapper for allow_unaligned()Marek Vasut2023-07-012-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename current assembler implementation of allow_unaligned() to v7_arch_cp15_allow_unaligned() and add it into armv7.h header, then add C wrapper of allow_unaligned(). This fixes misbehavior when linking U-Boot on ARMv7a i.MX6Q, where the CPU specific allow_unaligned() implementation was ignored and instead the __weak allow_unaligned() implementation from lib/efi_loader/efi_setup.c was used, which led to "data abort" just before booting Linux via tftp, in efi_dp_from_file() -> path_to_uefi() -> utf16_put() . The problem is triggerd by c7c0ca37673 ("efi_loader: fix efi_dp_from_file()") . Adding the wrapper fixes the problem. Fixes: 78f90aaeecc ("arm: armv7: allow unaligned memory access") Signed-off-by: Marek Vasut <marex@denx.de>
* | psci: fix use of clobbered registers in asmSam Edwards2023-06-201-3/+3
| | | | | | | | | | | | | | | | The functions `psci_get_context_id` and `psci_get_target_pc` are written in C, so the C compiler may clobber registers r0-r3. Do not use these registers to save data across calls. Signed-off-by: Sam Edwards <CFSworks@gmail.com>
* | global: Use proper project name U-BootMichal Simek2023-06-123-3/+3
|/ | | | | | | | | | | Use proper project name in comments, Kconfig, readmes. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Qu Wenruo <wqu@suse.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/0dbdf0432405c1c38ffca55703b6737a48219e79.1684307818.git.michal.simek@amd.com
* ARM: armv7: add non-SPL enable for Cortex SMPENRalph Siemsen2023-05-131-0/+5
| | | | | | | | | | Commit 2564fce7eea3 ("sunxi: move Cortex SMPEN setting into start.S") added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For platforms not using SPL boot, add the corresponding non-SPL config, so that CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) works as expected. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
* armv8: fsl-layerscape: check for crypto node first in fdt_fixup_remove_jrMathew McBride2023-05-051-0/+4
| | | | | | | | | | | | | | | | | | This a problem I found while updating the U-Boot fsl-ls1088a.dtsi to match the Linux version. fdt_fixup_remove_jr did not check whether there was a "crypto" alias in the device tree before calling more fdt_* functions, which resulted in a crash. Fixes: a797f274 ("ARMv8/sec_firmware : Update chosen/kaslr-seed with random number") Signed-off-by: Mathew McBride <matt@traverse.com.au> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ioana Ciornei <ioana.ciornei@nxp.com> Tested-by: Ioana Ciornei <ioana.ciornei@nxp.com> # on LS1088A-RDB
* armv7: Use isb/dsb directly in start.STom Rini2023-04-251-4/+4
| | | | | | | | | | Toolchains which do not directly support using "isb" and "dsb" directly are no longer functionally supported in U-Boot. Furthermore, clang has for a long time warned about using the alternate form that we were. Update the code. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: Centralize fixed register logicTom Rini2023-04-251-1/+0
| | | | | | | | | | | | When building for ARM64, we need to pass -ffixed-x18 and otherwise pass -ffixed-r9. Rather than having this logic in two places, we can do this once in arch/arm/config.mk. Further, while gcc will ignore being passed both -ffixed-r9 and -ffixed-x18 and simply use -ffixed-x18, clang will note that -ffixed-r9 is not used. Remove this duplication to also remove the warning. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* armv8: enable HAFDBS for other ELx when FEAT_HAFDBS is presentmeitao2023-04-251-1/+5
| | | | | | | | | | | | u-boot could be run at EL1/EL2/EL3. so we set it as same as EL1 does. otherwise it will hang when enable mmu, that is what we encounter in our SOC. Signed-off-by: meitao <meitaogao@asrmicro.com> [ Paul: pick from the Android tree. Rebase to the upstream ] Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: Tom Rini <trini@konsulko.com> Link: https://android.googlesource.com/platform/external/u-boot/+/3bf38943aeab4700c2319bff2a1477d99c6afd2f
* arm64: Use level-2 for largest block mappings when FEAT_HAFDBS is presentMarc Zyngier2023-04-251-4/+10
| | | | | | | | | | | | | In order to make invalidation by VA more efficient, set the largest block mapping to 2MB, mapping it onto level-2. This has no material impact on u-boot's runtime performance, and allows a huge speedup when cleaning the cache. Signed-off-by: Marc Zyngier <maz@kernel.org> [ Paul: pick from the Android tree. Rebase to the upstream ] Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: Tom Rini <trini@konsulko.com> Link: https://android.googlesource.com/platform/external/u-boot/+/417a73581a72ff6d6ee4b0938117b8a23e32f7e8
* arm64: Use FEAT_HAFDBS to track dirty pages when availableMarc Zyngier2023-04-251-1/+15
| | | | | | | | | | | | | Some recent arm64 cores have a facility that allows the page table walker to track the dirty state of a page. This makes it really efficient to perform CMOs by VA as we only need to look at dirty pages. Signed-off-by: Marc Zyngier <maz@kernel.org> [ Paul: pick from the Android tree. Rebase to the upstream ] Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: Tom Rini <trini@konsulko.com> Link: https://android.googlesource.com/platform/external/u-boot/+/3c433724e6f830a6b2edd5ec3d4a504794887263
* ARM: remove SPEAR entry in makefilePatrick Delaunay2023-03-061-1/+0
| | | | | | | | As the lastest spear directories are removed, delete the associated entry in Makefile. Fixes: 570c3dcfc153 ("arm: Remove spear600 boards and the rest of SPEAr support") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
* arm64: Reduce PT size estimation complexityMarc Zyngier2023-03-061-75/+34
| | | | | | | | | | | | | | | | | | | | count_required_pts()'s complexity is high if mappings are not using the largest possible block size (due to some other requirement such as tracking dirty pages, for example). Let's switch to a method that follows the pattern established with the add_map() helper, and make it almost instantaneous instead of taking a large amount of time if 2MB mappings are in use instead of 1GB. Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Pierre-Clément Tosi <ptosi@google.com> [ Paul: pick from the Android tree. Fixup Pierre's commit. Rebase to the upstream ] Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: Tom Rini <trini@konsulko.com> Link: https://android.googlesource.com/platform/external/u-boot/+/5d756d147e31a1cdaaa261a50e526404ca5968f5 Link: https://android.googlesource.com/platform/external/u-boot/+/6be9330601d81545c7c941e3609f35bf68a09059
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