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-rw-r--r--drivers/ddr/marvell/axp/ddr3_hw_training.h1
-rw-r--r--drivers/ddr/marvell/axp/ddr3_init.c40
-rw-r--r--drivers/ddr/marvell/axp/ddr3_init.h3
-rw-r--r--drivers/ddr/marvell/axp/ddr3_spd.c16
-rw-r--r--drivers/misc/fsl_portals.c10
-rw-r--r--drivers/pci/pci-aardvark.c1
-rw-r--r--drivers/pci/pci_mvebu.c1
-rw-r--r--drivers/pci/pcie_layerscape_fixup.c8
-rw-r--r--drivers/pci/pcie_layerscape_gen4_fixup.c8
-rw-r--r--drivers/phy/marvell/comphy_a3700.c133
-rw-r--r--drivers/phy/marvell/comphy_core.c59
-rw-r--r--drivers/phy/marvell/comphy_core.h23
-rw-r--r--drivers/phy/marvell/comphy_cp110.c58
-rw-r--r--drivers/serial/serial_mvebu_a3700.c1
14 files changed, 260 insertions, 102 deletions
diff --git a/drivers/ddr/marvell/axp/ddr3_hw_training.h b/drivers/ddr/marvell/axp/ddr3_hw_training.h
index 30daaa9831..fcdef792c7 100644
--- a/drivers/ddr/marvell/axp/ddr3_hw_training.h
+++ b/drivers/ddr/marvell/axp/ddr3_hw_training.h
@@ -373,7 +373,6 @@ int ddr3_load_dqs_patterns(MV_DRAM_INFO *dram_info);
void ddr3_static_training_init(void);
-u8 ddr3_get_eprom_fabric(void);
void ddr3_set_performance_params(MV_DRAM_INFO *dram_info);
int ddr3_dram_sram_burst(u32 src, u32 dst, u32 len);
void ddr3_save_training(MV_DRAM_INFO *dram_info);
diff --git a/drivers/ddr/marvell/axp/ddr3_init.c b/drivers/ddr/marvell/axp/ddr3_init.c
index 607f3e12c3..a9dcb74cec 100644
--- a/drivers/ddr/marvell/axp/ddr3_init.c
+++ b/drivers/ddr/marvell/axp/ddr3_init.c
@@ -361,12 +361,18 @@ static u32 ddr3_init_main(void)
__maybe_unused u32 ddr_width = BUS_WIDTH;
__maybe_unused int status;
__maybe_unused u32 win_backup[16];
+ __maybe_unused struct udevice *udev;
+ __maybe_unused int ret;
/* SoC/Board special Initializtions */
fab_opt = ddr3_get_fab_opt();
#ifdef CONFIG_SPD_EEPROM
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ ret = i2c_get_chip_for_busnum(0, BUS_WIDTH_ECC_TWSI_ADDR, 1, &udev);
+ if (ret) {
+ printf("Cannot find SPD EEPROM\n");
+ return MV_DDR3_TRAINING_ERR_BAD_DIMM_SETUP;
+ }
#endif
ddr3_print_version();
@@ -438,7 +444,7 @@ static u32 ddr3_init_main(void)
#if defined(ECC_SUPPORT) && defined(AUTO_DETECTION_SUPPORT)
ecc = 0;
- if (ddr3_check_config(BUS_WIDTH_ECC_TWSI_ADDR, CONFIG_ECC))
+ if (ddr3_check_config(udev, CONFIG_ECC))
ecc = 1;
#endif
@@ -483,7 +489,7 @@ static u32 ddr3_init_main(void)
* Dynamically Set 32Bit and ECC for AXP (Relevant only for
* Marvell DB boards)
*/
- if (ddr3_check_config(BUS_WIDTH_ECC_TWSI_ADDR, CONFIG_BUS_WIDTH)) {
+ if (ddr3_check_config(udev, CONFIG_BUS_WIDTH)) {
ddr_width = 32;
DEBUG_INIT_S("DDR3 Training Sequence - DRAM bus width 32Bit\n");
}
@@ -904,7 +910,7 @@ void ddr3_static_mc_init(void)
* Notes: Only Available for ArmadaXP/Armada 370 DB boards
* Returns: None.
*/
-int ddr3_check_config(u32 twsi_addr, MV_CONFIG_TYPE config_type)
+int ddr3_check_config(struct udevice *udev, MV_CONFIG_TYPE config_type)
{
#ifdef AUTO_DETECTION_SUPPORT
u8 data = 0;
@@ -916,7 +922,7 @@ int ddr3_check_config(u32 twsi_addr, MV_CONFIG_TYPE config_type)
else
offset = 0;
- ret = i2c_read(twsi_addr, offset, 1, (u8 *)&data, 1);
+ ret = dm_i2c_read(udev, offset, &data, 1);
if (!ret) {
switch (config_type) {
case CONFIG_ECC:
@@ -943,30 +949,6 @@ int ddr3_check_config(u32 twsi_addr, MV_CONFIG_TYPE config_type)
return 0;
}
-#if defined(DB_88F78X60_REV2)
-/*
- * Name: ddr3_get_eprom_fabric - Get Fabric configuration from EPROM
- * Desc:
- * Args: twsi Address
- * Notes: Only Available for ArmadaXP DB Rev2 boards
- * Returns: None.
- */
-u8 ddr3_get_eprom_fabric(void)
-{
-#ifdef AUTO_DETECTION_SUPPORT
- u8 data = 0;
- int ret;
-
- ret = i2c_read(NEW_FABRIC_TWSI_ADDR, 1, 1, (u8 *)&data, 1);
- if (!ret)
- return data & 0x1F;
-#endif
-
- return 0;
-}
-
-#endif
-
/*
* Name: ddr3_cl_to_valid_cl - this return register matching CL value
* Desc:
diff --git a/drivers/ddr/marvell/axp/ddr3_init.h b/drivers/ddr/marvell/axp/ddr3_init.h
index 569a14b718..a26bd2a120 100644
--- a/drivers/ddr/marvell/axp/ddr3_init.h
+++ b/drivers/ddr/marvell/axp/ddr3_init.h
@@ -98,11 +98,10 @@ int ddr3_hw_training(u32 target_freq, u32 ddr_width,
void ddr3_print_version(void);
void fix_pll_val(u8 target_fab);
-u8 ddr3_get_eprom_fabric(void);
u32 ddr3_get_fab_opt(void);
u32 ddr3_get_cpu_freq(void);
u32 ddr3_get_vco_freq(void);
-int ddr3_check_config(u32 addr, MV_CONFIG_TYPE config_type);
+int ddr3_check_config(struct udevice *udev, MV_CONFIG_TYPE config_type);
u32 ddr3_get_static_mc_value(u32 reg_addr, u32 offset1, u32 mask1, u32 offset2,
u32 mask2);
u32 ddr3_cl_to_valid_cl(u32 cl);
diff --git a/drivers/ddr/marvell/axp/ddr3_spd.c b/drivers/ddr/marvell/axp/ddr3_spd.c
index dd772e63ab..4763403c12 100644
--- a/drivers/ddr/marvell/axp/ddr3_spd.c
+++ b/drivers/ddr/marvell/axp/ddr3_spd.c
@@ -209,13 +209,19 @@ static u32 ddr3_get_dimm_num(u32 *dimm_addr)
/* Read the dimm eeprom */
for (dimm_cur_addr = MAX_DIMM_ADDR; dimm_cur_addr > MIN_DIMM_ADDR;
dimm_cur_addr--) {
+ struct udevice *udev;
+
data[SPD_DEV_TYPE_BYTE] = 0;
/* Far-End DIMM must be connected */
if ((dimm_num == 0) && (dimm_cur_addr < FAR_END_DIMM_ADDR))
return 0;
- ret = i2c_read(dimm_cur_addr, 0, 1, (uchar *)data, 3);
+ ret = i2c_get_chip_for_busnum(0, dimm_cur_addr, 1, &udev);
+ if (ret)
+ continue;
+
+ ret = dm_i2c_read(udev, 0, data, 3);
if (!ret) {
if (data[SPD_DEV_TYPE_BYTE] == SPD_MEM_TYPE_DDR3) {
dimm_addr[dimm_num] = dimm_cur_addr;
@@ -245,9 +251,15 @@ int ddr3_spd_init(MV_DIMM_INFO *info, u32 dimm_addr, u32 dimm_width)
__maybe_unused u8 vendor_high, vendor_low;
if (dimm_addr != 0) {
+ struct udevice *udev;
+
memset(spd_data, 0, SPD_SIZE * sizeof(u8));
- ret = i2c_read(dimm_addr, 0, 1, (uchar *)spd_data, SPD_SIZE);
+ ret = i2c_get_chip_for_busnum(0, dimm_addr, 1, &udev);
+ if (ret)
+ return MV_DDR3_TRAINING_ERR_TWSI_FAIL;
+
+ ret = dm_i2c_read(udev, 0, spd_data, SPD_SIZE);
if (ret)
return MV_DDR3_TRAINING_ERR_TWSI_FAIL;
}
diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c
index 632430e420..02bc3f86ca 100644
--- a/drivers/misc/fsl_portals.c
+++ b/drivers/misc/fsl_portals.c
@@ -106,7 +106,7 @@ static int fdt_qportal(void *blob, int off, int id, char *name,
enum fsl_dpaa_dev dev, int create)
{
int childoff, dev_off, ret = 0;
- u32 dev_handle;
+ unsigned int dev_handle;
#ifdef CONFIG_FSL_CORENET
int num;
u32 liodns[2];
@@ -142,11 +142,9 @@ static int fdt_qportal(void *blob, int off, int id, char *name,
if (childoff > 0) {
dev_handle = fdt_get_phandle(blob, dev_off);
if (dev_handle <= 0) {
- dev_handle = fdt_alloc_phandle(blob);
- ret = fdt_set_phandle(blob, dev_off,
- dev_handle);
- if (ret < 0)
- return ret;
+ dev_handle = fdt_create_phandle(blob, dev_off);
+ if (!dev_handle)
+ return -FDT_ERR_NOPHANDLES;
}
ret = fdt_setprop(blob, childoff, "dev-handle",
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index 6d73aab03f..6e5730cfc3 100644
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -21,6 +21,7 @@
*
* Author: Victor Gu <xigu@marvell.com>
* Hezi Shahmoon <hezi.shahmoon@marvell.com>
+ * Pali Rohár <pali@kernel.org>
*
*/
diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c
index 14cd82db6f..fad38b7db1 100644
--- a/drivers/pci/pci_mvebu.c
+++ b/drivers/pci/pci_mvebu.c
@@ -7,6 +7,7 @@
* Ported to U-Boot by:
* Anton Schubert <anton.schubert@gmx.de>
* Stefan Roese <sr@denx.de>
+ * Pali Rohár <pali@kernel.org>
*/
#include <common.h>
diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c
index 8a2a0e1f4a..a47c9ef7c2 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -584,9 +584,9 @@ static void ft_pcie_rc_fix(void *blob, struct ls_pcie_rc *pcie_rc)
return;
if (pcie_rc->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
- fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
+ fdt_set_node_status(blob, off, FDT_STATUS_OKAY);
else
- fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+ fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
}
static void ft_pcie_ep_fix(void *blob, struct ls_pcie_rc *pcie_rc)
@@ -600,9 +600,9 @@ static void ft_pcie_ep_fix(void *blob, struct ls_pcie_rc *pcie_rc)
return;
if (pcie_rc->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
- fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
+ fdt_set_node_status(blob, off, FDT_STATUS_OKAY);
else
- fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+ fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
}
static void ft_pcie_ls_setup(void *blob, struct ls_pcie_rc *pcie_rc)
diff --git a/drivers/pci/pcie_layerscape_gen4_fixup.c b/drivers/pci/pcie_layerscape_gen4_fixup.c
index 7d11234106..b2a45bf105 100644
--- a/drivers/pci/pcie_layerscape_gen4_fixup.c
+++ b/drivers/pci/pcie_layerscape_gen4_fixup.c
@@ -193,9 +193,9 @@ static void ft_pcie_ep_layerscape_gen4_fix(void *blob, struct ls_pcie_g4 *pcie)
}
if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
- fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
+ fdt_set_node_status(blob, off, FDT_STATUS_OKAY);
else
- fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+ fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
}
static void ft_pcie_rc_layerscape_gen4_fix(void *blob, struct ls_pcie_g4 *pcie)
@@ -214,9 +214,9 @@ static void ft_pcie_rc_layerscape_gen4_fix(void *blob, struct ls_pcie_g4 *pcie)
}
if (pcie->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
- fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
+ fdt_set_node_status(blob, off, FDT_STATUS_OKAY);
else
- fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+ fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
}
static void ft_pcie_layerscape_gen4_setup(void *blob, struct ls_pcie_g4 *pcie)
diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c
index 047c8bb045..4104353555 100644
--- a/drivers/phy/marvell/comphy_a3700.c
+++ b/drivers/phy/marvell/comphy_a3700.c
@@ -11,6 +11,7 @@
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <linux/delay.h>
+#include <phy.h>
#include "comphy_a3700.h"
@@ -982,6 +983,138 @@ void comphy_dedicated_phys_init(void)
debug_exit();
}
+static int find_available_node_by_compatible(int offset, const char *compatible)
+{
+ do {
+ offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset,
+ compatible);
+ } while (offset > 0 && !fdtdec_get_is_enabled(gd->fdt_blob, offset));
+
+ return offset;
+}
+
+static bool comphy_a3700_find_lane(const int nodes[3], int node,
+ int port, int *lane, int *invert)
+{
+ int res, i, j;
+
+ for (i = 0; ; i++) {
+ struct fdtdec_phandle_args args;
+
+ res = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "phys",
+ "#phy-cells", 0, i, &args);
+ if (res)
+ return false;
+
+ for (j = 0; j < 3; j++) {
+ if (nodes[j] >= 0 && args.node == nodes[j] &&
+ (args.args_count >= 1 ? args.args[0] : 0) == port) {
+ *lane = j;
+ *invert = args.args_count >= 2 ? args.args[1]
+ : 0;
+ return true;
+ }
+ }
+ }
+
+ return false;
+}
+
+static void comphy_a3700_fill_cfg(struct chip_serdes_phy_config *cfg,
+ const int nodes[3], const char *compatible,
+ int type)
+{
+ int node, lane, port, speed, invert;
+
+ port = (type == COMPHY_TYPE_SGMII1) ? 1 : 0;
+
+ node = -1;
+ while (1) {
+ node = find_available_node_by_compatible(node, compatible);
+ if (node < 0)
+ return;
+
+ if (comphy_a3700_find_lane(nodes, node, port, &lane, &invert))
+ break;
+ }
+
+ if (cfg->comphy_map_data[lane].type != COMPHY_TYPE_UNCONNECTED) {
+ printf("Error: More PHYs defined for lane %d, skipping\n",
+ lane);
+ return;
+ }
+
+ if (type == COMPHY_TYPE_SGMII0 || type == COMPHY_TYPE_SGMII1) {
+ const char *phy_mode;
+
+ phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
+ if (phy_mode &&
+ !strcmp(phy_mode,
+ phy_string_for_interface(PHY_INTERFACE_MODE_2500BASEX)))
+ speed = COMPHY_SPEED_3_125G;
+ else
+ speed = COMPHY_SPEED_1_25G;
+ } else if (type == COMPHY_TYPE_SATA0) {
+ speed = COMPHY_SPEED_6G;
+ } else {
+ speed = COMPHY_SPEED_5G;
+ }
+
+ cfg->comphy_map_data[lane].type = type;
+ cfg->comphy_map_data[lane].speed = speed;
+ cfg->comphy_map_data[lane].invert = invert;
+}
+
+static const fdt32_t comphy_a3700_mux_lane_order[3] = {
+ __constant_cpu_to_be32(1),
+ __constant_cpu_to_be32(0),
+ __constant_cpu_to_be32(2),
+};
+
+int comphy_a3700_init_serdes_map(int node, struct chip_serdes_phy_config *cfg)
+{
+ int comphy_nodes[3];
+ int child, i;
+
+ for (i = 0; i < ARRAY_SIZE(comphy_nodes); i++)
+ comphy_nodes[i] = -FDT_ERR_NOTFOUND;
+
+ fdt_for_each_subnode(child, gd->fdt_blob, node) {
+ if (!fdtdec_get_is_enabled(gd->fdt_blob, child))
+ continue;
+
+ i = fdtdec_get_int(gd->fdt_blob, child, "reg", -1);
+ if (i < 0 || i >= ARRAY_SIZE(comphy_nodes))
+ continue;
+
+ comphy_nodes[i] = child;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(comphy_nodes); i++) {
+ cfg->comphy_map_data[i].type = COMPHY_TYPE_UNCONNECTED;
+ cfg->comphy_map_data[i].speed = COMPHY_SPEED_INVALID;
+ }
+
+ comphy_a3700_fill_cfg(cfg, comphy_nodes, "marvell,armada3700-u3d",
+ COMPHY_TYPE_USB3_DEVICE);
+ comphy_a3700_fill_cfg(cfg, comphy_nodes, "marvell,armada3700-xhci",
+ COMPHY_TYPE_USB3_HOST0);
+ comphy_a3700_fill_cfg(cfg, comphy_nodes, "marvell,armada-3700-pcie",
+ COMPHY_TYPE_PEX0);
+ comphy_a3700_fill_cfg(cfg, comphy_nodes, "marvell,armada-3700-ahci",
+ COMPHY_TYPE_SATA0);
+ comphy_a3700_fill_cfg(cfg, comphy_nodes, "marvell,armada-3700-neta",
+ COMPHY_TYPE_SGMII0);
+ comphy_a3700_fill_cfg(cfg, comphy_nodes, "marvell,armada-3700-neta",
+ COMPHY_TYPE_SGMII1);
+
+ cfg->comphy_lanes_count = 3;
+ cfg->comphy_mux_bitcount = 4;
+ cfg->comphy_mux_lane_order = comphy_a3700_mux_lane_order;
+
+ return 0;
+}
+
int comphy_a3700_init(struct chip_serdes_phy_config *chip_cfg,
struct comphy_map *serdes_map)
{
diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c
index 2c9d7b2288..233a973035 100644
--- a/drivers/phy/marvell/comphy_core.c
+++ b/drivers/phy/marvell/comphy_core.c
@@ -86,11 +86,8 @@ __weak int comphy_update_map(struct comphy_map *serdes_map, int count)
static int comphy_probe(struct udevice *dev)
{
- const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
struct chip_serdes_phy_config *chip_cfg = dev_get_priv(dev);
- int subnode;
- int lane;
int last_idx = 0;
static int current_idx;
int res;
@@ -104,30 +101,14 @@ static int comphy_probe(struct udevice *dev)
if (IS_ERR(chip_cfg->hpipe3_base_addr))
return PTR_ERR(chip_cfg->hpipe3_base_addr);
- chip_cfg->comphy_lanes_count = fdtdec_get_int(blob, node,
- "max-lanes", 0);
- if (chip_cfg->comphy_lanes_count <= 0) {
- dev_err(dev, "comphy max lanes is wrong\n");
- return -EINVAL;
- }
-
- chip_cfg->comphy_mux_bitcount = fdtdec_get_int(blob, node,
- "mux-bitcount", 0);
- if (chip_cfg->comphy_mux_bitcount <= 0) {
- dev_err(dev, "comphy mux bit count is wrong\n");
- return -EINVAL;
- }
-
- chip_cfg->comphy_mux_lane_order =
- fdtdec_locate_array(blob, node, "mux-lane-order",
- chip_cfg->comphy_lanes_count);
-
if (device_is_compatible(dev, "marvell,comphy-armada-3700")) {
+ chip_cfg->comphy_init_map = comphy_a3700_init_serdes_map;
chip_cfg->ptr_comphy_chip_init = comphy_a3700_init;
chip_cfg->rx_training = NULL;
}
if (device_is_compatible(dev, "marvell,comphy-cp110")) {
+ chip_cfg->comphy_init_map = comphy_cp110_init_serdes_map;
chip_cfg->ptr_comphy_chip_init = comphy_cp110_init;
chip_cfg->rx_training = comphy_cp110_sfi_rx_training;
}
@@ -141,39 +122,9 @@ static int comphy_probe(struct udevice *dev)
return -ENODEV;
}
- lane = 0;
- fdt_for_each_subnode(subnode, blob, node) {
- /* Skip disabled ports */
- if (!fdtdec_get_is_enabled(blob, subnode))
- continue;
-
- chip_cfg->comphy_map_data[lane].type =
- fdtdec_get_int(blob, subnode, "phy-type",
- COMPHY_TYPE_INVALID);
-
- if (chip_cfg->comphy_map_data[lane].type ==
- COMPHY_TYPE_INVALID) {
- printf("no phy type for lane %d, setting lane as unconnected\n",
- lane + 1);
- continue;
- }
-
- chip_cfg->comphy_map_data[lane].speed =
- fdtdec_get_int(blob, subnode, "phy-speed",
- COMPHY_SPEED_INVALID);
-
- chip_cfg->comphy_map_data[lane].invert =
- fdtdec_get_int(blob, subnode, "phy-invert",
- COMPHY_POLARITY_NO_INVERT);
-
- chip_cfg->comphy_map_data[lane].clk_src =
- fdtdec_get_bool(blob, subnode, "clk-src");
-
- chip_cfg->comphy_map_data[lane].end_point =
- fdtdec_get_bool(blob, subnode, "end_point");
-
- lane++;
- }
+ res = chip_cfg->comphy_init_map(node, chip_cfg);
+ if (res < 0)
+ return res;
res = comphy_update_map(chip_cfg->comphy_map_data, chip_cfg->comphy_lanes_count);
if (res < 0)
diff --git a/drivers/phy/marvell/comphy_core.h b/drivers/phy/marvell/comphy_core.h
index 9bbd7f8f35..d573776c05 100644
--- a/drivers/phy/marvell/comphy_core.h
+++ b/drivers/phy/marvell/comphy_core.h
@@ -32,6 +32,7 @@ struct comphy_mux_data {
struct chip_serdes_phy_config {
struct comphy_mux_data *mux_data;
+ int (*comphy_init_map)(int, struct chip_serdes_phy_config *);
int (*ptr_comphy_chip_init)(struct chip_serdes_phy_config *,
struct comphy_map *);
int (*rx_training)(struct chip_serdes_phy_config *, u32);
@@ -85,9 +86,20 @@ static inline void reg_set16(void __iomem *addr, u16 data, u16 mask)
/* SoC specific init functions */
#ifdef CONFIG_ARMADA_3700
+int comphy_a3700_init_serdes_map(int node, struct chip_serdes_phy_config *cfg);
int comphy_a3700_init(struct chip_serdes_phy_config *ptr_chip_cfg,
struct comphy_map *serdes_map);
#else
+static inline int
+comphy_a3700_init_serdes_map(int node, struct chip_serdes_phy_config *cfg)
+{
+ /*
+ * This function should never be called in this configuration, so
+ * lets return an error here.
+ */
+ return -1;
+}
+
static inline int comphy_a3700_init(struct chip_serdes_phy_config *ptr_chip_cfg,
struct comphy_map *serdes_map)
{
@@ -100,11 +112,22 @@ static inline int comphy_a3700_init(struct chip_serdes_phy_config *ptr_chip_cfg,
#endif
#ifdef CONFIG_ARMADA_8K
+int comphy_cp110_init_serdes_map(int node, struct chip_serdes_phy_config *cfg);
int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
struct comphy_map *serdes_map);
int comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg,
u32 lane);
#else
+static inline int
+comphy_cp110_init_serdes_map(int node, struct chip_serdes_phy_config *cfg)
+{
+ /*
+ * This function should never be called in this configuration, so
+ * lets return an error here.
+ */
+ return -1;
+}
+
static inline int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
struct comphy_map *serdes_map)
{
diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c
index 4fe2dfcdd1..e063b51c6d 100644
--- a/drivers/phy/marvell/comphy_cp110.c
+++ b/drivers/phy/marvell/comphy_cp110.c
@@ -554,6 +554,64 @@ void comphy_dedicated_phys_init(void)
debug_exit();
}
+int comphy_cp110_init_serdes_map(int node, struct chip_serdes_phy_config *cfg)
+{
+ int lane, subnode;
+
+ cfg->comphy_lanes_count = fdtdec_get_int(gd->fdt_blob, node,
+ "max-lanes", 0);
+ if (cfg->comphy_lanes_count <= 0) {
+ printf("comphy max lanes is wrong\n");
+ return -EINVAL;
+ }
+
+ cfg->comphy_mux_bitcount = fdtdec_get_int(gd->fdt_blob, node,
+ "mux-bitcount", 0);
+ if (cfg->comphy_mux_bitcount <= 0) {
+ printf("comphy mux bit count is wrong\n");
+ return -EINVAL;
+ }
+
+ cfg->comphy_mux_lane_order = fdtdec_locate_array(gd->fdt_blob, node,
+ "mux-lane-order",
+ cfg->comphy_lanes_count);
+
+ lane = 0;
+ fdt_for_each_subnode(subnode, gd->fdt_blob, node) {
+ /* Skip disabled ports */
+ if (!fdtdec_get_is_enabled(gd->fdt_blob, subnode))
+ continue;
+
+ cfg->comphy_map_data[lane].type =
+ fdtdec_get_int(gd->fdt_blob, subnode, "phy-type",
+ COMPHY_TYPE_INVALID);
+
+ if (cfg->comphy_map_data[lane].type == COMPHY_TYPE_INVALID) {
+ printf("no phy type for lane %d, setting lane as unconnected\n",
+ lane + 1);
+ continue;
+ }
+
+ cfg->comphy_map_data[lane].speed =
+ fdtdec_get_int(gd->fdt_blob, subnode, "phy-speed",
+ COMPHY_SPEED_INVALID);
+
+ cfg->comphy_map_data[lane].invert =
+ fdtdec_get_int(gd->fdt_blob, subnode, "phy-invert",
+ COMPHY_POLARITY_NO_INVERT);
+
+ cfg->comphy_map_data[lane].clk_src =
+ fdtdec_get_bool(gd->fdt_blob, subnode, "clk-src");
+
+ cfg->comphy_map_data[lane].end_point =
+ fdtdec_get_bool(gd->fdt_blob, subnode, "end_point");
+
+ lane++;
+ }
+
+ return 0;
+}
+
int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
struct comphy_map *serdes_map)
{
diff --git a/drivers/serial/serial_mvebu_a3700.c b/drivers/serial/serial_mvebu_a3700.c
index 6bca8e4b7e..8c3c10c667 100644
--- a/drivers/serial/serial_mvebu_a3700.c
+++ b/drivers/serial/serial_mvebu_a3700.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ * Copyright (C) 2021 Pali Rohár <pali@kernel.org>
*/
#include <common.h>
generated by cgit v1.2.3 (git 2.39.1) at 2025-06-02 03:54:26 +0000