diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/sifive/Kconfig | 8 | ||||
| -rw-r--r-- | drivers/clk/sifive/Makefile | 4 | ||||
| -rw-r--r-- | drivers/clk/sifive/fu540-prci.c | 769 | ||||
| -rw-r--r-- | drivers/clk/sifive/fu540-prci.h | 22 | ||||
| -rw-r--r-- | drivers/clk/sifive/fu740-prci.c | 158 | ||||
| -rw-r--r-- | drivers/clk/sifive/fu740-prci.h | 22 | ||||
| -rw-r--r-- | drivers/clk/sifive/sifive-prci.c | 733 | ||||
| -rw-r--r-- | drivers/clk/sifive/sifive-prci.h | 323 | ||||
| -rw-r--r-- | drivers/pci/Kconfig | 10 | ||||
| -rw-r--r-- | drivers/pci/Makefile | 1 | ||||
| -rw-r--r-- | drivers/pci/pcie_dw_common.c | 54 | ||||
| -rw-r--r-- | drivers/pci/pcie_dw_sifive.c | 507 | ||||
| -rw-r--r-- | drivers/ram/sifive/Kconfig | 8 | ||||
| -rw-r--r-- | drivers/ram/sifive/Makefile | 2 | ||||
| -rw-r--r-- | drivers/ram/sifive/sifive_ddr.c (renamed from drivers/ram/sifive/fu540_ddr.c) | 89 | ||||
| -rw-r--r-- | drivers/reset/Kconfig | 2 |
16 files changed, 1884 insertions, 828 deletions
diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig index c4d0a1f9b1..20fc004b59 100644 --- a/drivers/clk/sifive/Kconfig +++ b/drivers/clk/sifive/Kconfig @@ -6,11 +6,11 @@ config CLK_SIFIVE help SoC drivers for SiFive Linux-capable SoCs. -config CLK_SIFIVE_FU540_PRCI - bool "PRCI driver for SiFive FU540 SoCs" +config CLK_SIFIVE_PRCI + bool "PRCI driver for SiFive SoCs" depends on CLK_SIFIVE select CLK_ANALOGBITS_WRPLL_CLN28HPC help Supports the Power Reset Clock interface (PRCI) IP block found in - FU540 SoCs. If this kernel is meant to run on a SiFive FU540 SoC, - enable this driver. + FU540/FU740 SoCs. If this kernel is meant to run on a SiFive FU540/ + FU740 SoCs, enable this driver. diff --git a/drivers/clk/sifive/Makefile b/drivers/clk/sifive/Makefile index b224279afb..51348b1ddc 100644 --- a/drivers/clk/sifive/Makefile +++ b/drivers/clk/sifive/Makefile @@ -1,3 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -obj-$(CONFIG_CLK_SIFIVE_FU540_PRCI) += fu540-prci.o +obj-y += sifive-prci.o + +obj-$(CONFIG_CLK_SIFIVE_PRCI) += fu540-prci.o fu740-prci.o diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c index b3882d0b77..ceb2c6fab0 100644 --- a/drivers/clk/sifive/fu540-prci.c +++ b/drivers/clk/sifive/fu540-prci.c @@ -5,6 +5,8 @@ * Copyright (C) 2018 SiFive, Inc. * Wesley Terpstra * Paul Walmsley + * Zong Li + * Pragnesh Patel * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -15,632 +17,48 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - * The FU540 PRCI implements clock and reset control for the SiFive - * FU540-C000 chip. This driver assumes that it has sole control - * over all PRCI resources. - * - * This driver is based on the PRCI driver written by Wesley Terpstra. - * - * Refer, commit 999529edf517ed75b56659d456d221b2ee56bb60 of: - * https://github.com/riscv/riscv-linux - * * References: * - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset" */ -#include <common.h> -#include <clk-uclass.h> -#include <clk.h> -#include <div64.h> -#include <dm.h> -#include <dm/device.h> -#include <dm/device_compat.h> -#include <dm/uclass.h> #include <dt-bindings/clock/sifive-fu540-prci.h> -#include <dt-bindings/reset/sifive-fu540-prci.h> -#include <errno.h> -#include <reset-uclass.h> -#include <asm/io.h> -#include <asm/arch/reset.h> -#include <linux/delay.h> -#include <linux/err.h> -#include <linux/math64.h> -#include <linux/clk/analogbits-wrpll-cln28hpc.h> - -/* - * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects: - * hfclk and rtcclk - */ -#define EXPECTED_CLK_PARENT_COUNT 2 - -/* - * Register offsets and bitmasks - */ - -/* COREPLLCFG0 */ -#define PRCI_COREPLLCFG0_OFFSET 0x4 -#define PRCI_COREPLLCFG0_DIVR_SHIFT 0 -#define PRCI_COREPLLCFG0_DIVR_MASK (0x3f << PRCI_COREPLLCFG0_DIVR_SHIFT) -#define PRCI_COREPLLCFG0_DIVF_SHIFT 6 -#define PRCI_COREPLLCFG0_DIVF_MASK (0x1ff << PRCI_COREPLLCFG0_DIVF_SHIFT) -#define PRCI_COREPLLCFG0_DIVQ_SHIFT 15 -#define PRCI_COREPLLCFG0_DIVQ_MASK (0x7 << PRCI_COREPLLCFG0_DIVQ_SHIFT) -#define PRCI_COREPLLCFG0_RANGE_SHIFT 18 -#define PRCI_COREPLLCFG0_RANGE_MASK (0x7 << PRCI_COREPLLCFG0_RANGE_SHIFT) -#define PRCI_COREPLLCFG0_BYPASS_SHIFT 24 -#define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT) -#define PRCI_COREPLLCFG0_FSE_SHIFT 25 -#define PRCI_COREPLLCFG0_FSE_MASK (0x1 << PRCI_COREPLLCFG0_FSE_SHIFT) -#define PRCI_COREPLLCFG0_LOCK_SHIFT 31 -#define PRCI_COREPLLCFG0_LOCK_MASK (0x1 << PRCI_COREPLLCFG0_LOCK_SHIFT) - -/* COREPLLCFG1 */ -#define PRCI_COREPLLCFG1_OFFSET 0x8 -#define PRCI_COREPLLCFG1_CKE_SHIFT 31 -#define PRCI_COREPLLCFG1_CKE_MASK (0x1 << PRCI_COREPLLCFG1_CKE_SHIFT) - -/* DDRPLLCFG0 */ -#define PRCI_DDRPLLCFG0_OFFSET 0xc -#define PRCI_DDRPLLCFG0_DIVR_SHIFT 0 -#define PRCI_DDRPLLCFG0_DIVR_MASK (0x3f << PRCI_DDRPLLCFG0_DIVR_SHIFT) -#define PRCI_DDRPLLCFG0_DIVF_SHIFT 6 -#define PRCI_DDRPLLCFG0_DIVF_MASK (0x1ff << PRCI_DDRPLLCFG0_DIVF_SHIFT) -#define PRCI_DDRPLLCFG0_DIVQ_SHIFT 15 -#define PRCI_DDRPLLCFG0_DIVQ_MASK (0x7 << PRCI_DDRPLLCFG0_DIVQ_SHIFT) -#define PRCI_DDRPLLCFG0_RANGE_SHIFT 18 -#define PRCI_DDRPLLCFG0_RANGE_MASK (0x7 << PRCI_DDRPLLCFG0_RANGE_SHIFT) -#define PRCI_DDRPLLCFG0_BYPASS_SHIFT 24 -#define PRCI_DDRPLLCFG0_BYPASS_MASK (0x1 << PRCI_DDRPLLCFG0_BYPASS_SHIFT) -#define PRCI_DDRPLLCFG0_FSE_SHIFT 25 -#define PRCI_DDRPLLCFG0_FSE_MASK (0x1 << PRCI_DDRPLLCFG0_FSE_SHIFT) -#define PRCI_DDRPLLCFG0_LOCK_SHIFT 31 -#define PRCI_DDRPLLCFG0_LOCK_MASK (0x1 << PRCI_DDRPLLCFG0_LOCK_SHIFT) - -/* DDRPLLCFG1 */ -#define PRCI_DDRPLLCFG1_OFFSET 0x10 -#define PRCI_DDRPLLCFG1_CKE_SHIFT 31 -#define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT) - -/* GEMGXLPLLCFG0 */ -#define PRCI_GEMGXLPLLCFG0_OFFSET 0x1c -#define PRCI_GEMGXLPLLCFG0_DIVR_SHIFT 0 -#define PRCI_GEMGXLPLLCFG0_DIVR_MASK \ - (0x3f << PRCI_GEMGXLPLLCFG0_DIVR_SHIFT) -#define PRCI_GEMGXLPLLCFG0_DIVF_SHIFT 6 -#define PRCI_GEMGXLPLLCFG0_DIVF_MASK \ - (0x1ff << PRCI_GEMGXLPLLCFG0_DIVF_SHIFT) -#define PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT 15 -#define PRCI_GEMGXLPLLCFG0_DIVQ_MASK (0x7 << PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT) -#define PRCI_GEMGXLPLLCFG0_RANGE_SHIFT 18 -#define PRCI_GEMGXLPLLCFG0_RANGE_MASK \ - (0x7 << PRCI_GEMGXLPLLCFG0_RANGE_SHIFT) -#define PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT 24 -#define PRCI_GEMGXLPLLCFG0_BYPASS_MASK \ - (0x1 << PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT) -#define PRCI_GEMGXLPLLCFG0_FSE_SHIFT 25 -#define PRCI_GEMGXLPLLCFG0_FSE_MASK \ - (0x1 << PRCI_GEMGXLPLLCFG0_FSE_SHIFT) -#define PRCI_GEMGXLPLLCFG0_LOCK_SHIFT 31 -#define PRCI_GEMGXLPLLCFG0_LOCK_MASK (0x1 << PRCI_GEMGXLPLLCFG0_LOCK_SHIFT) - -/* GEMGXLPLLCFG1 */ -#define PRCI_GEMGXLPLLCFG1_OFFSET 0x20 -#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 31 -#define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT) - -/* CORECLKSEL */ -#define PRCI_CORECLKSEL_OFFSET 0x24 -#define PRCI_CORECLKSEL_CORECLKSEL_SHIFT 0 -#define PRCI_CORECLKSEL_CORECLKSEL_MASK \ - (0x1 << PRCI_CORECLKSEL_CORECLKSEL_SHIFT) - -/* DEVICESRESETREG */ -#define PRCI_DEVICESRESETREG_OFFSET 0x28 -#define PRCI_DEVICERESETCNT 5 - -#define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK \ - (0x1 << PRCI_RST_DDR_CTRL_N) -#define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK \ - (0x1 << PRCI_RST_DDR_AXI_N) -#define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK \ - (0x1 << PRCI_RST_DDR_AHB_N) -#define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK \ - (0x1 << PRCI_RST_DDR_PHY_N) -#define PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK \ - (0x1 << PRCI_RST_GEMGXL_N) - -/* CLKMUXSTATUSREG */ -#define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c -#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1 -#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \ - (0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT) - -/* PROCMONCFG */ -#define PRCI_PROCMONCFG_OFFSET 0xF0 -#define PRCI_PROCMONCFG_CORE_CLOCK_SHIFT 24 -#define PRCI_PROCMONCFG_CORE_CLOCK_MASK \ - (0x1 << PRCI_PROCMONCFG_CORE_CLOCK_SHIFT) - -/* - * Private structures - */ - -/** - * struct __prci_data - per-device-instance data - * @va: base virtual address of the PRCI IP block - * @parent: parent clk instance - * - * PRCI per-device instance data - */ -struct __prci_data { - void *va; - struct clk parent_hfclk; - struct clk parent_rtcclk; -}; - -/** - * struct __prci_wrpll_data - WRPLL configuration and integration data - * @c: WRPLL current configuration record - * @enable_bypass: fn ptr to code to bypass the WRPLL (if applicable; else NULL) - * @disable_bypass: fn ptr to code to not bypass the WRPLL (or NULL) - * @cfg0_offs: WRPLL CFG0 register offset (in bytes) from the PRCI base address - * @cfg1_offs: WRPLL CFG1 register offset (in bytes) from the PRCI base address - * @release_reset: fn ptr to code to release clock reset - * - * @enable_bypass and @disable_bypass are used for WRPLL instances - * that contain a separate external glitchless clock mux downstream - * from the PLL. The WRPLL internal bypass mux is not glitchless. - */ -struct __prci_wrpll_data { - struct wrpll_cfg c; - void (*enable_bypass)(struct __prci_data *pd); - void (*disable_bypass)(struct __prci_data *pd); - u8 cfg0_offs; - u8 cfg1_offs; - void (*release_reset)(struct __prci_data *pd); -}; - -struct __prci_clock; - -/* struct __prci_clock_ops - clock operations */ -struct __prci_clock_ops { - int (*set_rate)(struct __prci_clock *pc, - unsigned long rate, - unsigned long parent_rate); - unsigned long (*round_rate)(struct __prci_clock *pc, - unsigned long rate, - unsigned long *parent_rate); - unsigned long (*recalc_rate)(struct __prci_clock *pc, - unsigned long parent_rate); - int (*enable_clk)(struct __prci_clock *pc, bool enable); -}; - -/** - * struct __prci_clock - describes a clock device managed by PRCI - * @name: user-readable clock name string - should match the manual - * @parent_name: parent name for this clock - * @ops: struct __prci_clock_ops for control - * @pwd: WRPLL-specific data, associated with this clock (if not NULL) - * @pd: PRCI-specific data associated with this clock (if not NULL) - * - * PRCI clock data. Used by the PRCI driver to register PRCI-provided - * clocks to the Linux clock infrastructure. - */ -struct __prci_clock { - const char *name; - const char *parent_name; - const struct __prci_clock_ops *ops; - struct __prci_wrpll_data *pwd; - struct __prci_data *pd; -}; - -/* - * Private functions - */ - -/** - * __prci_readl() - read from a PRCI register - * @pd: PRCI context - * @offs: register offset to read from (in bytes, from PRCI base address) - * - * Read the register located at offset @offs from the base virtual - * address of the PRCI register target described by @pd, and return - * the value to the caller. - * - * Context: Any context. - * - * Return: the contents of the register described by @pd and @offs. - */ -static u32 __prci_readl(struct __prci_data *pd, u32 offs) -{ - return readl(pd->va + offs); -} - -static void __prci_writel(u32 v, u32 offs, struct __prci_data *pd) -{ - writel(v, pd->va + offs); -} - -/* WRPLL-related private functions */ - -/** - * __prci_wrpll_unpack() - unpack WRPLL configuration registers into parameters - * @c: ptr to a struct wrpll_cfg record to write config into - * @r: value read from the PRCI PLL configuration register - * - * Given a value @r read from an FU540 PRCI PLL configuration register, - * split it into fields and populate it into the WRPLL configuration record - * pointed to by @c. - * - * The COREPLLCFG0 macros are used below, but the other *PLLCFG0 macros - * have the same register layout. - * - * Context: Any context. - */ -static void __prci_wrpll_unpack(struct wrpll_cfg *c, u32 r) -{ - u32 v; - - v = r & PRCI_COREPLLCFG0_DIVR_MASK; - v >>= PRCI_COREPLLCFG0_DIVR_SHIFT; - c->divr = v; - - v = r & PRCI_COREPLLCFG0_DIVF_MASK; - v >>= PRCI_COREPLLCFG0_DIVF_SHIFT; - c->divf = v; - - v = r & PRCI_COREPLLCFG0_DIVQ_MASK; - v >>= PRCI_COREPLLCFG0_DIVQ_SHIFT; - c->divq = v; - - v = r & PRCI_COREPLLCFG0_RANGE_MASK; - v >>= PRCI_COREPLLCFG0_RANGE_SHIFT; - c->range = v; - - c->flags &= (WRPLL_FLAGS_INT_FEEDBACK_MASK | - WRPLL_FLAGS_EXT_FEEDBACK_MASK); - - /* external feedback mode not supported */ - c->flags |= WRPLL_FLAGS_INT_FEEDBACK_MASK; -} - -/** - * __prci_wrpll_pack() - pack PLL configuration parameters into a register value - * @c: pointer to a struct wrpll_cfg record containing the PLL's cfg - * - * Using a set of WRPLL configuration values pointed to by @c, - * assemble a PRCI PLL configuration register value, and return it to - * the caller. - * - * Context: Any context. Caller must ensure that the contents of the - * record pointed to by @c do not change during the execution - * of this function. - * - * Returns: a value suitable for writing into a PRCI PLL configuration - * register - */ -static u32 __prci_wrpll_pack(const struct wrpll_cfg *c) -{ - u32 r = 0; - - r |= c->divr << PRCI_COREPLLCFG0_DIVR_SHIFT; - r |= c->divf << PRCI_COREPLLCFG0_DIVF_SHIFT; - r |= c->divq << PRCI_COREPLLCFG0_DIVQ_SHIFT; - r |= c->range << PRCI_COREPLLCFG0_RANGE_SHIFT; - - /* external feedback mode not supported */ - r |= PRCI_COREPLLCFG0_FSE_MASK; - - return r; -} - -/** - * __prci_wrpll_read_cfg0() - read the WRPLL configuration from the PRCI - * @pd: PRCI context - * @pwd: PRCI WRPLL metadata - * - * Read the current configuration of the PLL identified by @pwd from - * the PRCI identified by @pd, and store it into the local configuration - * cache in @pwd. - * - * Context: Any context. Caller must prevent the records pointed to by - * @pd and @pwd from changing during execution. - */ -static void __prci_wrpll_read_cfg0(struct __prci_data *pd, - struct __prci_wrpll_data *pwd) -{ - __prci_wrpll_unpack(&pwd->c, __prci_readl(pd, pwd->cfg0_offs)); -} - -/** - * __prci_wrpll_write_cfg0() - write WRPLL configuration into the PRCI - * @pd: PRCI context - * @pwd: PRCI WRPLL metadata - * @c: WRPLL configuration record to write - * - * Write the WRPLL configuration described by @c into the WRPLL - * configuration register identified by @pwd in the PRCI instance - * described by @c. Make a cached copy of the WRPLL's current - * configuration so it can be used by other code. - * - * Context: Any context. Caller must prevent the records pointed to by - * @pd and @pwd from changing during execution. - */ -static void __prci_wrpll_write_cfg0(struct __prci_data *pd, - struct __prci_wrpll_data *pwd, - struct wrpll_cfg *c) -{ - __prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd); - - memcpy(&pwd->c, c, sizeof(*c)); -} - -/** - * __prci_wrpll_write_cfg1() - write Clock enable/disable configuration - * into the PRCI - * @pd: PRCI context - * @pwd: PRCI WRPLL metadata - * @enable: Clock enable or disable value - */ -static void __prci_wrpll_write_cfg1(struct __prci_data *pd, - struct __prci_wrpll_data *pwd, - u32 enable) -{ - __prci_writel(enable, pwd->cfg1_offs, pd); -} - -/* Core clock mux control */ - -/** - * __prci_coreclksel_use_hfclk() - switch the CORECLK mux to output HFCLK - * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg - * - * Switch the CORECLK mux to the HFCLK input source; return once complete. - * - * Context: Any context. Caller must prevent concurrent changes to the - * PRCI_CORECLKSEL_OFFSET register. - */ -static void __prci_coreclksel_use_hfclk(struct __prci_data *pd) -{ - u32 r; - - r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); - r |= PRCI_CORECLKSEL_CORECLKSEL_MASK; - __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd); - - r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */ -} - -/** - * __prci_coreclksel_use_corepll() - switch the CORECLK mux to output COREPLL - * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg - * - * Switch the CORECLK mux to the PLL output clock; return once complete. - * - * Context: Any context. Caller must prevent concurrent changes to the - * PRCI_CORECLKSEL_OFFSET register. - */ -static void __prci_coreclksel_use_corepll(struct __prci_data *pd) -{ - u32 r; - - r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); - r &= ~PRCI_CORECLKSEL_CORECLKSEL_MASK; - __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd); - - r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */ -} - -static unsigned long sifive_fu540_prci_wrpll_recalc_rate( - struct __prci_clock *pc, - unsigned long parent_rate) -{ - struct __prci_wrpll_data *pwd = pc->pwd; - return wrpll_calc_output_rate(&pwd->c, parent_rate); -} - -static unsigned long sifive_fu540_prci_wrpll_round_rate( - struct __prci_clock *pc, - unsigned long rate, - unsigned long *parent_rate) -{ - struct __prci_wrpll_data *pwd = pc->pwd; - struct wrpll_cfg c; - - memcpy(&c, &pwd->c, sizeof(c)); - - wrpll_configure_for_rate(&c, rate, *parent_rate); - - return wrpll_calc_output_rate(&c, *parent_rate); -} - -static int sifive_fu540_prci_wrpll_set_rate(struct __prci_clock *pc, - unsigned long rate, - unsigned long parent_rate) -{ - struct __prci_wrpll_data *pwd = pc->pwd; - struct __prci_data *pd = pc->pd; - int r; - - r = wrpll_configure_for_rate(&pwd->c, rate, parent_rate); - if (r) - return r; - - if (pwd->enable_bypass) - pwd->enable_bypass(pd); - - __prci_wrpll_write_cfg0(pd, pwd, &pwd->c); - - udelay(wrpll_calc_max_lock_us(&pwd->c)); - - if (pwd->disable_bypass) - pwd->disable_bypass(pd); - - return 0; -} - -static int sifive_fu540_prci_clock_enable(struct __prci_clock *pc, bool enable) -{ - struct __prci_wrpll_data *pwd = pc->pwd; - struct __prci_data *pd = pc->pd; - - if (enable) { - __prci_wrpll_write_cfg1(pd, pwd, PRCI_COREPLLCFG1_CKE_MASK); - - if (pwd->release_reset) - pwd->release_reset(pd); - } else { - u32 r; - - r = __prci_readl(pd, pwd->cfg1_offs); - r &= ~PRCI_COREPLLCFG1_CKE_MASK; - - __prci_wrpll_write_cfg1(pd, pwd, r); - } - - return 0; -} - -static const struct __prci_clock_ops sifive_fu540_prci_wrpll_clk_ops = { - .set_rate = sifive_fu540_prci_wrpll_set_rate, - .round_rate = sifive_fu540_prci_wrpll_round_rate, - .recalc_rate = sifive_fu540_prci_wrpll_recalc_rate, - .enable_clk = sifive_fu540_prci_clock_enable, -}; - -/* TLCLKSEL clock integration */ - -static unsigned long sifive_fu540_prci_tlclksel_recalc_rate( - struct __prci_clock *pc, - unsigned long parent_rate) -{ - struct __prci_data *pd = pc->pd; - u32 v; - u8 div; - - v = __prci_readl(pd, PRCI_CLKMUXSTATUSREG_OFFSET); - v &= PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK; - div = v ? 1 : 2; - - return div_u64(parent_rate, div); -} - -static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = { - .recalc_rate = sifive_fu540_prci_tlclksel_recalc_rate, -}; - -static int __prci_consumer_reset(const char *rst_name, bool trigger) -{ - struct udevice *dev; - struct reset_ctl rst_sig; - int ret; - - ret = uclass_get_device_by_driver(UCLASS_RESET, - DM_DRIVER_GET(sifive_reset), - &dev); - if (ret) { - dev_err(dev, "Reset driver not found: %d\n", ret); - return ret; - } - - ret = reset_get_by_name(dev, rst_name, &rst_sig); - if (ret) { - dev_err(dev, "failed to get %s reset\n", rst_name); - return ret; - } - - if (reset_valid(&rst_sig)) { - if (trigger) - ret = reset_deassert(&rst_sig); - else - ret = reset_assert(&rst_sig); - if (ret) { - dev_err(dev, "failed to trigger reset id = %ld\n", - rst_sig.id); - return ret; - } - } - - return ret; -} - -/** - * __prci_ddr_release_reset() - Release DDR reset - * @pd: struct __prci_data * for the PRCI containing the DDRCLK mux reg - * - */ -static void __prci_ddr_release_reset(struct __prci_data *pd) -{ - /* Release DDR ctrl reset */ - __prci_consumer_reset("ddr_ctrl", true); - - /* HACK to get the '1 full controller clock cycle'. */ - asm volatile ("fence"); - - /* Release DDR AXI reset */ - __prci_consumer_reset("ddr_axi", true); - - /* Release DDR AHB reset */ - __prci_consumer_reset("ddr_ahb", true); - - /* Release DDR PHY reset */ - __prci_consumer_reset("ddr_phy", true); - - /* HACK to get the '1 full controller clock cycle'. */ - asm volatile ("fence"); - - /* - * These take like 16 cycles to actually propagate. We can't go sending - * stuff before they come out of reset. So wait. - */ - for (int i = 0; i < 256; i++) - asm volatile ("nop"); -} - -/** - * __prci_ethernet_release_reset() - Release ethernet reset - * @pd: struct __prci_data * for the PRCI containing the Ethernet CLK mux reg - * - */ -static void __prci_ethernet_release_reset(struct __prci_data *pd) -{ - /* Release GEMGXL reset */ - __prci_consumer_reset("gemgxl_reset", true); - - /* Procmon => core clock */ - __prci_writel(PRCI_PROCMONCFG_CORE_CLOCK_MASK, PRCI_PROCMONCFG_OFFSET, - pd); -} - -/* - * PRCI integration data for each WRPLL instance - */ +#include "sifive-prci.h" +/* PRCI integration data for each WRPLL instance */ static struct __prci_wrpll_data __prci_corepll_data = { .cfg0_offs = PRCI_COREPLLCFG0_OFFSET, .cfg1_offs = PRCI_COREPLLCFG1_OFFSET, - .enable_bypass = __prci_coreclksel_use_hfclk, - .disable_bypass = __prci_coreclksel_use_corepll, + .enable_bypass = sifive_prci_coreclksel_use_hfclk, + .disable_bypass = sifive_prci_coreclksel_use_corepll, }; static struct __prci_wrpll_data __prci_ddrpll_data = { .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET, .cfg1_offs = PRCI_DDRPLLCFG1_OFFSET, - .release_reset = __prci_ddr_release_reset, + .release_reset = sifive_prci_ddr_release_reset, }; static struct __prci_wrpll_data __prci_gemgxlpll_data = { .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET, .cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET, - .release_reset = __prci_ethernet_release_reset, + .release_reset = sifive_prci_ethernet_release_reset, }; -/* - * List of clock controls provided by the PRCI - */ +/* Linux clock framework integration */ +static const struct __prci_clock_ops sifive_fu540_prci_wrpll_clk_ops = { + .set_rate = sifive_prci_wrpll_set_rate, + .round_rate = sifive_prci_wrpll_round_rate, + .recalc_rate = sifive_prci_wrpll_recalc_rate, + .enable_clk = sifive_prci_clock_enable, +}; -static struct __prci_clock __prci_init_clocks[] = { +static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = { + .recalc_rate = sifive_prci_tlclksel_recalc_rate, +}; + +/* List of clock controls provided by the PRCI */ +struct __prci_clock __prci_init_clocks_fu540[] = { [PRCI_CLK_COREPLL] = { .name = "corepll", .parent_name = "hfclk", @@ -665,148 +83,3 @@ static struct __prci_clock __prci_init_clocks[] = { .ops = &sifive_fu540_prci_tlclksel_clk_ops, }, }; - -static ulong sifive_fu540_prci_parent_rate(struct __prci_clock *pc) -{ - ulong parent_rate; - struct __prci_clock *p; - - if (strcmp(pc->parent_name, "corepll") == 0) { - p = &__prci_init_clocks[PRCI_CLK_COREPLL]; - if (!p->pd || !p->ops->recalc_rate) - return -ENXIO; - - return p->ops->recalc_rate(p, sifive_fu540_prci_parent_rate(p)); - } - - if (strcmp(pc->parent_name, "rtcclk") == 0) - parent_rate = clk_get_rate(&pc->pd->parent_rtcclk); - else - parent_rate = clk_get_rate(&pc->pd->parent_hfclk); - - return parent_rate; -} - -static ulong sifive_fu540_prci_get_rate(struct clk *clk) -{ - struct __prci_clock *pc; - - if (ARRAY_SIZE(__prci_init_clocks) <= clk->id) - return -ENXIO; - - pc = &__prci_init_clocks[clk->id]; - if (!pc->pd || !pc->ops->recalc_rate) - return -ENXIO; - - return pc->ops->recalc_rate(pc, sifive_fu540_prci_parent_rate(pc)); -} - -static ulong sifive_fu540_prci_set_rate(struct clk *clk, ulong rate) -{ - int err; - struct __prci_clock *pc; - - if (ARRAY_SIZE(__prci_init_clocks) <= clk->id) - return -ENXIO; - - pc = &__prci_init_clocks[clk->id]; - if (!pc->pd || !pc->ops->set_rate) - return -ENXIO; - - err = pc->ops->set_rate(pc, rate, sifive_fu540_prci_parent_rate(pc)); - if (err) - return err; - - return rate; -} - -static int sifive_fu540_prci_enable(struct clk *clk) -{ - struct __prci_clock *pc; - int ret = 0; - - if (ARRAY_SIZE(__prci_init_clocks) <= clk->id) - return -ENXIO; - - pc = &__prci_init_clocks[clk->id]; - if (!pc->pd) - return -ENXIO; - - if (pc->ops->enable_clk) - ret = pc->ops->enable_clk(pc, 1); - - return ret; -} - -static int sifive_fu540_prci_disable(struct clk *clk) -{ - struct __prci_clock *pc; - int ret = 0; - - if (ARRAY_SIZE(__prci_init_clocks) <= clk->id) - return -ENXIO; - - pc = &__prci_init_clocks[clk->id]; - if (!pc->pd) - return -ENXIO; - - if (pc->ops->enable_clk) - ret = pc->ops->enable_clk(pc, 0); - - return ret; -} - -static int sifive_fu540_prci_probe(struct udevice *dev) -{ - int i, err; - struct __prci_clock *pc; - struct __prci_data *pd = dev_get_priv(dev); - - pd->va = (void *)dev_read_addr(dev); - if (IS_ERR(pd->va)) - return PTR_ERR(pd->va); - - err = clk_get_by_index(dev, 0, &pd->parent_hfclk); - if (err) - return err; - - err = clk_get_by_index(dev, 1, &pd->parent_rtcclk); - if (err) - return err; - - for (i = 0; i < ARRAY_SIZE(__prci_init_clocks); ++i) { - pc = &__prci_init_clocks[i]; - pc->pd = pd; - if (pc->pwd) - __prci_wrpll_read_cfg0(pd, pc->pwd); - } - - return 0; -} - -static struct clk_ops sifive_fu540_prci_ops = { - .set_rate = sifive_fu540_prci_set_rate, - .get_rate = sifive_fu540_prci_get_rate, - .enable = sifive_fu540_prci_enable, - .disable = sifive_fu540_prci_disable, -}; - -static int sifive_fu540_clk_bind(struct udevice *dev) -{ - return sifive_reset_bind(dev, PRCI_DEVICERESETCNT); -} - -static const struct udevice_id sifive_fu540_prci_ids[] = { - { .compatible = "sifive,fu540-c000-prci" }, - { } -}; - -U_BOOT_DRIVER(sifive_fu540_prci) = { - .name = "sifive-fu540-prci", - .id = UCLASS_CLK, - .of_match = sifive_fu540_prci_ids, - .probe = sifive_fu540_prci_probe, - .ops = &sifive_fu540_prci_ops, - .priv_auto = sizeof(struct __prci_data), - .bind = sifive_fu540_clk_bind, -}; diff --git a/drivers/clk/sifive/fu540-prci.h b/drivers/clk/sifive/fu540-prci.h new file mode 100644 index 0000000000..113301107d --- /dev/null +++ b/drivers/clk/sifive/fu540-prci.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020-2021 SiFive, Inc. + * Zong Li + * Pragnesh Patel + */ + +#ifndef __SIFIVE_CLK_FU540_PRCI_H +#define __SIFIVE_CLK_FU540_PRCI_H + +#include "sifive-prci.h" + +#define NUM_CLOCK_FU540 4 + +extern struct __prci_clock __prci_init_clocks_fu540[NUM_CLOCK_FU540]; + +static const struct prci_clk_desc prci_clk_fu540 = { + .clks = __prci_init_clocks_fu540, + .num_clks = ARRAY_SIZE(__prci_init_clocks_fu540), +}; + +#endif /* __SIFIVE_CLK_FU540_PRCI_H */ diff --git a/drivers/clk/sifive/fu740-prci.c b/drivers/clk/sifive/fu740-prci.c new file mode 100644 index 0000000000..9a642c1c99 --- /dev/null +++ b/drivers/clk/sifive/fu740-prci.c @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018-2021 SiFive, Inc. + * Wesley Terpstra + * Paul Walmsley + * Zong Li + * Pragnesh Patel + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <dt-bindings/clock/sifive-fu740-prci.h> +#include "sifive-prci.h" +#include <asm/io.h> + +int sifive_prci_fu740_pciauxclk_enable(struct __prci_clock *pc, bool enable) +{ + struct __prci_wrpll_data *pwd = pc->pwd; + struct __prci_data *pd = pc->pd; + u32 v; + + if (pwd->cfg1_offs != PRCI_PCIEAUXCFG1_OFFSET) + return -EINVAL; + + v = readl(pd->va + pwd->cfg1_offs); + v = enable ? (v | PRCI_PCIEAUXCFG1_MASK) : (v & ~PRCI_PCIEAUXCFG1_MASK); + writel(v, pd->va + pwd->cfg1_offs); + + return 0; +} + +/* PRCI integration data for each WRPLL instance */ +static struct __prci_wrpll_data __prci_corepll_data = { + .cfg0_offs = PRCI_COREPLLCFG0_OFFSET, + .cfg1_offs = PRCI_COREPLLCFG1_OFFSET, + .enable_bypass = sifive_prci_coreclksel_use_hfclk, + .disable_bypass = sifive_prci_coreclksel_use_final_corepll, +}; + +static struct __prci_wrpll_data __prci_ddrpll_data = { + .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET, + .cfg1_offs = PRCI_DDRPLLCFG1_OFFSET, + .release_reset = sifive_prci_ddr_release_reset, +}; + +static struct __prci_wrpll_data __prci_gemgxlpll_data = { + .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET, + .cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET, + .release_reset = sifive_prci_ethernet_release_reset, +}; + +static struct __prci_wrpll_data __prci_dvfscorepll_data = { + .cfg0_offs = PRCI_DVFSCOREPLLCFG0_OFFSET, + .cfg1_offs = PRCI_DVFSCOREPLLCFG1_OFFSET, + .enable_bypass = sifive_prci_corepllsel_use_corepll, + .disable_bypass = sifive_prci_corepllsel_use_dvfscorepll, +}; + +static struct __prci_wrpll_data __prci_hfpclkpll_data = { + .cfg0_offs = PRCI_HFPCLKPLLCFG0_OFFSET, + .cfg1_offs = PRCI_HFPCLKPLLCFG1_OFFSET, + .enable_bypass = sifive_prci_hfpclkpllsel_use_hfclk, + .disable_bypass = sifive_prci_hfpclkpllsel_use_hfpclkpll, +}; + +static struct __prci_wrpll_data __prci_cltxpll_data = { + .cfg0_offs = PRCI_CLTXPLLCFG0_OFFSET, + .cfg1_offs = PRCI_CLTXPLLCFG1_OFFSET, + .release_reset = sifive_prci_cltx_release_reset, +}; + +static struct __prci_wrpll_data __prci_pcieaux_data = { + .cfg1_offs = PRCI_PCIEAUXCFG1_OFFSET, +}; + +/* Linux clock framework integration */ + +static const struct __prci_clock_ops sifive_fu740_prci_wrpll_clk_ops = { + .set_rate = sifive_prci_wrpll_set_rate, + .round_rate = sifive_prci_wrpll_round_rate, + .recalc_rate = sifive_prci_wrpll_recalc_rate, + .enable_clk = sifive_prci_clock_enable, +}; + +static const struct __prci_clock_ops sifive_fu740_prci_tlclksel_clk_ops = { + .recalc_rate = sifive_prci_tlclksel_recalc_rate, +}; + +static const struct __prci_clock_ops sifive_fu740_prci_hfpclkplldiv_clk_ops = { + .recalc_rate = sifive_prci_hfpclkplldiv_recalc_rate, +}; + +static const struct __prci_clock_ops sifive_fu740_prci_pcieaux_clk_ops = { + .enable_clk = sifive_prci_fu740_pciauxclk_enable, +}; + +/* List of clock controls provided by the PRCI */ +struct __prci_clock __prci_init_clocks_fu740[] = { + [PRCI_CLK_COREPLL] = { + .name = "corepll", + .parent_name = "hfclk", + .ops = &sifive_fu740_prci_wrpll_clk_ops, + .pwd = &__prci_corepll_data, + }, + [PRCI_CLK_DDRPLL] = { + .name = "ddrpll", + .parent_name = "hfclk", + .ops = &sifive_fu740_prci_wrpll_clk_ops, + .pwd = &__prci_ddrpll_data, + }, + [PRCI_CLK_GEMGXLPLL] = { + .name = "gemgxlpll", + .parent_name = "hfclk", + .ops = &sifive_fu740_prci_wrpll_clk_ops, + .pwd = &__prci_gemgxlpll_data, + }, + [PRCI_CLK_DVFSCOREPLL] = { + .name = "dvfscorepll", + .parent_name = "hfclk", + .ops = &sifive_fu740_prci_wrpll_clk_ops, + .pwd = &__prci_dvfscorepll_data, + }, + [PRCI_CLK_HFPCLKPLL] = { + .name = "hfpclkpll", + .parent_name = "hfclk", + .ops = &sifive_fu740_prci_wrpll_clk_ops, + .pwd = &__prci_hfpclkpll_data, + }, + [PRCI_CLK_CLTXPLL] = { + .name = "cltxpll", + .parent_name = "hfclk", + .ops = &sifive_fu740_prci_wrpll_clk_ops, + .pwd = &__prci_cltxpll_data, + }, + [PRCI_CLK_TLCLK] = { + .name = "tlclk", + .parent_name = "corepll", + .ops = &sifive_fu740_prci_tlclksel_clk_ops, + }, + [PRCI_CLK_PCLK] = { + .name = "pclk", + .parent_name = "hfpclkpll", + .ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops, + }, + [PRCI_CLK_PCIEAUX] { + .name = "pciaux", + .parent_name = "", + .ops = &sifive_fu740_prci_pcieaux_clk_ops, + .pwd = &__prci_pcieaux_data, + } +}; diff --git a/drivers/clk/sifive/fu740-prci.h b/drivers/clk/sifive/fu740-prci.h new file mode 100644 index 0000000000..b74f078906 --- /dev/null +++ b/drivers/clk/sifive/fu740-prci.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020-2021 SiFive, Inc. + * Zong Li + * Pragnesh Patel + */ + +#ifndef __SIFIVE_CLK_FU740_PRCI_H +#define __SIFIVE_CLK_FU740_PRCI_H + +#include "sifive-prci.h" + +#define NUM_CLOCK_FU740 9 + +extern struct __prci_clock __prci_init_clocks_fu740[NUM_CLOCK_FU740]; + +static const struct prci_clk_desc prci_clk_fu740 = { + .clks = __prci_init_clocks_fu740, + .num_clks = ARRAY_SIZE(__prci_init_clocks_fu740), +}; + +#endif /* __SIFIVE_CLK_FU740_PRCI_H */ diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c new file mode 100644 index 0000000000..cd1acb9442 --- /dev/null +++ b/drivers/clk/sifive/sifive-prci.c @@ -0,0 +1,733 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018-2021 SiFive, Inc. + * Wesley Terpstra + * Paul Walmsley + * Zong Li + * Pragnesh Patel + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * The PRCI implements clock and reset control for the SiFive chip. + * This driver assumes that it has sole control over all PRCI resources. + * + * This driver is based on the PRCI driver written by Wesley Terpstra: + * https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60 + */ + +#include <common.h> +#include <clk-uclass.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <reset.h> +#include <asm/io.h> +#include <asm/arch/reset.h> +#include <linux/delay.h> +#include <linux/math64.h> +#include <dt-bindings/clock/sifive-fu740-prci.h> + +#include "fu540-prci.h" +#include "fu740-prci.h" + +/* + * Private functions + */ + +/** + * __prci_readl() - read from a PRCI register + * @pd: PRCI context + * @offs: register offset to read from (in bytes, from PRCI base address) + * + * Read the register located at offset @offs from the base virtual + * address of the PRCI register target described by @pd, and return + * the value to the caller. + * + * Context: Any context. + * + * Return: the contents of the register described by @pd and @offs. + */ +static u32 __prci_readl(struct __prci_data *pd, u32 offs) +{ + return readl(pd->va + offs); +} + +static void __prci_writel(u32 v, u32 offs, struct __prci_data *pd) +{ + writel(v, pd->va + offs); +} + +/* WRPLL-related private functions */ + +/** + * __prci_wrpll_unpack() - unpack WRPLL configuration registers into parameters + * @c: ptr to a struct wrpll_cfg record to write config into + * @r: value read from the PRCI PLL configuration register + * + * Given a value @r read from an FU540 PRCI PLL configuration register, + * split it into fields and populate it into the WRPLL configuration record + * pointed to by @c. + * + * The COREPLLCFG0 macros are used below, but the other *PLLCFG0 macros + * have the same register layout. + * + * Context: Any context. + */ +static void __prci_wrpll_unpack(struct wrpll_cfg *c, u32 r) +{ + u32 v; + + v = r & PRCI_COREPLLCFG0_DIVR_MASK; + v >>= PRCI_COREPLLCFG0_DIVR_SHIFT; + c->divr = v; + + v = r & PRCI_COREPLLCFG0_DIVF_MASK; + v >>= PRCI_COREPLLCFG0_DIVF_SHIFT; + c->divf = v; + + v = r & PRCI_COREPLLCFG0_DIVQ_MASK; + v >>= PRCI_COREPLLCFG0_DIVQ_SHIFT; + c->divq = v; + + v = r & PRCI_COREPLLCFG0_RANGE_MASK; + v >>= PRCI_COREPLLCFG0_RANGE_SHIFT; + c->range = v; + + c->flags &= (WRPLL_FLAGS_INT_FEEDBACK_MASK | + WRPLL_FLAGS_EXT_FEEDBACK_MASK); + + /* external feedback mode not supported */ + c->flags |= WRPLL_FLAGS_INT_FEEDBACK_MASK; +} + +/** + * __prci_wrpll_pack() - pack PLL configuration parameters into a register value + * @c: pointer to a struct wrpll_cfg record containing the PLL's cfg + * + * Using a set of WRPLL configuration values pointed to by @c, + * assemble a PRCI PLL configuration register value, and return it to + * the caller. + * + * Context: Any context. Caller must ensure that the contents of the + * record pointed to by @c do not change during the execution + * of this function. + * + * Returns: a value suitable for writing into a PRCI PLL configuration + * register + */ +static u32 __prci_wrpll_pack(const struct wrpll_cfg *c) +{ + u32 r = 0; + + r |= c->divr << PRCI_COREPLLCFG0_DIVR_SHIFT; + r |= c->divf << PRCI_COREPLLCFG0_DIVF_SHIFT; + r |= c->divq << PRCI_COREPLLCFG0_DIVQ_SHIFT; + r |= c->range << PRCI_COREPLLCFG0_RANGE_SHIFT; + + /* external feedback mode not supported */ + r |= PRCI_COREPLLCFG0_FSE_MASK; + + return r; +} + +/** + * __prci_wrpll_read_cfg0() - read the WRPLL configuration from the PRCI + * @pd: PRCI context + * @pwd: PRCI WRPLL metadata + * + * Read the current configuration of the PLL identified by @pwd from + * the PRCI identified by @pd, and store it into the local configuration + * cache in @pwd. + * + * Context: Any context. Caller must prevent the records pointed to by + * @pd and @pwd from changing during execution. + */ +static void __prci_wrpll_read_cfg0(struct __prci_data *pd, + struct __prci_wrpll_data *pwd) +{ + __prci_wrpll_unpack(&pwd->c, __prci_readl(pd, pwd->cfg0_offs)); +} + +/** + * __prci_wrpll_write_cfg0() - write WRPLL configuration into the PRCI + * @pd: PRCI context + * @pwd: PRCI WRPLL metadata + * @c: WRPLL configuration record to write + * + * Write the WRPLL configuration described by @c into the WRPLL + * configuration register identified by @pwd in the PRCI instance + * described by @c. Make a cached copy of the WRPLL's current + * configuration so it can be used by other code. + * + * Context: Any context. Caller must prevent the records pointed to by + * @pd and @pwd from changing during execution. + */ +static void __prci_wrpll_write_cfg0(struct __prci_data *pd, + struct __prci_wrpll_data *pwd, + struct wrpll_cfg *c) +{ + __prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd); + + memcpy(&pwd->c, c, sizeof(*c)); +} + +/** + * __prci_wrpll_write_cfg1() - write Clock enable/disable configuration + * into the PRCI + * @pd: PRCI context + * @pwd: PRCI WRPLL metadata + * @enable: Clock enable or disable value + */ +static void __prci_wrpll_write_cfg1(struct __prci_data *pd, + struct __prci_wrpll_data *pwd, + u32 enable) +{ + __prci_writel(enable, pwd->cfg1_offs, pd); +} + +unsigned long sifive_prci_wrpll_recalc_rate(struct __prci_clock *pc, + unsigned long parent_rate) +{ + struct __prci_wrpll_data *pwd = pc->pwd; + + return wrpll_calc_output_rate(&pwd->c, parent_rate); +} + +unsigned long sifive_prci_wrpll_round_rate(struct __prci_clock *pc, + unsigned long rate, + unsigned long *parent_rate) +{ + struct __prci_wrpll_data *pwd = pc->pwd; + struct wrpll_cfg c; + + memcpy(&c, &pwd->c, sizeof(c)); + + wrpll_configure_for_rate(&c, rate, *parent_rate); + + return wrpll_calc_output_rate(&c, *parent_rate); +} + +int sifive_prci_wrpll_set_rate(struct __prci_clock *pc, + unsigned long rate, + unsigned long parent_rate) +{ + struct __prci_wrpll_data *pwd = pc->pwd; + struct __prci_data *pd = pc->pd; + int r; + + r = wrpll_configure_for_rate(&pwd->c, rate, parent_rate); + if (r) + return r; + + if (pwd->enable_bypass) + pwd->enable_bypass(pd); + + __prci_wrpll_write_cfg0(pd, pwd, &pwd->c); + + udelay(wrpll_calc_max_lock_us(&pwd->c)); + + return 0; +} + +int sifive_prci_clock_enable(struct __prci_clock *pc, bool enable) +{ + struct __prci_wrpll_data *pwd = pc->pwd; + struct __prci_data *pd = pc->pd; + + if (enable) { + __prci_wrpll_write_cfg1(pd, pwd, PRCI_COREPLLCFG1_CKE_MASK); + + if (pwd->disable_bypass) + pwd->disable_bypass(pd); + + if (pwd->release_reset) + pwd->release_reset(pd); + } else { + u32 r; + + if (pwd->enable_bypass) + pwd->enable_bypass(pd); + + r = __prci_readl(pd, pwd->cfg1_offs); + r &= ~PRCI_COREPLLCFG1_CKE_MASK; + + __prci_wrpll_write_cfg1(pd, pwd, r); + } + + return 0; +} + +/* TLCLKSEL clock integration */ + +unsigned long sifive_prci_tlclksel_recalc_rate(struct __prci_clock *pc, + unsigned long parent_rate) +{ + struct __prci_data *pd = pc->pd; + u32 v; + u8 div; + + v = __prci_readl(pd, PRCI_CLKMUXSTATUSREG_OFFSET); + v &= PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK; + div = v ? 1 : 2; + + return div_u64(parent_rate, div); +} + +/* HFPCLK clock integration */ + +unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct __prci_clock *pc, + unsigned long parent_rate) +{ + struct __prci_data *pd = pc->pd; + u32 div = __prci_readl(pd, PRCI_HFPCLKPLLDIV_OFFSET); + + return div_u64(parent_rate, div + 2); +} + +/** + * sifive_prci_coreclksel_use_final_corepll() - switch the CORECLK mux to output + * FINAL_COREPLL + * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg + * + * Switch the CORECLK mux to the final COREPLL output clock; return once + * complete. + * + * Context: Any context. Caller must prevent concurrent changes to the + * PRCI_CORECLKSEL_OFFSET register. + */ +void sifive_prci_coreclksel_use_final_corepll(struct __prci_data *pd) +{ + u32 r; + + r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); + r &= ~PRCI_CORECLKSEL_CORECLKSEL_MASK; + __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd); + + r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */ +} + +/** + * sifive_prci_corepllsel_use_dvfscorepll() - switch the COREPLL mux to + * output DVFS_COREPLL + * @pd: struct __prci_data * for the PRCI containing the COREPLL mux reg + * + * Switch the COREPLL mux to the DVFSCOREPLL output clock; return once complete. + * + * Context: Any context. Caller must prevent concurrent changes to the + * PRCI_COREPLLSEL_OFFSET register. + */ +void sifive_prci_corepllsel_use_dvfscorepll(struct __prci_data *pd) +{ + u32 r; + + r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET); + r |= PRCI_COREPLLSEL_COREPLLSEL_MASK; + __prci_writel(r, PRCI_COREPLLSEL_OFFSET, pd); + + r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET); /* barrier */ +} + +/** + * sifive_prci_corepllsel_use_corepll() - switch the COREPLL mux to + * output COREPLL + * @pd: struct __prci_data * for the PRCI containing the COREPLL mux reg + * + * Switch the COREPLL mux to the COREPLL output clock; return once complete. + * + * Context: Any context. Caller must prevent concurrent changes to the + * PRCI_COREPLLSEL_OFFSET register. + */ +void sifive_prci_corepllsel_use_corepll(struct __prci_data *pd) +{ + u32 r; + + r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET); + r &= ~PRCI_COREPLLSEL_COREPLLSEL_MASK; + __prci_writel(r, PRCI_COREPLLSEL_OFFSET, pd); + + r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET); /* barrier */ +} + +/** + * sifive_prci_hfpclkpllsel_use_hfclk() - switch the HFPCLKPLL mux to + * output HFCLK + * @pd: struct __prci_data * for the PRCI containing the HFPCLKPLL mux reg + * + * Switch the HFPCLKPLL mux to the HFCLK input source; return once complete. + * + * Context: Any context. Caller must prevent concurrent changes to the + * PRCI_HFPCLKPLLSEL_OFFSET register. + */ +void sifive_prci_hfpclkpllsel_use_hfclk(struct __prci_data *pd) +{ + u32 r; + + r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); + r |= PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_MASK; + __prci_writel(r, PRCI_HFPCLKPLLSEL_OFFSET, pd); + + r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); /* barrier */ +} + +/** + * sifive_prci_hfpclkpllsel_use_hfpclkpll() - switch the HFPCLKPLL mux to + * output HFPCLKPLL + * @pd: struct __prci_data * for the PRCI containing the HFPCLKPLL mux reg + * + * Switch the HFPCLKPLL mux to the HFPCLKPLL output clock; return once complete. + * + * Context: Any context. Caller must prevent concurrent changes to the + * PRCI_HFPCLKPLLSEL_OFFSET register. + */ +void sifive_prci_hfpclkpllsel_use_hfpclkpll(struct __prci_data *pd) +{ + u32 r; + + r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); + r &= ~PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_MASK; + __prci_writel(r, PRCI_HFPCLKPLLSEL_OFFSET, pd); + + r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); /* barrier */ +} + +static int __prci_consumer_reset(const char *rst_name, bool trigger) +{ + struct udevice *dev; + struct reset_ctl rst_sig; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_RESET, + DM_DRIVER_GET(sifive_reset), + &dev); + if (ret) { + dev_err(dev, "Reset driver not found: %d\n", ret); + return ret; + } + + ret = reset_get_by_name(dev, rst_name, &rst_sig); + if (ret) { + dev_err(dev, "failed to get %s reset\n", rst_name); + return ret; + } + + if (reset_valid(&rst_sig)) { + if (trigger) + ret = reset_deassert(&rst_sig); + else + ret = reset_assert(&rst_sig); + if (ret) { + dev_err(dev, "failed to trigger reset id = %ld\n", + rst_sig.id); + return ret; + } + } + + return ret; +} + +/** + * sifive_prci_ddr_release_reset() - Release DDR reset + * @pd: struct __prci_data * for the PRCI containing the DDRCLK mux reg + * + */ +void sifive_prci_ddr_release_reset(struct __prci_data *pd) +{ + /* Release DDR ctrl reset */ + __prci_consumer_reset("ddr_ctrl", true); + + /* HACK to get the '1 full controller clock cycle'. */ + asm volatile ("fence"); + + /* Release DDR AXI reset */ + __prci_consumer_reset("ddr_axi", true); + + /* Release DDR AHB reset */ + __prci_consumer_reset("ddr_ahb", true); + + /* Release DDR PHY reset */ + __prci_consumer_reset("ddr_phy", true); + + /* HACK to get the '1 full controller clock cycle'. */ + asm volatile ("fence"); + + /* + * These take like 16 cycles to actually propagate. We can't go sending + * stuff before they come out of reset. So wait. + */ + for (int i = 0; i < 256; i++) + asm volatile ("nop"); +} + +/** + * sifive_prci_ethernet_release_reset() - Release ethernet reset + * @pd: struct __prci_data * for the PRCI containing the Ethernet CLK mux reg + * + */ +void sifive_prci_ethernet_release_reset(struct __prci_data *pd) +{ + /* Release GEMGXL reset */ + __prci_consumer_reset("gemgxl_reset", true); + + /* Procmon => core clock */ + __prci_writel(PRCI_PROCMONCFG_CORE_CLOCK_MASK, PRCI_PROCMONCFG_OFFSET, + pd); + + /* Release Chiplink reset */ + __prci_consumer_reset("cltx_reset", true); +} + +/** + * sifive_prci_cltx_release_reset() - Release cltx reset + * @pd: struct __prci_data * for the PRCI containing the Ethernet CLK mux reg + * + */ +void sifive_prci_cltx_release_reset(struct __prci_data *pd) +{ + /* Release CLTX reset */ + __prci_consumer_reset("cltx_reset", true); +} + +/* Core clock mux control */ + +/** + * sifive_prci_coreclksel_use_hfclk() - switch the CORECLK mux to output HFCLK + * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg + * + * Switch the CORECLK mux to the HFCLK input source; return once complete. + * + * Context: Any context. Caller must prevent concurrent changes to the + * PRCI_CORECLKSEL_OFFSET register. + */ +void sifive_prci_coreclksel_use_hfclk(struct __prci_data *pd) +{ + u32 r; + + r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); + r |= PRCI_CORECLKSEL_CORECLKSEL_MASK; + __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd); + + r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */ +} + +/** + * sifive_prci_coreclksel_use_corepll() - switch the CORECLK mux to output COREPLL + * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg + * + * Switch the CORECLK mux to the PLL output clock; return once complete. + * + * Context: Any context. Caller must prevent concurrent changes to the + * PRCI_CORECLKSEL_OFFSET register. + */ +void sifive_prci_coreclksel_use_corepll(struct __prci_data *pd) +{ + u32 r; + + r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); + r &= ~PRCI_CORECLKSEL_CORECLKSEL_MASK; + __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd); + + r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */ +} + +static ulong sifive_prci_parent_rate(struct __prci_clock *pc, struct prci_clk_desc *data) +{ + ulong parent_rate; + ulong i; + struct __prci_clock *p; + + if (strcmp(pc->parent_name, "corepll") == 0 || + strcmp(pc->parent_name, "hfpclkpll") == 0) { + for (i = 0; i < data->num_clks; i++) { + if (strcmp(pc->parent_name, data->clks[i].name) == 0) + break; + } + + if (i >= data->num_clks) + return -ENXIO; + + p = &data->clks[i]; + if (!p->pd || !p->ops->recalc_rate) + return -ENXIO; + + return p->ops->recalc_rate(p, sifive_prci_parent_rate(p, data)); + } + + if (strcmp(pc->parent_name, "rtcclk") == 0) + parent_rate = clk_get_rate(&pc->pd->parent_rtcclk); + else + parent_rate = clk_get_rate(&pc->pd->parent_hfclk); + + return parent_rate; +} + +static ulong sifive_prci_get_rate(struct clk *clk) +{ + struct __prci_clock *pc; + struct prci_clk_desc *data = + (struct prci_clk_desc *)dev_get_driver_data(clk->dev); + + if (data->num_clks <= clk->id) + return -ENXIO; + + pc = &data->clks[clk->id]; + if (!pc->pd || !pc->ops->recalc_rate) + return -ENXIO; + + return pc->ops->recalc_rate(pc, sifive_prci_parent_rate(pc, data)); +} + +static ulong sifive_prci_set_rate(struct clk *clk, ulong rate) +{ + int err; + struct __prci_clock *pc; + struct prci_clk_desc *data = + (struct prci_clk_desc *)dev_get_driver_data(clk->dev); + + if (data->num_clks <= clk->id) + return -ENXIO; + + pc = &data->clks[clk->id]; + if (!pc->pd || !pc->ops->set_rate) + return -ENXIO; + + err = pc->ops->set_rate(pc, rate, sifive_prci_parent_rate(pc, data)); + if (err) + return err; + + return rate; +} + +static int sifive_prci_enable(struct clk *clk) +{ + struct __prci_clock *pc; + int ret = 0; + struct prci_clk_desc *data = + (struct prci_clk_desc *)dev_get_driver_data(clk->dev); + + if (data->num_clks <= clk->id) + return -ENXIO; + + pc = &data->clks[clk->id]; + if (!pc->pd) + return -ENXIO; + + if (pc->ops->enable_clk) + ret = pc->ops->enable_clk(pc, 1); + + return ret; +} + +static int sifive_prci_disable(struct clk *clk) +{ + struct __prci_clock *pc; + int ret = 0; + struct prci_clk_desc *data = + (struct prci_clk_desc *)dev_get_driver_data(clk->dev); + + if (data->num_clks <= clk->id) + return -ENXIO; + + pc = &data->clks[clk->id]; + if (!pc->pd) + return -ENXIO; + + if (pc->ops->enable_clk) + ret = pc->ops->enable_clk(pc, 0); + + return ret; +} + +static int sifive_prci_probe(struct udevice *dev) +{ + int i, err; + struct __prci_clock *pc; + struct __prci_data *pd = dev_get_priv(dev); + + struct prci_clk_desc *data = + (struct prci_clk_desc *)dev_get_driver_data(dev); + + pd->va = (void *)dev_read_addr(dev); + if (IS_ERR(pd->va)) + return PTR_ERR(pd->va); + + err = clk_get_by_index(dev, 0, &pd->parent_hfclk); + if (err) + return err; + + err = clk_get_by_index(dev, 1, &pd->parent_rtcclk); + if (err) + return err; + + for (i = 0; i < data->num_clks; ++i) { + pc = &data->clks[i]; + pc->pd = pd; + if (pc->pwd) + __prci_wrpll_read_cfg0(pd, pc->pwd); + } + + if (IS_ENABLED(CONFIG_SPL_BUILD)) { + if (device_is_compatible(dev, "sifive,fu740-c000-prci")) { + u32 prci_pll_reg; + unsigned long parent_rate; + + prci_pll_reg = readl(pd->va + PRCI_PRCIPLL_OFFSET); + + if (prci_pll_reg & PRCI_PRCIPLL_HFPCLKPLL) { + /* + * Only initialize the HFPCLK PLL. In this + * case the design uses hfpclk to drive + * Chiplink + */ + pc = &data->clks[PRCI_CLK_HFPCLKPLL]; + parent_rate = sifive_prci_parent_rate(pc, data); + sifive_prci_wrpll_set_rate(pc, 260000000, + parent_rate); + pc->ops->enable_clk(pc, 1); + } else if (prci_pll_reg & PRCI_PRCIPLL_CLTXPLL) { + /* CLTX pll init */ + pc = &data->clks[PRCI_CLK_CLTXPLL]; + parent_rate = sifive_prci_parent_rate(pc, data); + sifive_prci_wrpll_set_rate(pc, 260000000, + parent_rate); + pc->ops->enable_clk(pc, 1); + } + } + } + + return 0; +} + +static struct clk_ops sifive_prci_ops = { + .set_rate = sifive_prci_set_rate, + .get_rate = sifive_prci_get_rate, + .enable = sifive_prci_enable, + .disable = sifive_prci_disable, +}; + +static int sifive_clk_bind(struct udevice *dev) +{ + return sifive_reset_bind(dev, PRCI_DEVICERESETCNT); +} + +static const struct udevice_id sifive_prci_ids[] = { + { .compatible = "sifive,fu540-c000-prci", .data = (ulong)&prci_clk_fu540 }, + { .compatible = "sifive,fu740-c000-prci", .data = (ulong)&prci_clk_fu740 }, + { } +}; + +U_BOOT_DRIVER(sifive_prci) = { + .name = "sifive-prci", + .id = UCLASS_CLK, + .of_match = sifive_prci_ids, + .probe = sifive_prci_probe, + .ops = &sifive_prci_ops, + .priv_auto = sizeof(struct __prci_data), + .bind = sifive_clk_bind, +}; diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h new file mode 100644 index 0000000000..5ce33d6184 --- /dev/null +++ b/drivers/clk/sifive/sifive-prci.h @@ -0,0 +1,323 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020-2021 SiFive, Inc. + * Wesley Terpstra + * Paul Walmsley + * Zong Li + * Pragnesh Patel + */ + +#ifndef __SIFIVE_CLK_SIFIVE_PRCI_H +#define __SIFIVE_CLK_SIFIVE_PRCI_H + +#include <clk.h> +#include <linux/clk/analogbits-wrpll-cln28hpc.h> + +/* + * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects: + * hfclk and rtcclk + */ +#define EXPECTED_CLK_PARENT_COUNT 2 + +/* + * Register offsets and bitmasks + */ + +/* COREPLLCFG0 */ +#define PRCI_COREPLLCFG0_OFFSET 0x4 +#define PRCI_COREPLLCFG0_DIVR_SHIFT 0 +#define PRCI_COREPLLCFG0_DIVR_MASK (0x3f << PRCI_COREPLLCFG0_DIVR_SHIFT) +#define PRCI_COREPLLCFG0_DIVF_SHIFT 6 +#define PRCI_COREPLLCFG0_DIVF_MASK (0x1ff << PRCI_COREPLLCFG0_DIVF_SHIFT) +#define PRCI_COREPLLCFG0_DIVQ_SHIFT 15 +#define PRCI_COREPLLCFG0_DIVQ_MASK (0x7 << PRCI_COREPLLCFG0_DIVQ_SHIFT) +#define PRCI_COREPLLCFG0_RANGE_SHIFT 18 +#define PRCI_COREPLLCFG0_RANGE_MASK (0x7 << PRCI_COREPLLCFG0_RANGE_SHIFT) +#define PRCI_COREPLLCFG0_BYPASS_SHIFT 24 +#define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT) +#define PRCI_COREPLLCFG0_FSE_SHIFT 25 +#define PRCI_COREPLLCFG0_FSE_MASK (0x1 << PRCI_COREPLLCFG0_FSE_SHIFT) +#define PRCI_COREPLLCFG0_LOCK_SHIFT 31 +#define PRCI_COREPLLCFG0_LOCK_MASK (0x1 << PRCI_COREPLLCFG0_LOCK_SHIFT) + +/* COREPLLCFG1 */ +#define PRCI_COREPLLCFG1_OFFSET 0x8 +#define PRCI_COREPLLCFG1_CKE_SHIFT 31 +#define PRCI_COREPLLCFG1_CKE_MASK (0x1 << PRCI_COREPLLCFG1_CKE_SHIFT) + +/* DDRPLLCFG0 */ +#define PRCI_DDRPLLCFG0_OFFSET 0xc +#define PRCI_DDRPLLCFG0_DIVR_SHIFT 0 +#define PRCI_DDRPLLCFG0_DIVR_MASK (0x3f << PRCI_DDRPLLCFG0_DIVR_SHIFT) +#define PRCI_DDRPLLCFG0_DIVF_SHIFT 6 +#define PRCI_DDRPLLCFG0_DIVF_MASK (0x1ff << PRCI_DDRPLLCFG0_DIVF_SHIFT) +#define PRCI_DDRPLLCFG0_DIVQ_SHIFT 15 +#define PRCI_DDRPLLCFG0_DIVQ_MASK (0x7 << PRCI_DDRPLLCFG0_DIVQ_SHIFT) +#define PRCI_DDRPLLCFG0_RANGE_SHIFT 18 +#define PRCI_DDRPLLCFG0_RANGE_MASK (0x7 << PRCI_DDRPLLCFG0_RANGE_SHIFT) +#define PRCI_DDRPLLCFG0_BYPASS_SHIFT 24 +#define PRCI_DDRPLLCFG0_BYPASS_MASK (0x1 << PRCI_DDRPLLCFG0_BYPASS_SHIFT) +#define PRCI_DDRPLLCFG0_FSE_SHIFT 25 +#define PRCI_DDRPLLCFG0_FSE_MASK (0x1 << PRCI_DDRPLLCFG0_FSE_SHIFT) +#define PRCI_DDRPLLCFG0_LOCK_SHIFT 31 +#define PRCI_DDRPLLCFG0_LOCK_MASK (0x1 << PRCI_DDRPLLCFG0_LOCK_SHIFT) + +/* DDRPLLCFG1 */ +#define PRCI_DDRPLLCFG1_OFFSET 0x10 +#define PRCI_DDRPLLCFG1_CKE_SHIFT 31 +#define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT) + +/* PCIEAUXCFG1 */ +#define PRCI_PCIEAUXCFG1_OFFSET 0x14 +#define PRCI_PCIEAUXCFG1_SHIFT 0 +#define PRCI_PCIEAUXCFG1_MASK (0x1 << PRCI_PCIEAUXCFG1_SHIFT) + +/* GEMGXLPLLCFG0 */ +#define PRCI_GEMGXLPLLCFG0_OFFSET 0x1c +#define PRCI_GEMGXLPLLCFG0_DIVR_SHIFT 0 +#define PRCI_GEMGXLPLLCFG0_DIVR_MASK \ + (0x3f << PRCI_GEMGXLPLLCFG0_DIVR_SHIFT) +#define PRCI_GEMGXLPLLCFG0_DIVF_SHIFT 6 +#define PRCI_GEMGXLPLLCFG0_DIVF_MASK \ + (0x1ff << PRCI_GEMGXLPLLCFG0_DIVF_SHIFT) +#define PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT 15 +#define PRCI_GEMGXLPLLCFG0_DIVQ_MASK (0x7 << PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT) +#define PRCI_GEMGXLPLLCFG0_RANGE_SHIFT 18 +#define PRCI_GEMGXLPLLCFG0_RANGE_MASK \ + (0x7 << PRCI_GEMGXLPLLCFG0_RANGE_SHIFT) +#define PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT 24 +#define PRCI_GEMGXLPLLCFG0_BYPASS_MASK \ + (0x1 << PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT) +#define PRCI_GEMGXLPLLCFG0_FSE_SHIFT 25 +#define PRCI_GEMGXLPLLCFG0_FSE_MASK \ + (0x1 << PRCI_GEMGXLPLLCFG0_FSE_SHIFT) +#define PRCI_GEMGXLPLLCFG0_LOCK_SHIFT 31 +#define PRCI_GEMGXLPLLCFG0_LOCK_MASK (0x1 << PRCI_GEMGXLPLLCFG0_LOCK_SHIFT) + +/* GEMGXLPLLCFG1 */ +#define PRCI_GEMGXLPLLCFG1_OFFSET 0x20 +#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 31 +#define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT) + +/* CORECLKSEL */ +#define PRCI_CORECLKSEL_OFFSET 0x24 +#define PRCI_CORECLKSEL_CORECLKSEL_SHIFT 0 +#define PRCI_CORECLKSEL_CORECLKSEL_MASK \ + (0x1 << PRCI_CORECLKSEL_CORECLKSEL_SHIFT) + +/* DEVICESRESETREG */ +#define PRCI_DEVICESRESETREG_OFFSET 0x28 +#define PRCI_DEVICERESETCNT 6 + +/* CLKMUXSTATUSREG */ +#define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c +#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1 +#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \ + (0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT) + +/* CLTXPLLCFG0 */ +#define PRCI_CLTXPLLCFG0_OFFSET 0x30 +#define PRCI_CLTXPLLCFG0_DIVR_SHIFT 0 +#define PRCI_CLTXPLLCFG0_DIVR_MASK (0x3f << PRCI_CLTXPLLCFG0_DIVR_SHIFT) +#define PRCI_CLTXPLLCFG0_DIVF_SHIFT 6 +#define PRCI_CLTXPLLCFG0_DIVF_MASK (0x1ff << PRCI_CLTXPLLCFG0_DIVF_SHIFT) +#define PRCI_CLTXPLLCFG0_DIVQ_SHIFT 15 +#define PRCI_CLTXPLLCFG0_DIVQ_MASK (0x7 << PRCI_CLTXPLLCFG0_DIVQ_SHIFT) +#define PRCI_CLTXPLLCFG0_RANGE_SHIFT 18 +#define PRCI_CLTXPLLCFG0_RANGE_MASK (0x7 << PRCI_CLTXPLLCFG0_RANGE_SHIFT) +#define PRCI_CLTXPLLCFG0_BYPASS_SHIFT 24 +#define PRCI_CLTXPLLCFG0_BYPASS_MASK (0x1 << PRCI_CLTXPLLCFG0_BYPASS_SHIFT) +#define PRCI_CLTXPLLCFG0_FSE_SHIFT 25 +#define PRCI_CLTXPLLCFG0_FSE_MASK (0x1 << PRCI_CLTXPLLCFG0_FSE_SHIFT) +#define PRCI_CLTXPLLCFG0_LOCK_SHIFT 31 +#define PRCI_CLTXPLLCFG0_LOCK_MASK (0x1 << PRCI_CLTXPLLCFG0_LOCK_SHIFT) + +/* CLTXPLLCFG1 */ +#define PRCI_CLTXPLLCFG1_OFFSET 0x34 +#define PRCI_CLTXPLLCFG1_CKE_SHIFT 24 +#define PRCI_CLTXPLLCFG1_CKE_MASK (0x1 << PRCI_CLTXPLLCFG1_CKE_SHIFT) + +/* DVFSCOREPLLCFG0 */ +#define PRCI_DVFSCOREPLLCFG0_OFFSET 0x38 + +/* DVFSCOREPLLCFG1 */ +#define PRCI_DVFSCOREPLLCFG1_OFFSET 0x3c +#define PRCI_DVFSCOREPLLCFG1_CKE_SHIFT 24 +#define PRCI_DVFSCOREPLLCFG1_CKE_MASK (0x1 << PRCI_DVFSCOREPLLCFG1_CKE_SHIFT) + +/* COREPLLSEL */ +#define PRCI_COREPLLSEL_OFFSET 0x40 +#define PRCI_COREPLLSEL_COREPLLSEL_SHIFT 0 +#define PRCI_COREPLLSEL_COREPLLSEL_MASK \ + (0x1 << PRCI_COREPLLSEL_COREPLLSEL_SHIFT) + +/* HFPCLKPLLCFG0 */ +#define PRCI_HFPCLKPLLCFG0_OFFSET 0x50 +#define PRCI_HFPCLKPLL_CFG0_DIVR_SHIFT 0 +#define PRCI_HFPCLKPLL_CFG0_DIVR_MASK \ + (0x3f << PRCI_HFPCLKPLLCFG0_DIVR_SHIFT) +#define PRCI_HFPCLKPLL_CFG0_DIVF_SHIFT 6 +#define PRCI_HFPCLKPLL_CFG0_DIVF_MASK \ + (0x1ff << PRCI_HFPCLKPLLCFG0_DIVF_SHIFT) +#define PRCI_HFPCLKPLL_CFG0_DIVQ_SHIFT 15 +#define PRCI_HFPCLKPLL_CFG0_DIVQ_MASK \ + (0x7 << PRCI_HFPCLKPLLCFG0_DIVQ_SHIFT) +#define PRCI_HFPCLKPLL_CFG0_RANGE_SHIFT 18 +#define PRCI_HFPCLKPLL_CFG0_RANGE_MASK \ + (0x7 << PRCI_HFPCLKPLLCFG0_RANGE_SHIFT) +#define PRCI_HFPCLKPLL_CFG0_BYPASS_SHIFT 24 +#define PRCI_HFPCLKPLL_CFG0_BYPASS_MASK \ + (0x1 << PRCI_HFPCLKPLLCFG0_BYPASS_SHIFT) +#define PRCI_HFPCLKPLL_CFG0_FSE_SHIFT 25 +#define PRCI_HFPCLKPLL_CFG0_FSE_MASK \ + (0x1 << PRCI_HFPCLKPLLCFG0_FSE_SHIFT) +#define PRCI_HFPCLKPLL_CFG0_LOCK_SHIFT 31 +#define PRCI_HFPCLKPLL_CFG0_LOCK_MASK \ + (0x1 << PRCI_HFPCLKPLLCFG0_LOCK_SHIFT) + +/* HFPCLKPLLCFG1 */ +#define PRCI_HFPCLKPLLCFG1_OFFSET 0x54 +#define PRCI_HFPCLKPLLCFG1_CKE_SHIFT 24 +#define PRCI_HFPCLKPLLCFG1_CKE_MASK \ + (0x1 << PRCI_HFPCLKPLLCFG1_CKE_SHIFT) + +/* HFPCLKPLLSEL */ +#define PRCI_HFPCLKPLLSEL_OFFSET 0x58 +#define PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_SHIFT 0 +#define PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_MASK \ + (0x1 << PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_SHIFT) + +/* HFPCLKPLLDIV */ +#define PRCI_HFPCLKPLLDIV_OFFSET 0x5c + +/* PRCIPLL */ +#define PRCI_PRCIPLL_OFFSET 0xe0 + +#define PRCI_PRCIPLL_CLTXPLL (0x1 << 0) +#define PRCI_PRCIPLL_GEMGXLPLL (0x1 << 1) +#define PRCI_PRCIPLL_DDRPLL (0x1 << 2) +#define PRCI_PRCIPLL_HFPCLKPLL (0x1 << 3) +#define PRCI_PRCIPLL_DVFSCOREPLL (0x1 << 4) +#define PRCI_PRCIPLL_COREPLL (0x1 << 5) + +/* PROCMONCFG */ +#define PRCI_PROCMONCFG_OFFSET 0xF0 +#define PRCI_PROCMONCFG_CORE_CLOCK_SHIFT 24 +#define PRCI_PROCMONCFG_CORE_CLOCK_MASK \ + (0x1 << PRCI_PROCMONCFG_CORE_CLOCK_SHIFT) + +/* + * Private structures + */ + +/** + * struct __prci_data - per-device-instance data + * @va: base virtual address of the PRCI IP block + * @parent: parent clk instance + * + * PRCI per-device instance data + */ +struct __prci_data { + void *va; + struct clk parent_hfclk; + struct clk parent_rtcclk; +}; + +/** + * struct __prci_wrpll_data - WRPLL configuration and integration data + * @c: WRPLL current configuration record + * @enable_bypass: fn ptr to code to bypass the WRPLL (if applicable; else NULL) + * @disable_bypass: fn ptr to code to not bypass the WRPLL (or NULL) + * @cfg0_offs: WRPLL CFG0 register offset (in bytes) from the PRCI base address + * @cfg1_offs: WRPLL CFG1 register offset (in bytes) from the PRCI base address + * @release_reset: fn ptr to code to release clock reset + * + * @enable_bypass and @disable_bypass are used for WRPLL instances + * that contain a separate external glitchless clock mux downstream + * from the PLL. The WRPLL internal bypass mux is not glitchless. + */ +struct __prci_wrpll_data { + struct wrpll_cfg c; + void (*enable_bypass)(struct __prci_data *pd); + void (*disable_bypass)(struct __prci_data *pd); + u8 cfg0_offs; + u8 cfg1_offs; + void (*release_reset)(struct __prci_data *pd); +}; + +/** + * struct __prci_clock - describes a clock device managed by PRCI + * @name: user-readable clock name string - should match the manual + * @parent_name: parent name for this clock + * @ops: struct __prci_clock_ops for control + * @pwd: WRPLL-specific data, associated with this clock (if not NULL) + * @pd: PRCI-specific data associated with this clock (if not NULL) + * + * PRCI clock data. Used by the PRCI driver to register PRCI-provided + * clocks to the Linux clock infrastructure. + */ +struct __prci_clock { + const char *name; + const char *parent_name; + const struct __prci_clock_ops *ops; + struct __prci_wrpll_data *pwd; + struct __prci_data *pd; +}; + +/* struct __prci_clock_ops - clock operations */ +struct __prci_clock_ops { + int (*set_rate)(struct __prci_clock *pc, + unsigned long rate, + unsigned long parent_rate); + unsigned long (*round_rate)(struct __prci_clock *pc, + unsigned long rate, + unsigned long *parent_rate); + unsigned long (*recalc_rate)(struct __prci_clock *pc, + unsigned long parent_rate); + int (*enable_clk)(struct __prci_clock *pc, bool enable); +}; + +/* + * struct prci_clk_desc - describes the information of clocks of each SoCs + * @clks: point to a array of __prci_clock + * @num_clks: the number of element of clks + */ +struct prci_clk_desc { + struct __prci_clock *clks; + size_t num_clks; +}; + +void sifive_prci_ethernet_release_reset(struct __prci_data *pd); +void sifive_prci_ddr_release_reset(struct __prci_data *pd); +void sifive_prci_cltx_release_reset(struct __prci_data *pd); + +/* Core clock mux control */ +void sifive_prci_coreclksel_use_hfclk(struct __prci_data *pd); +void sifive_prci_coreclksel_use_corepll(struct __prci_data *pd); +void sifive_prci_coreclksel_use_final_corepll(struct __prci_data *pd); +void sifive_prci_corepllsel_use_dvfscorepll(struct __prci_data *pd); +void sifive_prci_corepllsel_use_corepll(struct __prci_data *pd); +void sifive_prci_hfpclkpllsel_use_hfclk(struct __prci_data *pd); +void sifive_prci_hfpclkpllsel_use_hfpclkpll(struct __prci_data *pd); + +unsigned long sifive_prci_wrpll_round_rate(struct __prci_clock *pc, + unsigned long rate, + unsigned long *parent_rate); + +/* Linux clock framework integration */ +int sifive_prci_wrpll_set_rate(struct __prci_clock *pc, + unsigned long rate, + unsigned long parent_rate); + +unsigned long sifive_prci_wrpll_recalc_rate(struct __prci_clock *pc, + unsigned long parent_rate); + +unsigned long sifive_prci_tlclksel_recalc_rate(struct __prci_clock *pc, + unsigned long parent_rate); + +unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct __prci_clock *pc, + unsigned long parent_rate); + +int sifive_prci_clock_enable(struct __prci_clock *pc, bool enable); + +#endif /* __SIFIVE_CLK_SIFIVE_PRCI_H */ diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index d5b6018b3d..b2b7b253f8 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -97,6 +97,16 @@ config PCIE_DW_MVEBU Armada-8K SoCs. The PCIe controller on Armada-8K is based on DesignWare hardware. +config PCIE_DW_SIFIVE + bool "Enable SiFive FU740 PCIe" + depends on CLK_SIFIVE_PRCI + depends on RESET_SIFIVE + depends on SIFIVE_GPIO + select PCIE_DW_COMMON + help + Say Y here if you want to enable PCIe controller support on + FU740. + config PCIE_FSL bool "FSL PowerPC PCIe support" depends on DM_PCI diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 1f741786a0..c742bb2c94 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -54,3 +54,4 @@ obj-$(CONFIG_PCIE_DW_MESON) += pcie_dw_meson.o obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o +obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o diff --git a/drivers/pci/pcie_dw_common.c b/drivers/pci/pcie_dw_common.c index 785fd3aad0..e66fb1490a 100644 --- a/drivers/pci/pcie_dw_common.c +++ b/drivers/pci/pcie_dw_common.c @@ -213,7 +213,7 @@ int pcie_dw_read_config(const struct udevice *bus, pci_dev_t bdf, va_address = set_cfg_address(pcie, bdf, offset); - value = readl(va_address); + value = readl((void __iomem *)va_address); debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); *valuep = pci_conv_32_to_size(value, offset, size); @@ -257,9 +257,9 @@ int pcie_dw_write_config(struct udevice *bus, pci_dev_t bdf, va_address = set_cfg_address(pcie, bdf, offset); - old = readl(va_address); + old = readl((void __iomem *)va_address); value = pci_conv_size_to_32(old, value, offset, size); - writel(value, va_address); + writel(value, (void __iomem *)va_address); return pcie_dw_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1, PCIE_ATU_TYPE_IO, pcie->io.phys_start, @@ -333,33 +333,37 @@ void pcie_dw_setup_host(struct pcie_dw *pci) } } - dev_dbg(pci->dev, "Config space: [0x%p - 0x%p, size 0x%llx]\n", - pci->cfg_base, pci->cfg_base + pci->cfg_size, - pci->cfg_size); + dev_dbg(pci->dev, "Config space: [0x%llx - 0x%llx, size 0x%llx]\n", + (u64)pci->cfg_base, (u64)pci->cfg_base + pci->cfg_size, + (u64)pci->cfg_size); - dev_dbg(pci->dev, "IO space: [0x%llx - 0x%llx, size 0x%lx]\n", - pci->io.phys_start, pci->io.phys_start + pci->io.size, - pci->io.size); + dev_dbg(pci->dev, "IO space: [0x%llx - 0x%llx, size 0x%llx]\n", + (u64)pci->io.phys_start, (u64)pci->io.phys_start + pci->io.size, + (u64)pci->io.size); - dev_dbg(pci->dev, "IO bus: [0x%lx - 0x%lx, size 0x%lx]\n", - pci->io.bus_start, pci->io.bus_start + pci->io.size, - pci->io.size); + dev_dbg(pci->dev, "IO bus: [0x%llx - 0x%llx, size 0x%llx]\n", + (u64)pci->io.bus_start, (u64)pci->io.bus_start + pci->io.size, + (u64)pci->io.size); - dev_dbg(pci->dev, "MEM space: [0x%llx - 0x%llx, size 0x%lx]\n", - pci->mem.phys_start, pci->mem.phys_start + pci->mem.size, - pci->mem.size); + dev_dbg(pci->dev, "MEM space: [0x%llx - 0x%llx, size 0x%llx]\n", + (u64)pci->mem.phys_start, + (u64)pci->mem.phys_start + pci->mem.size, + (u64)pci->mem.size); - dev_dbg(pci->dev, "MEM bus: [0x%lx - 0x%lx, size 0x%lx]\n", - pci->mem.bus_start, pci->mem.bus_start + pci->mem.size, - pci->mem.size); + dev_dbg(pci->dev, "MEM bus: [0x%llx - 0x%llx, size 0x%llx]\n", + (u64)pci->mem.bus_start, + (u64)pci->mem.bus_start + pci->mem.size, + (u64)pci->mem.size); if (pci->prefetch.size) { - dev_dbg(pci->dev, "PREFETCH space: [0x%llx - 0x%llx, size 0x%lx]\n", - pci->prefetch.phys_start, pci->prefetch.phys_start + pci->prefetch.size, - pci->prefetch.size); - - dev_dbg(pci->dev, "PREFETCH bus: [0x%lx - 0x%lx, size 0x%lx]\n", - pci->prefetch.bus_start, pci->prefetch.bus_start + pci->prefetch.size, - pci->prefetch.size); + dev_dbg(pci->dev, "PREFETCH space: [0x%llx - 0x%llx, size 0x%llx]\n", + (u64)pci->prefetch.phys_start, + (u64)pci->prefetch.phys_start + pci->prefetch.size, + (u64)pci->prefetch.size); + + dev_dbg(pci->dev, "PREFETCH bus: [0x%llx - 0x%llx, size 0x%llx]\n", + (u64)pci->prefetch.bus_start, + (u64)pci->prefetch.bus_start + pci->prefetch.size, + (u64)pci->prefetch.size); } } diff --git a/drivers/pci/pcie_dw_sifive.c b/drivers/pci/pcie_dw_sifive.c new file mode 100644 index 0000000000..fac3f18237 --- /dev/null +++ b/drivers/pci/pcie_dw_sifive.c @@ -0,0 +1,507 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * SiFive FU740 DesignWare PCIe Controller + * + * Copyright (C) 2020-2021 SiFive, Inc. + * + * Based in early part on the i.MX6 PCIe host controller shim which is: + * + * Copyright (C) 2013 Kosagi + * http://www.kosagi.com + * + * Based on driver from author: Alan Mikhak <amikhak@wirelessfabric.com> + */ +#include <asm/io.h> +#include <asm-generic/gpio.h> +#include <clk.h> +#include <common.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <generic-phy.h> +#include <linux/bitops.h> +#include <linux/log2.h> +#include <pci.h> +#include <pci_ep.h> +#include <pci_ids.h> +#include <regmap.h> +#include <reset.h> +#include <syscon.h> + +#include "pcie_dw_common.h" + +struct pcie_sifive { + /* Must be first member of the struct */ + struct pcie_dw dw; + + /* private control regs */ + void __iomem *priv_base; + + /* reset, power, clock resources */ + int sys_int_pin; + struct gpio_desc pwren_gpio; + struct gpio_desc reset_gpio; + struct clk aux_ck; + struct reset_ctl reset; +}; + +enum pcie_sifive_devtype { + SV_PCIE_UNKNOWN_TYPE = 0, + SV_PCIE_ENDPOINT_TYPE = 1, + SV_PCIE_HOST_TYPE = 3 +}; + +#define ASSERTION_DELAY 100 +#define PCIE_PERST_ASSERT 0x0 +#define PCIE_PERST_DEASSERT 0x1 +#define PCIE_PHY_RESET 0x1 +#define PCIE_PHY_RESET_DEASSERT 0x0 +#define GPIO_LOW 0x0 +#define GPIO_HIGH 0x1 +#define PCIE_PHY_SEL 0x1 + +#define sv_info(sv, fmt, arg...) printf(fmt, ## arg) +#define sv_warn(sv, fmt, arg...) printf(fmt, ## arg) +#define sv_debug(sv, fmt, arg...) debug(fmt, ## arg) +#define sv_err(sv, fmt, arg...) printf(fmt, ## arg) + +/* Doorbell Interface */ +#define DBI_OFFSET 0x0 +#define DBI_SIZE 0x1000 + +#define PL_OFFSET 0x700 + +#define PHY_DEBUG_R0 (PL_OFFSET + 0x28) + +#define PHY_DEBUG_R1 (PL_OFFSET + 0x2c) +#define PHY_DEBUG_R1_LINK_UP (0x1 << 4) +#define PHY_DEBUG_R1_LINK_IN_TRAINING (0x1 << 29) + +#define PCIE_MISC_CONTROL_1 0x8bc +#define DBI_RO_WR_EN BIT(0) + +/* pcie reset */ +#define PCIEX8MGMT_PERST_N 0x0 + +/* LTSSM */ +#define PCIEX8MGMT_APP_LTSSM_ENABLE 0x10 +#define LTSSM_ENABLE_BIT BIT(0) + +/* phy reset */ +#define PCIEX8MGMT_APP_HOLD_PHY_RST 0x18 + +/* device type */ +#define PCIEX8MGMT_DEVICE_TYPE 0x708 +#define DEVICE_TYPE_EP 0x0 +#define DEVICE_TYPE_RC 0x4 + +/* phy control registers*/ +#define PCIEX8MGMT_PHY0_CR_PARA_ADDR 0x860 +#define PCIEX8MGMT_PHY0_CR_PARA_RD_EN 0x870 +#define PCIEX8MGMT_PHY0_CR_PARA_RD_DATA 0x878 +#define PCIEX8MGMT_PHY0_CR_PARA_SEL 0x880 +#define PCIEX8MGMT_PHY0_CR_PARA_WR_DATA 0x888 +#define PCIEX8MGMT_PHY0_CR_PARA_WR_EN 0x890 +#define PCIEX8MGMT_PHY0_CR_PARA_ACK 0x898 +#define PCIEX8MGMT_PHY1_CR_PARA_ADDR 0x8a0 +#define PCIEX8MGMT_PHY1_CR_PARA_RD_EN 0x8b0 +#define PCIEX8MGMT_PHY1_CR_PARA_RD_DATA 0x8b8 +#define PCIEX8MGMT_PHY1_CR_PARA_SEL 0x8c0 +#define PCIEX8MGMT_PHY1_CR_PARA_WR_DATA 0x8c8 +#define PCIEX8MGMT_PHY1_CR_PARA_WR_EN 0x8d0 +#define PCIEX8MGMT_PHY1_CR_PARA_ACK 0x8d8 + +#define PCIEX8MGMT_LANE_NUM 8 +#define PCIEX8MGMT_LANE 0x1008 +#define PCIEX8MGMT_LANE_OFF 0x100 +#define PCIEX8MGMT_TERM_MODE 0x0e21 + +#define PCIE_CAP_BASE 0x70 +#define PCI_CONFIG(r) (DBI_OFFSET + (r)) +#define PCIE_CAPABILITIES(r) PCI_CONFIG(PCIE_CAP_BASE + (r)) + +/* Link capability */ +#define PF0_PCIE_CAP_LINK_CAP PCIE_CAPABILITIES(0xc) +#define PCIE_LINK_CAP_MAX_SPEED_MASK 0xf +#define PCIE_LINK_CAP_MAX_SPEED_GEN1 BIT(0) +#define PCIE_LINK_CAP_MAX_SPEED_GEN2 BIT(1) +#define PCIE_LINK_CAP_MAX_SPEED_GEN3 BIT(2) +#define PCIE_LINK_CAP_MAX_SPEED_GEN4 BIT(3) + +static enum pcie_sifive_devtype pcie_sifive_get_devtype(struct pcie_sifive *sv) +{ + u32 val; + + val = readl(sv->priv_base + PCIEX8MGMT_DEVICE_TYPE); + switch (val) { + case DEVICE_TYPE_RC: + return SV_PCIE_HOST_TYPE; + case DEVICE_TYPE_EP: + return SV_PCIE_ENDPOINT_TYPE; + default: + return SV_PCIE_UNKNOWN_TYPE; + } +} + +static void pcie_sifive_priv_set_state(struct pcie_sifive *sv, u32 reg, + u32 bits, int state) +{ + u32 val; + + val = readl(sv->priv_base + reg); + val = state ? (val | bits) : (val & !bits); + writel(val, sv->priv_base + reg); +} + +static void pcie_sifive_assert_reset(struct pcie_sifive *sv) +{ + dm_gpio_set_value(&sv->reset_gpio, GPIO_LOW); + writel(PCIE_PERST_ASSERT, sv->priv_base + PCIEX8MGMT_PERST_N); + mdelay(ASSERTION_DELAY); +} + +static void pcie_sifive_power_on(struct pcie_sifive *sv) +{ + dm_gpio_set_value(&sv->pwren_gpio, GPIO_HIGH); + mdelay(ASSERTION_DELAY); +} + +static void pcie_sifive_deassert_reset(struct pcie_sifive *sv) +{ + writel(PCIE_PERST_DEASSERT, sv->priv_base + PCIEX8MGMT_PERST_N); + dm_gpio_set_value(&sv->reset_gpio, GPIO_HIGH); + mdelay(ASSERTION_DELAY); +} + +static int pcie_sifive_setphy(const u8 phy, const u8 write, + const u16 addr, const u16 wrdata, + u16 *rddata, struct pcie_sifive *sv) +{ + unsigned char ack = 0; + + if (!(phy == 0 || phy == 1)) + return -2; + + /* setup phy para */ + writel(addr, sv->priv_base + + (phy ? PCIEX8MGMT_PHY1_CR_PARA_ADDR : + PCIEX8MGMT_PHY0_CR_PARA_ADDR)); + + if (write) + writel(wrdata, sv->priv_base + + (phy ? PCIEX8MGMT_PHY1_CR_PARA_WR_DATA : + PCIEX8MGMT_PHY0_CR_PARA_WR_DATA)); + + /* enable access if write */ + if (write) + writel(1, sv->priv_base + + (phy ? PCIEX8MGMT_PHY1_CR_PARA_WR_EN : + PCIEX8MGMT_PHY0_CR_PARA_WR_EN)); + else + writel(1, sv->priv_base + + (phy ? PCIEX8MGMT_PHY1_CR_PARA_RD_EN : + PCIEX8MGMT_PHY0_CR_PARA_RD_EN)); + + /* wait for wait_idle */ + do { + u32 val; + + val = readl(sv->priv_base + + (phy ? PCIEX8MGMT_PHY1_CR_PARA_ACK : + PCIEX8MGMT_PHY0_CR_PARA_ACK)); + if (val) { + ack = 1; + if (!write) + readl(sv->priv_base + + (phy ? PCIEX8MGMT_PHY1_CR_PARA_RD_DATA : + PCIEX8MGMT_PHY0_CR_PARA_RD_DATA)); + mdelay(1); + } + } while (!ack); + + /* clear */ + if (write) + writel(0, sv->priv_base + + (phy ? PCIEX8MGMT_PHY1_CR_PARA_WR_EN : + PCIEX8MGMT_PHY0_CR_PARA_WR_EN)); + else + writel(0, sv->priv_base + + (phy ? PCIEX8MGMT_PHY1_CR_PARA_RD_EN : + PCIEX8MGMT_PHY0_CR_PARA_RD_EN)); + + while (readl(sv->priv_base + + (phy ? PCIEX8MGMT_PHY1_CR_PARA_ACK : + PCIEX8MGMT_PHY0_CR_PARA_ACK))) { + /* wait for ~wait_idle */ + } + + return 0; +} + +static void pcie_sifive_init_phy(struct pcie_sifive *sv) +{ + int lane; + + /* enable phy cr_para_sel interfaces */ + writel(PCIE_PHY_SEL, sv->priv_base + PCIEX8MGMT_PHY0_CR_PARA_SEL); + writel(PCIE_PHY_SEL, sv->priv_base + PCIEX8MGMT_PHY1_CR_PARA_SEL); + mdelay(1); + + /* set PHY AC termination mode */ + for (lane = 0; lane < PCIEX8MGMT_LANE_NUM; lane++) { + pcie_sifive_setphy(0, 1, + PCIEX8MGMT_LANE + + (PCIEX8MGMT_LANE_OFF * lane), + PCIEX8MGMT_TERM_MODE, NULL, sv); + pcie_sifive_setphy(1, 1, + PCIEX8MGMT_LANE + + (PCIEX8MGMT_LANE_OFF * lane), + PCIEX8MGMT_TERM_MODE, NULL, sv); + } +} + +static int pcie_sifive_check_link(struct pcie_sifive *sv) +{ + u32 val; + + val = readl(sv->dw.dbi_base + PHY_DEBUG_R1); + return (val & PHY_DEBUG_R1_LINK_UP) && + !(val & PHY_DEBUG_R1_LINK_IN_TRAINING); +} + +static void pcie_sifive_force_gen1(struct pcie_sifive *sv) +{ + u32 val, linkcap; + + /* + * Force Gen1 operation when starting the link. In case the link is + * started in Gen2 mode, there is a possibility the devices on the + * bus will not be detected at all. This happens with PCIe switches. + */ + + /* ctrl_ro_wr_enable */ + val = readl(sv->dw.dbi_base + PCIE_MISC_CONTROL_1); + val |= DBI_RO_WR_EN; + writel(val, sv->dw.dbi_base + PCIE_MISC_CONTROL_1); + + /* configure link cap */ + linkcap = readl(sv->dw.dbi_base + PF0_PCIE_CAP_LINK_CAP); + linkcap |= PCIE_LINK_CAP_MAX_SPEED_MASK; + writel(linkcap, sv->dw.dbi_base + PF0_PCIE_CAP_LINK_CAP); + + /* ctrl_ro_wr_disable */ + val &= ~DBI_RO_WR_EN; + writel(val, sv->dw.dbi_base + PCIE_MISC_CONTROL_1); +} + +static void pcie_sifive_print_phy_debug(struct pcie_sifive *sv) +{ + sv_err(sv, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n", + readl(sv->dw.dbi_base + PHY_DEBUG_R0), + readl(sv->dw.dbi_base + PHY_DEBUG_R1)); +} + +static int pcie_sifive_wait_for_link(struct pcie_sifive *sv) +{ + u32 val; + int timeout; + + /* Wait for the link to train */ + mdelay(20); + timeout = 20; + + do { + mdelay(1); + } while (--timeout && !pcie_sifive_check_link(sv)); + + val = readl(sv->dw.dbi_base + PHY_DEBUG_R1); + if (!(val & PHY_DEBUG_R1_LINK_UP) || + (val & PHY_DEBUG_R1_LINK_IN_TRAINING)) { + sv_info(sv, "Failed to negotiate PCIe link!\n"); + pcie_sifive_print_phy_debug(sv); + writel(PCIE_PHY_RESET, + sv->priv_base + PCIEX8MGMT_APP_HOLD_PHY_RST); + return -ETIMEDOUT; + } + + return 0; +} + +static int pcie_sifive_start_link(struct pcie_sifive *sv) +{ + if (pcie_sifive_check_link(sv)) + return -EALREADY; + + pcie_sifive_force_gen1(sv); + + /* set ltssm */ + pcie_sifive_priv_set_state(sv, PCIEX8MGMT_APP_LTSSM_ENABLE, + LTSSM_ENABLE_BIT, 1); + return 0; +} + +static int pcie_sifive_init_port(struct udevice *dev, + enum pcie_sifive_devtype mode) +{ + struct pcie_sifive *sv = dev_get_priv(dev); + int ret; + + /* Power on reset */ + pcie_sifive_assert_reset(sv); + pcie_sifive_power_on(sv); + pcie_sifive_deassert_reset(sv); + + /* Enable pcieauxclk */ + ret = clk_enable(&sv->aux_ck); + if (ret) + dev_err(dev, "unable to enable pcie_aux clock\n"); + + /* + * assert hold_phy_rst (hold the controller LTSSM in reset + * after power_up_rst_n for register programming with cr_para) + */ + writel(PCIE_PHY_RESET, sv->priv_base + PCIEX8MGMT_APP_HOLD_PHY_RST); + + /* deassert power_up_rst_n */ + ret = reset_deassert(&sv->reset); + if (ret < 0) { + dev_err(dev, "failed to deassert reset"); + return -EINVAL; + } + + pcie_sifive_init_phy(sv); + + /* disable pcieauxclk */ + clk_disable(&sv->aux_ck); + + /* deassert hold_phy_rst */ + writel(PCIE_PHY_RESET_DEASSERT, + sv->priv_base + PCIEX8MGMT_APP_HOLD_PHY_RST); + + /* enable pcieauxclk */ + clk_enable(&sv->aux_ck); + + /* Set desired mode while core is not operational */ + if (mode == SV_PCIE_HOST_TYPE) + writel(DEVICE_TYPE_RC, + sv->priv_base + PCIEX8MGMT_DEVICE_TYPE); + else + writel(DEVICE_TYPE_EP, + sv->priv_base + PCIEX8MGMT_DEVICE_TYPE); + + /* Confirm desired mode from operational core */ + if (pcie_sifive_get_devtype(sv) != mode) + return -EINVAL; + + pcie_dw_setup_host(&sv->dw); + + if (pcie_sifive_start_link(sv) == -EALREADY) + sv_info(sv, "PCIe link is already up\n"); + else if (pcie_sifive_wait_for_link(sv) == -ETIMEDOUT) + return -ETIMEDOUT; + + return 0; +} + +static int pcie_sifive_probe(struct udevice *dev) +{ + struct pcie_sifive *sv = dev_get_priv(dev); + struct udevice *parent = pci_get_controller(dev); + struct pci_controller *hose = dev_get_uclass_priv(parent); + int err; + + sv->dw.first_busno = dev_seq(dev); + sv->dw.dev = dev; + + err = pcie_sifive_init_port(dev, SV_PCIE_HOST_TYPE); + if (err) { + sv_info(sv, "Failed to init port.\n"); + return err; + } + + printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n", + dev_seq(dev), pcie_dw_get_link_speed(&sv->dw), + pcie_dw_get_link_width(&sv->dw), + hose->first_busno); + + return pcie_dw_prog_outbound_atu_unroll(&sv->dw, + PCIE_ATU_REGION_INDEX0, + PCIE_ATU_TYPE_MEM, + sv->dw.mem.phys_start, + sv->dw.mem.bus_start, + sv->dw.mem.size); +} + +static void __iomem *get_fdt_addr(struct udevice *dev, const char *name) +{ + fdt_addr_t addr; + + addr = dev_read_addr_name(dev, name); + + return (addr == FDT_ADDR_T_NONE) ? NULL : (void __iomem *)addr; +} + +static int pcie_sifive_of_to_plat(struct udevice *dev) +{ + struct pcie_sifive *sv = dev_get_priv(dev); + int err; + + /* get designware DBI base addr */ + sv->dw.dbi_base = get_fdt_addr(dev, "dbi"); + if (!sv->dw.dbi_base) + return -EINVAL; + + /* get private control base addr */ + sv->priv_base = get_fdt_addr(dev, "mgmt"); + if (!sv->priv_base) + return -EINVAL; + + gpio_request_by_name(dev, "pwren-gpios", 0, &sv->pwren_gpio, + GPIOD_IS_OUT); + + if (!dm_gpio_is_valid(&sv->pwren_gpio)) { + sv_info(sv, "pwren_gpio is invalid\n"); + return -EINVAL; + } + + gpio_request_by_name(dev, "reset-gpios", 0, &sv->reset_gpio, + GPIOD_IS_OUT); + + if (!dm_gpio_is_valid(&sv->reset_gpio)) { + sv_info(sv, "reset_gpio is invalid\n"); + return -EINVAL; + } + + err = clk_get_by_index(dev, 0, &sv->aux_ck); + if (err) { + sv_info(sv, "clk_get_by_index(aux_ck) failed: %d\n", err); + return err; + } + + err = reset_get_by_index(dev, 0, &sv->reset); + if (err) { + sv_info(sv, "reset_get_by_index(reset) failed: %d\n", err); + return err; + } + + return 0; +} + +static const struct dm_pci_ops pcie_sifive_ops = { + .read_config = pcie_dw_read_config, + .write_config = pcie_dw_write_config, +}; + +static const struct udevice_id pcie_sifive_ids[] = { + { .compatible = "sifive,fu740-pcie" }, + {} +}; + +U_BOOT_DRIVER(pcie_sifive) = { + .name = "pcie_sifive", + .id = UCLASS_PCI, + .of_match = pcie_sifive_ids, + .ops = &pcie_sifive_ops, + .of_to_plat = pcie_sifive_of_to_plat, + .probe = pcie_sifive_probe, + .priv_auto = sizeof(struct pcie_sifive), +}; diff --git a/drivers/ram/sifive/Kconfig b/drivers/ram/sifive/Kconfig index 08de692e02..0aaac02656 100644 --- a/drivers/ram/sifive/Kconfig +++ b/drivers/ram/sifive/Kconfig @@ -5,9 +5,9 @@ config RAM_SIFIVE help This enables support for ram drivers of SiFive SoCs. -config SIFIVE_FU540_DDR - bool "SiFive FU540 DDR driver" +config SIFIVE_DDR + bool "SiFive DDR driver" depends on RAM_SIFIVE - default y if TARGET_SIFIVE_UNLEASHED + default y if TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED help - This enables DDR support for the platforms based on SiFive FU540 SoC. + This enables DDR support for the platforms based on SiFive SoC. diff --git a/drivers/ram/sifive/Makefile b/drivers/ram/sifive/Makefile index d66efec264..4ef89f85bb 100644 --- a/drivers/ram/sifive/Makefile +++ b/drivers/ram/sifive/Makefile @@ -3,4 +3,4 @@ # Copyright (c) 2020 SiFive, Inc # -obj-$(CONFIG_SIFIVE_FU540_DDR) += fu540_ddr.o +obj-$(CONFIG_SIFIVE_DDR) += sifive_ddr.o diff --git a/drivers/ram/sifive/fu540_ddr.c b/drivers/ram/sifive/sifive_ddr.c index c0653bb897..ba18466033 100644 --- a/drivers/ram/sifive/fu540_ddr.c +++ b/drivers/ram/sifive/sifive_ddr.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* - * (C) Copyright 2020 SiFive, Inc. + * (C) Copyright 2020-2021 SiFive, Inc. * * Authors: * Pragnesh Patel <pragnesh.patel@sifive.com> @@ -65,16 +65,16 @@ DECLARE_GLOBAL_DATA_PTR; -struct fu540_ddrctl { +struct sifive_ddrctl { volatile u32 denali_ctl[265]; }; -struct fu540_ddrphy { +struct sifive_ddrphy { volatile u32 denali_phy[1215]; }; /** - * struct fu540_ddr_info + * struct sifive_ddr_info * * @dev : pointer for the device * @info : UCLASS RAM information @@ -83,23 +83,23 @@ struct fu540_ddrphy { * @ctrl : DDR control base address * @physical_filter_ctrl : DDR physical filter control base address */ -struct fu540_ddr_info { +struct sifive_ddr_info { struct udevice *dev; struct ram_info info; - struct fu540_ddrctl *ctl; - struct fu540_ddrphy *phy; + struct sifive_ddrctl *ctl; + struct sifive_ddrphy *phy; struct clk ddr_clk; u32 *physical_filter_ctrl; }; #if defined(CONFIG_SPL_BUILD) -struct fu540_ddr_params { - struct fu540_ddrctl pctl_regs; - struct fu540_ddrphy phy_regs; +struct sifive_ddr_params { + struct sifive_ddrctl pctl_regs; + struct sifive_ddrphy phy_regs; }; struct sifive_dmc_plat { - struct fu540_ddr_params ddr_params; + struct sifive_ddr_params ddr_params; }; /* @@ -118,7 +118,7 @@ static void sdram_copy_to_reg(volatile u32 *dest, } } -static void fu540_ddr_setup_range_protection(volatile u32 *ctl, u64 end_addr) +static void sifive_ddr_setup_range_protection(volatile u32 *ctl, u64 end_addr) { u32 end_addr_16kblocks = ((end_addr >> 14) & 0x7FFFFF) - 1; @@ -135,8 +135,8 @@ static void fu540_ddr_setup_range_protection(volatile u32 *ctl, u64 end_addr) 0x1 << PORT_ADDR_PROTECTION_EN_OFFSET); } -static void fu540_ddr_start(volatile u32 *ctl, u32 *physical_filter_ctrl, - u64 ddr_end) +static void sifive_ddr_start(volatile u32 *ctl, u32 *physical_filter_ctrl, + u64 ddr_end) { volatile u64 *filterreg = (volatile u64 *)physical_filter_ctrl; @@ -149,7 +149,7 @@ static void fu540_ddr_start(volatile u32 *ctl, u32 *physical_filter_ctrl, filterreg[0] = 0x0f00000000000000UL | (ddr_end >> 2); } -static void fu540_ddr_check_errata(u32 regbase, u32 updownreg) +static void sifive_ddr_check_errata(u32 regbase, u32 updownreg) { u64 fails = 0; u32 dq = 0; @@ -202,7 +202,7 @@ static void fu540_ddr_check_errata(u32 regbase, u32 updownreg) } } -static u64 fu540_ddr_phy_fixup(volatile u32 *ddrphyreg) +static u64 sifive_ddr_phy_fixup(volatile u32 *ddrphyreg) { u32 slicebase = 0; @@ -213,7 +213,7 @@ static u64 fu540_ddr_phy_fixup(volatile u32 *ddrphyreg) for (u32 reg = 0; reg < 4; reg++) { u32 updownreg = readl(regbase + reg + ddrphyreg); - fu540_ddr_check_errata(regbase, updownreg); + sifive_ddr_check_errata(regbase, updownreg); } slicebase += 128; } @@ -221,18 +221,18 @@ static u64 fu540_ddr_phy_fixup(volatile u32 *ddrphyreg) return(0); } -static u32 fu540_ddr_get_dram_class(volatile u32 *ctl) +static u32 sifive_ddr_get_dram_class(volatile u32 *ctl) { u32 reg = readl(DENALI_CTL_0 + ctl); return ((reg >> DRAM_CLASS_OFFSET) & 0xF); } -static int fu540_ddr_setup(struct udevice *dev) +static int sifive_ddr_setup(struct udevice *dev) { - struct fu540_ddr_info *priv = dev_get_priv(dev); + struct sifive_ddr_info *priv = dev_get_priv(dev); struct sifive_dmc_plat *plat = dev_get_plat(dev); - struct fu540_ddr_params *params = &plat->ddr_params; + struct sifive_ddr_params *params = &plat->ddr_params; volatile u32 *denali_ctl = priv->ctl->denali_ctl; volatile u32 *denali_phy = priv->phy->denali_phy; const u64 ddr_size = priv->info.size; @@ -251,7 +251,7 @@ static int fu540_ddr_setup(struct udevice *dev) sdram_copy_to_reg(priv->ctl->denali_ctl, params->pctl_regs.denali_ctl, - sizeof(struct fu540_ddrctl)); + sizeof(struct sifive_ddrctl)); /* phy reset */ for (i = DENALI_PHY_1152; i <= DENALI_PHY_1214; i++) { @@ -285,7 +285,7 @@ static int fu540_ddr_setup(struct udevice *dev) setbits_le32(DENALI_CTL_182 + denali_ctl, 1 << DFI_PHY_RDLVL_GATE_MODE_OFFSET); - if (fu540_ddr_get_dram_class(denali_ctl) == DRAM_CLASS_DDR4) { + if (sifive_ddr_get_dram_class(denali_ctl) == DRAM_CLASS_DDR4) { /* Enable vref training DENALI_CTL_184 */ setbits_le32(DENALI_CTL_184 + denali_ctl, 1 << VREF_EN_OFFSET); } @@ -302,15 +302,15 @@ static int fu540_ddr_setup(struct udevice *dev) | (1 << MULTIPLE_OUT_OF_RANGE_OFFSET)); /* set up range protection */ - fu540_ddr_setup_range_protection(denali_ctl, priv->info.size); + sifive_ddr_setup_range_protection(denali_ctl, priv->info.size); /* Mask off port command error interrupt DENALI_CTL_136 */ setbits_le32(DENALI_CTL_136 + denali_ctl, 1 << PORT_COMMAND_CHANNEL_ERROR_OFFSET); - fu540_ddr_start(denali_ctl, priv->physical_filter_ctrl, ddr_end); + sifive_ddr_start(denali_ctl, priv->physical_filter_ctrl, ddr_end); - fu540_ddr_phy_fixup(denali_phy); + sifive_ddr_phy_fixup(denali_phy); /* check size */ priv->info.size = get_ram_size((long *)priv->info.base, @@ -329,9 +329,9 @@ static int fu540_ddr_setup(struct udevice *dev) } #endif -static int fu540_ddr_probe(struct udevice *dev) +static int sifive_ddr_probe(struct udevice *dev) { - struct fu540_ddr_info *priv = dev_get_priv(dev); + struct sifive_ddr_info *priv = dev_get_priv(dev); /* Read memory base and size from DT */ fdtdec_setup_mem_size_base(); @@ -342,7 +342,7 @@ static int fu540_ddr_probe(struct udevice *dev) int ret; u32 clock = 0; - debug("FU540 DDR probe\n"); + debug("sifive DDR probe\n"); priv->dev = dev; ret = clk_get_by_index(dev, 0, &priv->ddr_clk); @@ -369,42 +369,43 @@ static int fu540_ddr_probe(struct udevice *dev) return ret; } - priv->ctl = (struct fu540_ddrctl *)dev_read_addr_index(dev, 0); - priv->phy = (struct fu540_ddrphy *)dev_read_addr_index(dev, 1); + priv->ctl = (struct sifive_ddrctl *)dev_read_addr_index(dev, 0); + priv->phy = (struct sifive_ddrphy *)dev_read_addr_index(dev, 1); priv->physical_filter_ctrl = (u32 *)dev_read_addr_index(dev, 2); - return fu540_ddr_setup(dev); + return sifive_ddr_setup(dev); #endif return 0; } -static int fu540_ddr_get_info(struct udevice *dev, struct ram_info *info) +static int sifive_ddr_get_info(struct udevice *dev, struct ram_info *info) { - struct fu540_ddr_info *priv = dev_get_priv(dev); + struct sifive_ddr_info *priv = dev_get_priv(dev); *info = priv->info; return 0; } -static struct ram_ops fu540_ddr_ops = { - .get_info = fu540_ddr_get_info, +static struct ram_ops sifive_ddr_ops = { + .get_info = sifive_ddr_get_info, }; -static const struct udevice_id fu540_ddr_ids[] = { +static const struct udevice_id sifive_ddr_ids[] = { { .compatible = "sifive,fu540-c000-ddr" }, + { .compatible = "sifive,fu740-c000-ddr" }, { } }; -U_BOOT_DRIVER(fu540_ddr) = { - .name = "fu540_ddr", +U_BOOT_DRIVER(sifive_ddr) = { + .name = "sifive_ddr", .id = UCLASS_RAM, - .of_match = fu540_ddr_ids, - .ops = &fu540_ddr_ops, - .probe = fu540_ddr_probe, - .priv_auto = sizeof(struct fu540_ddr_info), + .of_match = sifive_ddr_ids, + .ops = &sifive_ddr_ops, + .probe = sifive_ddr_probe, + .priv_auto = sizeof(struct sifive_ddr_info), #if defined(CONFIG_SPL_BUILD) - .plat_auto = sizeof(struct sifive_dmc_plat), + .plat_auto = sizeof(struct sifive_dmc_plat), #endif }; diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 019565f979..a42b3f0077 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -166,7 +166,7 @@ config RESET_IPQ419 config RESET_SIFIVE bool "Reset Driver for SiFive SoC's" - depends on DM_RESET && CLK_SIFIVE_FU540_PRCI && TARGET_SIFIVE_UNLEASHED + depends on DM_RESET && CLK_SIFIVE_PRCI && (TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED) default y help PRCI module within SiFive SoC's provides mechanism to reset |