diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/imx/clk-imx8mm.c | 23 | ||||
| -rw-r--r-- | drivers/mtd/spi/spi-nor-ids.c | 2 | ||||
| -rw-r--r-- | drivers/net/Kconfig | 7 | ||||
| -rw-r--r-- | drivers/net/Makefile | 1 | ||||
| -rw-r--r-- | drivers/net/fec_mxc.c | 21 | ||||
| -rw-r--r-- | drivers/net/fec_mxc.h | 1 | ||||
| -rw-r--r-- | drivers/net/ksz9477.c | 546 | ||||
| -rw-r--r-- | drivers/pci/pcie_imx.c | 29 | ||||
| -rw-r--r-- | drivers/phy/Kconfig | 7 | ||||
| -rw-r--r-- | drivers/phy/Makefile | 1 | ||||
| -rw-r--r-- | drivers/phy/phy-imx8mq-usb.c | 197 | ||||
| -rw-r--r-- | drivers/spi/Makefile | 2 | ||||
| -rw-r--r-- | drivers/spi/mxc_spi.c | 4 | ||||
| -rw-r--r-- | drivers/watchdog/ulp_wdog.c | 57 |
14 files changed, 867 insertions, 31 deletions
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index d32ff8409a..3aa8c641f9 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -131,6 +131,15 @@ static const char *imx8mm_usb_core_sels[] = {"clock-osc-24m", "sys_pll1_100m", " static const char *imx8mm_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_100m", "sys_pll1_40m", "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", "clk_ext3", "audio_pll2_out", }; +static const char *imx8mm_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", + "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; + +static const char *imx8mm_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", + "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; + +static const char *imx8mm_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m", "sys_pll1_160m", + "sys_pll1_800m", "sys_pll3_out", "sys_pll2_250m", "audio_pll2_out", }; + static ulong imx8mm_clk_get_rate(struct clk *clk) { struct clk *c; @@ -393,7 +402,19 @@ static int imx8mm_clk_probe(struct udevice *dev) imx8m_clk_composite("usb_core_ref", imx8mm_usb_core_sels, base + 0xb100)); clk_dm(IMX8MM_CLK_USB_PHY_REF, imx8m_clk_composite("usb_phy_ref", imx8mm_usb_phy_sels, base + 0xb180)); - + clk_dm(IMX8MM_CLK_ECSPI1, + imx8m_clk_composite("ecspi1", imx8mm_ecspi1_sels, base + 0xb280)); + clk_dm(IMX8MM_CLK_ECSPI2, + imx8m_clk_composite("ecspi2", imx8mm_ecspi2_sels, base + 0xb300)); + clk_dm(IMX8MM_CLK_ECSPI3, + imx8m_clk_composite("ecspi3", imx8mm_ecspi3_sels, base + 0xc180)); + + clk_dm(IMX8MM_CLK_ECSPI1_ROOT, + imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0)); + clk_dm(IMX8MM_CLK_ECSPI2_ROOT, + imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0)); + clk_dm(IMX8MM_CLK_ECSPI3_ROOT, + imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0)); clk_dm(IMX8MM_CLK_I2C1_ROOT, imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0)); clk_dm(IMX8MM_CLK_I2C2_ROOT, diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 1af1c86486..6f84c54a47 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -160,6 +160,8 @@ const struct flash_info spi_nor_ids[] = { { INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) }, { INFO("mx25l25635e", 0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("mx25u25635f", 0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) }, + { INFO("mx25v8035f", 0xc22314, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("mx25r1635f", 0xc22815, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("mx25l25655e", 0xc22619, 0, 64 * 1024, 512, 0) }, { INFO("mx66l51235l", 0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx66u51235f", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 483401681d..726ad36b7c 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -402,6 +402,13 @@ config KS8851_MLL_BASEADDR endif #DM_ETH endif #KS8851_MLL +config KSZ9477 + bool "Microchip KSZ9477 I2C controller driver" + depends on DM_DSA && DM_I2C + help + This driver implements a DSA switch driver for the KSZ9477 family + of GbE switches using the I2C interface. + config MVGBE bool "Marvell Orion5x/Kirkwood network interface support" depends on ARCH_KIRKWOOD || ARCH_ORION5X diff --git a/drivers/net/Makefile b/drivers/net/Makefile index d56baa65b2..03900ffa3a 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_FTMAC110) += ftmac110.o obj-$(CONFIG_FTMAC100) += ftmac100.o obj-$(CONFIG_GMAC_ROCKCHIP) += gmac_rockchip.o obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o +obj-$(CONFIG_KSZ9477) += ksz9477.o obj-$(CONFIG_LAN91C96) += lan91c96.o obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o obj-$(CONFIG_MACB) += macb.o diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 4fd5c01b4a..db2cdaf684 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -146,7 +146,7 @@ static int fec_get_clk_rate(void *udev, int idx) CONFIG_IS_ENABLED(CLK_CCF)) { dev = udev; if (!dev) { - ret = uclass_get_device(UCLASS_ETH, idx, &dev); + ret = uclass_get_device_by_seq(UCLASS_ETH, idx, &dev); if (ret < 0) { debug("Can't get FEC udev: %d\n", ret); return ret; @@ -458,6 +458,9 @@ static void fec_reg_setup(struct fec_priv *fec) else if (fec->xcv_type == RMII) rcntrl |= FEC_RCNTRL_RMII; + if (fec->promisc) + rcntrl |= 0x8; + writel(rcntrl, &fec->eth->r_cntrl); } @@ -1278,6 +1281,15 @@ static int fecmxc_read_rom_hwaddr(struct udevice *dev) return fec_get_hwaddr(priv->dev_id, pdata->enetaddr); } +static int fecmxc_set_promisc(struct udevice *dev, bool enable) +{ + struct fec_priv *priv = dev_get_priv(dev); + + priv->promisc = enable; + + return 0; +} + static int fecmxc_free_pkt(struct udevice *dev, uchar *packet, int length) { if (packet) @@ -1294,6 +1306,7 @@ static const struct eth_ops fecmxc_ops = { .stop = fecmxc_halt, .write_hwaddr = fecmxc_set_hwaddr, .read_rom_hwaddr = fecmxc_read_rom_hwaddr, + .set_promisc = fecmxc_set_promisc, }; static int device_get_phy_addr(struct fec_priv *priv, struct udevice *dev) @@ -1304,7 +1317,11 @@ static int device_get_phy_addr(struct fec_priv *priv, struct udevice *dev) ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &phandle_args); if (ret) { - debug("Failed to find phy-handle (err = %d\n)", ret); + priv->phy_of_node = ofnode_find_subnode(dev_ofnode(dev), + "fixed-link"); + if (ofnode_valid(priv->phy_of_node)) + return 0; + debug("Failed to find phy-handle (err = %d)\n", ret); return ret; } diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h index 5ccde9193b..62b55ef395 100644 --- a/drivers/net/fec_mxc.h +++ b/drivers/net/fec_mxc.h @@ -272,6 +272,7 @@ struct fec_priv { struct clk clk_ref; struct clk clk_ptp; u32 clk_rate; + char promisc; }; /** diff --git a/drivers/net/ksz9477.c b/drivers/net/ksz9477.c new file mode 100644 index 0000000000..ed8f1895cb --- /dev/null +++ b/drivers/net/ksz9477.c @@ -0,0 +1,546 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2020 + * Tim Harvey, Gateworks Corporation + */ + +#include <dm.h> +#include <dm/device_compat.h> +#include <dm/device-internal.h> +#include <dm/lists.h> +#include <eth_phy.h> +#include <linux/delay.h> +#include <miiphy.h> +#include <i2c.h> +#include <net/dsa.h> + +#include <asm-generic/gpio.h> + +/* Global registers */ + +/* Chip ID */ +#define REG_CHIP_ID0__1 0x0000 + +/* Operation control */ +#define REG_SW_OPERATION 0x0300 +#define SW_RESET BIT(1) +#define SW_START BIT(0) + +/* Port Specific Registers */ +#define PORT_CTRL_ADDR(port, addr) ((addr) | (((port) + 1) << 12)) + +/* Port Control */ +#define REG_PORT_XMII_CTRL_1 0x0301 +#define PORT_MII_NOT_1GBIT BIT(6) +#define PORT_MII_SEL_EDGE BIT(5) +#define PORT_RGMII_ID_IG_ENABLE BIT(4) +#define PORT_RGMII_ID_EG_ENABLE BIT(3) +#define PORT_MII_MAC_MODE BIT(2) +#define PORT_MII_SEL_M 0x3 +#define PORT_RGMII_SEL 0x0 +#define PORT_RMII_SEL 0x1 +#define PORT_GMII_SEL 0x2 +#define PORT_MII_SEL 0x3 + +/* Port MSTP State Register */ +#define REG_PORT_MSTP_STATE 0x0b04 +#define PORT_TX_ENABLE BIT(2) +#define PORT_RX_ENABLE BIT(1) +#define PORT_LEARN_DISABLE BIT(0) + +/* MMD */ +#define REG_PORT_PHY_MMD_SETUP 0x011A +#define PORT_MMD_OP_MODE_M 0x3 +#define PORT_MMD_OP_MODE_S 14 +#define PORT_MMD_OP_INDEX 0 +#define PORT_MMD_OP_DATA_NO_INCR 1 +#define PORT_MMD_OP_DATA_INCR_RW 2 +#define PORT_MMD_OP_DATA_INCR_W 3 +#define PORT_MMD_DEVICE_ID_M 0x1F +#define MMD_SETUP(mode, dev) (((u16)(mode) << PORT_MMD_OP_MODE_S) | (dev)) +#define REG_PORT_PHY_MMD_INDEX_DATA 0x011C + +struct ksz_dsa_priv { + struct udevice *dev; + int active_port; +}; + +static inline int ksz_read8(struct udevice *dev, u32 reg, u8 *val) +{ + int ret = dm_i2c_read(dev, reg, val, 1); + + dev_dbg(dev, "%s 0x%04x<<0x%02x\n", __func__, reg, *val); + + return ret; +} + +static inline int ksz_pread8(struct udevice *dev, int port, int reg, u8 *val) +{ + return ksz_read8(dev, PORT_CTRL_ADDR(port, reg), val); +} + +static inline int ksz_write8(struct udevice *dev, u32 reg, u8 val) +{ + dev_dbg(dev, "%s 0x%04x>>0x%02x\n", __func__, reg, val); + return dm_i2c_write(dev, reg, &val, 1); +} + +static inline int ksz_pwrite8(struct udevice *dev, int port, int reg, u8 val) +{ + return ksz_write8(dev, PORT_CTRL_ADDR(port, reg), val); +} + +static inline int ksz_write16(struct udevice *dev, u32 reg, u16 val) +{ + u8 buf[2]; + + buf[1] = val & 0xff; + buf[0] = val >> 8; + dev_dbg(dev, "%s 0x%04x>>0x%04x\n", __func__, reg, val); + + return dm_i2c_write(dev, reg, buf, 2); +} + +static inline int ksz_pwrite16(struct udevice *dev, int port, int reg, u16 val) +{ + return ksz_write16(dev, PORT_CTRL_ADDR(port, reg), val); +} + +static inline int ksz_read16(struct udevice *dev, u32 reg, u16 *val) +{ + u8 buf[2]; + int ret; + + ret = dm_i2c_read(dev, reg, buf, 2); + *val = (buf[0] << 8) | buf[1]; + dev_dbg(dev, "%s 0x%04x<<0x%04x\n", __func__, reg, *val); + + return ret; +} + +static inline int ksz_pread16(struct udevice *dev, int port, int reg, u16 *val) +{ + return ksz_read16(dev, PORT_CTRL_ADDR(port, reg), val); +} + +static inline int ksz_read32(struct udevice *dev, u32 reg, u32 *val) +{ + return dm_i2c_read(dev, reg, (u8 *)val, 4); +} + +static inline int ksz_pread32(struct udevice *dev, int port, int reg, u32 *val) +{ + return ksz_read32(dev, PORT_CTRL_ADDR(port, reg), val); +} + +static inline int ksz_write32(struct udevice *dev, u32 reg, u32 val) +{ + u8 buf[4]; + + buf[3] = val & 0xff; + buf[2] = (val >> 24) & 0xff; + buf[1] = (val >> 16) & 0xff; + buf[0] = (val >> 8) & 0xff; + dev_dbg(dev, "%s 0x%04x>>0x%04x\n", __func__, reg, val); + + return dm_i2c_write(dev, reg, buf, 4); +} + +static inline int ksz_pwrite32(struct udevice *dev, int port, int reg, u32 val) +{ + return ksz_write32(dev, PORT_CTRL_ADDR(port, reg), val); +} + +static __maybe_unused void ksz_port_mmd_read(struct udevice *dev, int port, + u8 addr, u16 reg, u16 *val) +{ + ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, MMD_SETUP(PORT_MMD_OP_INDEX, addr)); + ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, reg); + ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, MMD_SETUP(PORT_MMD_OP_DATA_NO_INCR, addr)); + ksz_pread16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, val); + dev_dbg(dev, "%s P%d 0x%02x:0x%04x<<0x%04x\n", __func__, port + 1, addr, reg, *val); +} + +static void ksz_port_mmd_write(struct udevice *dev, int port, u8 addr, u16 reg, u16 val) +{ + dev_dbg(dev, "%s P%d 0x%02x:0x%04x>>0x%04x\n", __func__, port + 1, addr, addr, val); + ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, MMD_SETUP(PORT_MMD_OP_INDEX, addr)); + ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, addr); + ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_SETUP, MMD_SETUP(PORT_MMD_OP_DATA_NO_INCR, addr)); + ksz_pwrite16(dev, port, REG_PORT_PHY_MMD_INDEX_DATA, val); +} + +/* Apply PHY settings to address errata listed in KSZ9477, KSZ9897, KSZ9896, KSZ9567 + * Silicon Errata and Data Sheet Clarification documents + */ +static void ksz_phy_errata_setup(struct udevice *dev, int port) +{ + dev_dbg(dev, "%s P%d\n", __func__, port + 1); + + /* Register settings are needed to improve PHY receive performance */ + ksz_port_mmd_write(dev, port, 0x01, 0x6f, 0xdd0b); + ksz_port_mmd_write(dev, port, 0x01, 0x8f, 0x6032); + ksz_port_mmd_write(dev, port, 0x01, 0x9d, 0x248c); + ksz_port_mmd_write(dev, port, 0x01, 0x75, 0x0060); + ksz_port_mmd_write(dev, port, 0x01, 0xd3, 0x7777); + ksz_port_mmd_write(dev, port, 0x1c, 0x06, 0x3008); + ksz_port_mmd_write(dev, port, 0x1c, 0x08, 0x2001); + + /* Transmit waveform amplitude can be improved (1000BASE-T, 100BASE-TX, 10BASE-Te) */ + ksz_port_mmd_write(dev, port, 0x1c, 0x04, 0x00d0); + + /* Energy Efficient Ethernet (EEE) feature select must be manually disabled */ + ksz_port_mmd_write(dev, port, 0x07, 0x3c, 0x0000); + + /* Register settings are required to meet data sheet supply current specifications */ + ksz_port_mmd_write(dev, port, 0x1c, 0x13, 0x6eff); + ksz_port_mmd_write(dev, port, 0x1c, 0x14, 0xe6ff); + ksz_port_mmd_write(dev, port, 0x1c, 0x15, 0x6eff); + ksz_port_mmd_write(dev, port, 0x1c, 0x16, 0xe6ff); + ksz_port_mmd_write(dev, port, 0x1c, 0x17, 0x00ff); + ksz_port_mmd_write(dev, port, 0x1c, 0x18, 0x43ff); + ksz_port_mmd_write(dev, port, 0x1c, 0x19, 0xc3ff); + ksz_port_mmd_write(dev, port, 0x1c, 0x1a, 0x6fff); + ksz_port_mmd_write(dev, port, 0x1c, 0x1b, 0x07ff); + ksz_port_mmd_write(dev, port, 0x1c, 0x1c, 0x0fff); + ksz_port_mmd_write(dev, port, 0x1c, 0x1d, 0xe7ff); + ksz_port_mmd_write(dev, port, 0x1c, 0x1e, 0xefff); + ksz_port_mmd_write(dev, port, 0x1c, 0x20, 0xeeee); +} + +/* + * mii bus driver + */ +#define KSZ_MDIO_CHILD_DRV_NAME "ksz_mdio" + +struct ksz_mdio_priv { + struct ksz_dsa_priv *ksz; +}; + +static int dm_ksz_mdio_read(struct udevice *dev, int addr, int devad, int reg) +{ + struct ksz_mdio_priv *priv = dev_get_priv(dev); + struct ksz_dsa_priv *ksz = priv->ksz; + u16 val = 0xffff; + + ksz_pread16(ksz->dev, addr, 0x100 + (reg << 1), &val); + dev_dbg(ksz->dev, "%s P%d reg=0x%04x:0x%04x<<0x%04x\n", __func__, + addr + 1, reg, 0x100 + (reg << 1), val); + + return val; +}; + +static int dm_ksz_mdio_write(struct udevice *dev, int addr, int devad, int reg, u16 val) +{ + struct ksz_mdio_priv *priv = dev_get_priv(dev); + struct ksz_dsa_priv *ksz = priv->ksz; + + dev_dbg(ksz->dev, "%s P%d reg=0x%04x:%04x>>0x%04x\n", + __func__, addr + 1, reg, 0x100 + (reg << 1), val); + ksz_pwrite16(ksz->dev, addr, 0x100 + (reg << 1), val); + + return 0; +} + +static const struct mdio_ops ksz_mdio_ops = { + .read = dm_ksz_mdio_read, + .write = dm_ksz_mdio_write, +}; + +static int ksz_mdio_bind(struct udevice *dev) +{ + char name[16]; + static int num_devices; + + dev_dbg(dev, "%s\n", __func__); + sprintf(name, "ksz-mdio-%d", num_devices++); + device_set_name(dev, name); + + return 0; +} + +static int ksz_mdio_probe(struct udevice *dev) +{ + struct ksz_mdio_priv *priv = dev_get_priv(dev); + + dev_dbg(dev, "%s\n", __func__); + priv->ksz = dev_get_parent_priv(dev->parent); + + return 0; +} + +static const struct udevice_id ksz_mdio_ids[] = { + { .compatible = "microchip,ksz-mdio" }, + { } +}; + +U_BOOT_DRIVER(ksz_mdio) = { + .name = KSZ_MDIO_CHILD_DRV_NAME, + .id = UCLASS_MDIO, + .of_match = ksz_mdio_ids, + .bind = ksz_mdio_bind, + .probe = ksz_mdio_probe, + .ops = &ksz_mdio_ops, + .priv_auto = sizeof(struct ksz_mdio_priv), + .plat_auto = sizeof(struct mdio_perdev_priv), +}; + +static int ksz_port_setup(struct udevice *dev, int port, + phy_interface_t interface) +{ + struct dsa_pdata *pdata = dev_get_uclass_plat(dev); + u8 data8; + + dev_dbg(dev, "%s P%d %s\n", __func__, port + 1, + (port == pdata->cpu_port) ? "cpu" : ""); + + if (port != pdata->cpu_port) { + /* phy port: config errata and leds */ + ksz_phy_errata_setup(dev, port); + } else { + /* cpu port: configure MAC interface mode */ + ksz_pread8(dev, port, REG_PORT_XMII_CTRL_1, &data8); + dev_dbg(dev, "%s P%d cpu interface %s\n", __func__, port + 1, + phy_string_for_interface(interface)); + switch (interface) { + case PHY_INTERFACE_MODE_MII: + data8 &= ~PORT_MII_SEL_M; + data8 |= PORT_MII_SEL; + data8 |= PORT_MII_NOT_1GBIT; + break; + case PHY_INTERFACE_MODE_RMII: + data8 &= ~PORT_MII_SEL_M; + data8 |= PORT_RMII_SEL; + data8 |= PORT_MII_NOT_1GBIT; + break; + case PHY_INTERFACE_MODE_GMII: + data8 &= ~PORT_MII_SEL_M; + data8 |= PORT_GMII_SEL; + data8 &= ~PORT_MII_NOT_1GBIT; + break; + default: + data8 &= ~PORT_MII_SEL_M; + data8 |= PORT_RGMII_SEL; + data8 &= ~PORT_MII_NOT_1GBIT; + data8 &= ~PORT_RGMII_ID_IG_ENABLE; + data8 &= ~PORT_RGMII_ID_EG_ENABLE; + if (interface == PHY_INTERFACE_MODE_RGMII_ID || + interface == PHY_INTERFACE_MODE_RGMII_RXID) + data8 |= PORT_RGMII_ID_IG_ENABLE; + if (interface == PHY_INTERFACE_MODE_RGMII_ID || + interface == PHY_INTERFACE_MODE_RGMII_TXID) + data8 |= PORT_RGMII_ID_EG_ENABLE; + break; + } + ksz_write8(dev, PORT_CTRL_ADDR(port, REG_PORT_XMII_CTRL_1), data8); + } + + return 0; +} + +static int ksz_port_enable(struct udevice *dev, int port, struct phy_device *phy) +{ + struct dsa_pdata *pdata = dev_get_uclass_plat(dev); + struct ksz_dsa_priv *priv = dev_get_priv(dev); + int supported = PHY_GBIT_FEATURES; + u8 data8; + int ret; + + dev_dbg(dev, "%s P%d 0x%x %s\n", __func__, port + 1, phy->phy_id, + phy_string_for_interface(phy->interface)); + + /* setup this port */ + ret = ksz_port_setup(dev, port, phy->interface); + if (ret) { + dev_err(dev, "port setup failed: %d\n", ret); + return ret; + } + + /* enable port forwarding for this port */ + ksz_pread8(priv->dev, port, REG_PORT_MSTP_STATE, &data8); + data8 &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); + data8 |= (PORT_TX_ENABLE | PORT_RX_ENABLE); + ksz_pwrite8(priv->dev, port, REG_PORT_MSTP_STATE, data8); + + /* if cpu master we are done */ + if (port == pdata->cpu_port) + return 0; + + /* configure phy */ + phy->supported &= supported; + phy->advertising &= supported; + ret = phy_config(phy); + if (ret) + return ret; + + ret = phy_startup(phy); + if (ret) + return ret; + + /* start switch */ + ksz_read8(priv->dev, REG_SW_OPERATION, &data8); + data8 |= SW_START; + ksz_write8(priv->dev, REG_SW_OPERATION, data8); + + /* keep track of current enabled non-cpu port */ + priv->active_port = port; + + return 0; +} + +static void ksz_port_disable(struct udevice *dev, int port, struct phy_device *phy) +{ + struct dsa_pdata *pdata = dev_get_uclass_plat(dev); + struct ksz_dsa_priv *priv = dev_get_priv(dev); + u8 data8; + + dev_dbg(dev, "%s P%d 0x%x\n", __func__, port + 1, phy->phy_id); + + /* can't disable CPU port without re-configuring/re-starting switch */ + if (port == pdata->cpu_port) + return; + + /* disable port */ + ksz_pread8(priv->dev, port, REG_PORT_MSTP_STATE, &data8); + data8 &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); + data8 |= PORT_LEARN_DISABLE; + ksz_pwrite8(priv->dev, port, REG_PORT_MSTP_STATE, data8); + + /* + * we don't call phy_shutdown here to avoid waiting next time we use + * the port, but the downside is that remote side will think we're + * actively processing traffic although we are not. + */ +} + +static int ksz_xmit(struct udevice *dev, int port, void *packet, int length) +{ + dev_dbg(dev, "%s P%d %d\n", __func__, port + 1, length); + + return 0; +} + +static int ksz_recv(struct udevice *dev, int *port, void *packet, int length) +{ + struct ksz_dsa_priv *priv = dev_get_priv(dev); + + dev_dbg(dev, "%s P%d %d\n", __func__, priv->active_port + 1, length); + *port = priv->active_port; + + return 0; +}; + +static const struct dsa_ops ksz_dsa_ops = { + .port_enable = ksz_port_enable, + .port_disable = ksz_port_disable, + .xmit = ksz_xmit, + .rcv = ksz_recv, +}; + +static int ksz_probe_mdio(struct udevice *dev) +{ + ofnode node, mdios; + int ret; + + mdios = dev_read_subnode(dev, "mdios"); + if (ofnode_valid(mdios)) { + ofnode_for_each_subnode(node, mdios) { + const char *name = ofnode_get_name(node); + struct udevice *pdev; + + ret = device_bind_driver_to_node(dev, + KSZ_MDIO_CHILD_DRV_NAME, + name, node, &pdev); + if (ret) + dev_err(dev, "failed to probe %s: %d\n", name, ret); + } + } + + return 0; +} + +/* + * I2C driver + */ +static int ksz_i2c_probe(struct udevice *dev) +{ + struct dsa_pdata *pdata = dev_get_uclass_plat(dev); + struct ksz_dsa_priv *priv = dev_get_priv(dev); + struct udevice *master = dsa_get_master(dev); + int i, ret; + u8 data8; + u32 id; + + if (!master) + return -ENODEV; + + dev_dbg(dev, "%s %s master:%s\n", __func__, dev->name, master->name); + dev_set_parent_priv(dev, priv); + + ret = i2c_set_chip_offset_len(dev, 2); + if (ret) { + printf("i2c_set_chip_offset_len failed: %d\n", ret); + return ret; + } + + /* default config */ + priv->dev = dev; + + /* chip level reset */ + ksz_read8(priv->dev, REG_SW_OPERATION, &data8); + data8 |= SW_RESET; + ksz_write8(priv->dev, REG_SW_OPERATION, data8); + + /* read chip id */ + ret = ksz_read32(dev, REG_CHIP_ID0__1, &id); + if (ret) + return ret; + id = __swab32(id); + dev_dbg(dev, "%s id=0x%08x\n", __func__, id); + switch (id & 0xffffff00) { + case 0x00947700: + puts("KSZ9477S: "); + break; + case 0x00956700: + puts("KSZ9567R: "); + break; + case 0x00989700: + puts("KSZ9897S: "); + break; + default: + dev_err(dev, "invalid chip id: 0x%08x\n", id); + return -EINVAL; + } + + /* probe mdio bus */ + ret = ksz_probe_mdio(dev); + if (ret) + return ret; + + /* disable ports by default */ + for (i = 0; i < pdata->num_ports; i++) { + ksz_pread8(priv->dev, i, REG_PORT_MSTP_STATE, &data8); + data8 &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); + ksz_pwrite8(priv->dev, i, REG_PORT_MSTP_STATE, data8); + } + + dsa_set_tagging(dev, 0, 0); + + return 0; +}; + +static const struct udevice_id ksz_i2c_ids[] = { + { .compatible = "microchip,ksz9897" }, + { .compatible = "microchip,ksz9477" }, + { .compatible = "microchip,ksz9567" }, + { } +}; + +U_BOOT_DRIVER(ksz) = { + .name = "ksz-switch", + .id = UCLASS_DSA, + .of_match = ksz_i2c_ids, + .probe = ksz_i2c_probe, + .ops = &ksz_dsa_ops, + .priv_auto = sizeof(struct ksz_dsa_priv), +}; diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index 73875e00db..7b46fdb89a 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -100,6 +100,8 @@ struct imx_pcie_priv { void __iomem *dbi_base; void __iomem *cfg_base; + struct gpio_desc reset_gpio; + bool reset_active_high; }; /* @@ -541,7 +543,7 @@ __weak int imx6_pcie_toggle_power(void) return 0; } -__weak int imx6_pcie_toggle_reset(void) +__weak int imx6_pcie_toggle_reset(struct gpio_desc *gpio, bool active_high) { /* * See 'PCI EXPRESS BASE SPECIFICATION, REV 3.0, SECTION 6.6.1' @@ -579,12 +581,20 @@ __weak int imx6_pcie_toggle_reset(void) mdelay(20); gpio_free(CONFIG_PCIE_IMX_PERST_GPIO); #else - puts("WARNING: Make sure the PCIe #PERST line is connected!\n"); + if (dm_gpio_is_valid(gpio)) { + /* Assert PERST# for 20ms then de-assert */ + dm_gpio_set_value(gpio, active_high ? 0 : 1); + mdelay(20); + dm_gpio_set_value(gpio, active_high ? 1 : 0); + mdelay(20); + } else { + puts("WARNING: Make sure the PCIe #PERST line is connected!\n"); + } #endif return 0; } -static int imx6_pcie_deassert_core_reset(void) +static int imx6_pcie_deassert_core_reset(struct imx_pcie_priv *priv) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; @@ -612,7 +622,7 @@ static int imx6_pcie_deassert_core_reset(void) setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); #endif - imx6_pcie_toggle_reset(); + imx6_pcie_toggle_reset(&priv->reset_gpio, priv->reset_active_high); return 0; } @@ -625,7 +635,7 @@ static int imx_pcie_link_up(struct imx_pcie_priv *priv) imx6_pcie_assert_core_reset(priv, false); imx6_pcie_init_phy(); - imx6_pcie_deassert_core_reset(); + imx6_pcie_deassert_core_reset(priv); imx_pcie_regions_setup(priv); @@ -787,6 +797,15 @@ static int imx_pcie_dm_probe(struct udevice *dev) { struct imx_pcie_priv *priv = dev_get_priv(dev); + /* if PERST# valid from dt then assert it */ + gpio_request_by_name(dev, "reset-gpio", 0, &priv->reset_gpio, + GPIOD_IS_OUT); + priv->reset_active_high = dev_read_bool(dev, "reset-gpio-active-high"); + if (dm_gpio_is_valid(&priv->reset_gpio)) { + dm_gpio_set_value(&priv->reset_gpio, + priv->reset_active_high ? 0 : 1); + } + return imx_pcie_link_up(priv); } diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 92c74b9d0b..80ae1af329 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -274,5 +274,12 @@ config PHY_MTK_TPHY multi-ports is first version, otherwise is second veriosn, so you can easily distinguish them by banks layout. +config PHY_IMX8MQ_USB + bool "NXP i.MX8MQ USB PHY Driver" + depends on PHY + depends on IMX8MQ + help + Support the USB3.0 PHY in NXP i.MX8MQ SoC + source "drivers/phy/rockchip/Kconfig" endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index bf03d05d9b..0f2b63ae3c 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -32,3 +32,4 @@ obj-$(CONFIG_MT7620_USB_PHY) += mt7620-usb-phy.o obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o +obj-$(CONFIG_PHY_IMX8MQ_USB) += phy-imx8mq-usb.o diff --git a/drivers/phy/phy-imx8mq-usb.c b/drivers/phy/phy-imx8mq-usb.c new file mode 100644 index 0000000000..afbc7ad8dd --- /dev/null +++ b/drivers/phy/phy-imx8mq-usb.c @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + * + */ + +#include <common.h> +#include <asm/io.h> +#include <dm.h> +#include <errno.h> +#include <generic-phy.h> +#include <linux/bitops.h> +#include <linux/err.h> +#include <clk.h> + +#define PHY_CTRL0 0x0 +#define PHY_CTRL0_REF_SSP_EN BIT(2) +#define PHY_CTRL0_FSEL_MASK GENMASK(10, 5) +#define PHY_CTRL0_FSEL_24M 0x2a +#define PHY_CTRL0_FSEL_100M 0x27 +#define PHY_CTRL0_SSC_RANGE_MASK GENMASK(23, 21) +#define PHY_CTRL0_SSC_RANGE_4003PPM (0x2 << 21) + +#define PHY_CTRL1 0x4 +#define PHY_CTRL1_RESET BIT(0) +#define PHY_CTRL1_COMMONONN BIT(1) +#define PHY_CTRL1_ATERESET BIT(3) +#define PHY_CTRL1_DCDENB BIT(17) +#define PHY_CTRL1_CHRGSEL BIT(18) +#define PHY_CTRL1_VDATSRCENB0 BIT(19) +#define PHY_CTRL1_VDATDETENB0 BIT(20) + +#define PHY_CTRL2 0x8 +#define PHY_CTRL2_TXENABLEN0 BIT(8) +#define PHY_CTRL2_OTG_DISABLE BIT(9) + +#define PHY_CTRL3 0xc +#define PHY_CTRL3_COMPDISTUNE_MASK GENMASK(2, 0) +#define PHY_CTRL3_TXPREEMP_TUNE_MASK GENMASK(16, 15) +#define PHY_CTRL3_TXPREEMP_TUNE_SHIFT 15 +#define PHY_CTRL3_TXRISE_TUNE_MASK GENMASK(21, 20) +#define PHY_CTRL3_TXRISE_TUNE_SHIFT 20 +/* 1111: +24% ... 0000: -6% step: 2% */ +#define PHY_CTRL3_TXVREF_TUNE_MASK GENMASK(25, 22) +#define PHY_CTRL3_TXVREF_TUNE_SHIFT 22 +#define PHY_CTRL3_TX_VBOOST_LEVEL_MASK GENMASK(31, 29) +#define PHY_CTRL3_TX_VBOOST_LEVEL_SHIFT 29 + +#define PHY_CTRL4 0x10 +#define PHY_CTRL4_PCS_TX_DEEMPH_3P5DB_MASK GENMASK(20, 15) +#define PHY_CTRL4_PCS_TX_DEEMPH_3P5DB_SHIFT 15 + +#define PHY_CTRL5 0x14 +#define PHY_CTRL5_DMPWD_OVERRIDE_SEL BIT(23) +#define PHY_CTRL5_DMPWD_OVERRIDE BIT(22) +#define PHY_CTRL5_DPPWD_OVERRIDE_SEL BIT(21) +#define PHY_CTRL5_DPPWD_OVERRIDE BIT(20) +#define PHY_CTRL5_PCS_TX_SWING_FULL_MASK GENMASK(6, 0) + +#define PHY_CTRL6 0x18 +#define PHY_CTRL6_RXTERM_OVERRIDE_SEL BIT(29) +#define PHY_CTRL6_ALT_CLK_EN BIT(1) +#define PHY_CTRL6_ALT_CLK_SEL BIT(0) + +#define PHY_STS0 0x40 +#define PHY_STS0_OTGSESSVLD BIT(7) +#define PHY_STS0_CHGDET BIT(4) +#define PHY_STS0_FSVPLUS BIT(3) +#define PHY_STS0_FSVMINUS BIT(2) + +struct imx8mq_usb_phy { +#if CONFIG_IS_ENABLED(CLK) + struct clk phy_clk; +#endif + void __iomem *base; +}; + +static const struct udevice_id imx8mq_usb_phy_of_match[] = { + { + .compatible = "fsl,imx8mq-usb-phy", + }, + {}, +}; + +static int imx8mq_usb_phy_init(struct phy *usb_phy) +{ + struct udevice *dev = usb_phy->dev; + struct imx8mq_usb_phy *imx_phy = dev_get_priv(dev); + u32 value; + + value = readl(imx_phy->base + PHY_CTRL1); + value &= ~(PHY_CTRL1_VDATSRCENB0 | PHY_CTRL1_VDATDETENB0 | + PHY_CTRL1_COMMONONN); + value |= PHY_CTRL1_RESET | PHY_CTRL1_ATERESET; + writel(value, imx_phy->base + PHY_CTRL1); + + value = readl(imx_phy->base + PHY_CTRL0); + value |= PHY_CTRL0_REF_SSP_EN; + value &= ~PHY_CTRL0_SSC_RANGE_MASK; + value |= PHY_CTRL0_SSC_RANGE_4003PPM; + writel(value, imx_phy->base + PHY_CTRL0); + + value = readl(imx_phy->base + PHY_CTRL2); + value |= PHY_CTRL2_TXENABLEN0; + writel(value, imx_phy->base + PHY_CTRL2); + + value = readl(imx_phy->base + PHY_CTRL1); + value &= ~(PHY_CTRL1_RESET | PHY_CTRL1_ATERESET); + writel(value, imx_phy->base + PHY_CTRL1); + + return 0; +} + +static int imx8mq_usb_phy_power_on(struct phy *usb_phy) +{ + struct udevice *dev = usb_phy->dev; + struct imx8mq_usb_phy *imx_phy = dev_get_priv(dev); + u32 value; + +#if CONFIG_IS_ENABLED(CLK) + int ret; + ret = clk_enable(&imx_phy->phy_clk); + if (ret) { + printf("Failed to enable usb phy clock\n"); + return ret; + } +#endif + + /* Disable rx term override */ + value = readl(imx_phy->base + PHY_CTRL6); + value &= ~PHY_CTRL6_RXTERM_OVERRIDE_SEL; + writel(value, imx_phy->base + PHY_CTRL6); + + return 0; +} + +static int imx8mq_usb_phy_power_off(struct phy *usb_phy) +{ + struct udevice *dev = usb_phy->dev; + struct imx8mq_usb_phy *imx_phy = dev_get_priv(dev); + u32 value; + + /* Override rx term to be 0 */ + value = readl(imx_phy->base + PHY_CTRL6); + value |= PHY_CTRL6_RXTERM_OVERRIDE_SEL; + writel(value, imx_phy->base + PHY_CTRL6); + +#if CONFIG_IS_ENABLED(CLK) + clk_disable(&imx_phy->phy_clk); +#endif + + return 0; +} + +static int imx8mq_usb_phy_exit(struct phy *usb_phy) +{ + return imx8mq_usb_phy_power_off(usb_phy); +} + +struct phy_ops imx8mq_usb_phy_ops = { + .init = imx8mq_usb_phy_init, + .power_on = imx8mq_usb_phy_power_on, + .power_off = imx8mq_usb_phy_power_off, + .exit = imx8mq_usb_phy_exit, +}; + +int imx8mq_usb_phy_probe(struct udevice *dev) +{ + struct imx8mq_usb_phy *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + + if (!priv->base) + return -EINVAL; + +#if CONFIG_IS_ENABLED(CLK) + int ret; + + /* Assigned clock already set clock */ + ret = clk_get_by_name(dev, "phy", &priv->phy_clk); + if (ret) { + printf("Failed to get usb phy clock\n"); + return ret; + } +#endif + + return 0; +} + +U_BOOT_DRIVER(nxp_imx8mq_usb_phy) = { + .name = "nxp_imx8mq_usb_phy", + .id = UCLASS_PHY, + .of_match = imx8mq_usb_phy_of_match, + .probe = imx8mq_usb_phy_probe, + .ops = &imx8mq_usb_phy_ops, + .priv_auto = sizeof(struct imx8mq_usb_phy), +}; diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index f70851e4bc..216e72c60f 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_SANDBOX) += spi-emul-uclass.o obj-$(CONFIG_SOFT_SPI) += soft_spi.o obj-$(CONFIG_SPI_MEM) += spi-mem.o obj-$(CONFIG_TI_QSPI) += ti_qspi.o +obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o else obj-y += spi.o obj-$(CONFIG_SPI_MEM) += spi-mem-nodm.o @@ -30,7 +31,6 @@ obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o obj-$(CONFIG_FSL_ESPI) += fsl_espi.o -obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o obj-$(CONFIG_SYNQUACER_SPI) += spi-synquacer.o obj-$(CONFIG_ICH_SPI) += ich.o obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index f3dddbdbd7..a80c3e737d 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -591,8 +591,6 @@ void spi_release_bus(struct spi_slave *slave) static int mxc_spi_probe(struct udevice *bus) { struct mxc_spi_slave *mxcs = dev_get_plat(bus); - int node = dev_of_offset(bus); - const void *blob = gd->fdt_blob; int ret; int i; @@ -629,6 +627,8 @@ static int mxc_spi_probe(struct udevice *bus) mxcs->max_hz = clk_get_rate(&clk); #else + int node = dev_of_offset(bus); + const void *blob = gd->fdt_blob; mxcs->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", 20000000); #endif diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c index 6f63b11b9f..ecd35ef22a 100644 --- a/drivers/watchdog/ulp_wdog.c +++ b/drivers/watchdog/ulp_wdog.c @@ -12,9 +12,7 @@ * MX7ULP WDOG Register Map */ struct wdog_regs { - u8 cs1; - u8 cs2; - u16 reserve0; + u32 cs; u32 cnt; u32 toval; u32 win; @@ -30,10 +28,12 @@ struct wdog_regs { #define UNLOCK_WORD0 0xC520 /* 1st unlock word */ #define UNLOCK_WORD1 0xD928 /* 2nd unlock word */ -#define WDGCS1_WDGE (1<<7) -#define WDGCS1_WDGUPDATE (1<<5) +#define WDGCS_WDGE BIT(7) +#define WDGCS_WDGUPDATE BIT(5) -#define WDGCS2_FLG (1<<6) +#define WDGCS_RCS BIT(10) +#define WDGCS_ULK BIT(11) +#define WDGCS_FLG BIT(14) #define WDG_BUS_CLK (0x0) #define WDG_LPO_CLK (0x1) @@ -52,27 +52,34 @@ void hw_watchdog_reset(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; - writel(REFRESH_WORD0, &wdog->cnt); - writel(REFRESH_WORD1, &wdog->cnt); + dmb(); + __raw_writel(REFRESH_WORD0, &wdog->cnt); + __raw_writel(REFRESH_WORD1, &wdog->cnt); + dmb(); } void hw_watchdog_init(void) { - u8 val; struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; - writel(UNLOCK_WORD0, &wdog->cnt); - writel(UNLOCK_WORD1, &wdog->cnt); + dmb(); + __raw_writel(UNLOCK_WORD0, &wdog->cnt); + __raw_writel(UNLOCK_WORD1, &wdog->cnt); + dmb(); - val = readb(&wdog->cs2); - val |= WDGCS2_FLG; - writeb(val, &wdog->cs2); + /* Wait WDOG Unlock */ + while (!(readl(&wdog->cs) & WDGCS_ULK)) + ; hw_watchdog_set_timeout(CONFIG_WATCHDOG_TIMEOUT_MSECS); writel(0, &wdog->win); - writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */ - writeb((WDGCS1_WDGE | WDGCS1_WDGUPDATE), &wdog->cs1);/* enable counter running */ + /* setting 1-kHz clock source, enable counter running, and clear interrupt */ + writel((WDGCS_WDGE | WDGCS_WDGUPDATE |(WDG_LPO_CLK << 8) | WDGCS_FLG), &wdog->cs); + + /* Wait WDOG reconfiguration */ + while (!(readl(&wdog->cs) & WDGCS_RCS)) + ; hw_watchdog_reset(); } @@ -81,14 +88,24 @@ void reset_cpu(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; - writel(UNLOCK_WORD0, &wdog->cnt); - writel(UNLOCK_WORD1, &wdog->cnt); + dmb(); + __raw_writel(UNLOCK_WORD0, &wdog->cnt); + __raw_writel(UNLOCK_WORD1, &wdog->cnt); + dmb(); + + /* Wait WDOG Unlock */ + while (!(readl(&wdog->cs) & WDGCS_ULK)) + ; hw_watchdog_set_timeout(5); /* 5ms timeout */ writel(0, &wdog->win); - writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */ - writeb(WDGCS1_WDGE, &wdog->cs1);/* enable counter running */ + /* enable counter running */ + writel((WDGCS_WDGE | (WDG_LPO_CLK << 8)), &wdog->cs); + + /* Wait WDOG reconfiguration */ + while (!(readl(&wdog->cs) & WDGCS_RCS)) + ; hw_watchdog_reset(); |