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-rw-r--r--drivers/video/Kconfig14
-rw-r--r--drivers/video/Makefile2
-rw-r--r--drivers/video/hx8238d.c197
-rw-r--r--drivers/video/mb862xx.c486
-rw-r--r--drivers/video/nexell_display.c2
-rw-r--r--drivers/video/simple_panel.c2
6 files changed, 213 insertions, 490 deletions
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index d782eb806a..667157c2e9 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -30,7 +30,7 @@ config VIDEO_PCI_DEFAULT_FB_SIZE
help
Generally, video drivers request the amount of memory they need for
the frame buffer when they are bound, by setting the size field in
- struct video_uc_platdata. That memory is then reserved for use after
+ struct video_uc_plat. That memory is then reserved for use after
relocation. But PCI drivers cannot be bound before relocation unless
they are mentioned in the devicetree.
@@ -51,7 +51,7 @@ config VIDEO_COPY
U-Boot) and then copied to the hardware frame-buffer as needed.
To use this, your video driver must set @copy_base in
- struct video_uc_platdata.
+ struct video_uc_plat.
config BACKLIGHT_PWM
bool "Generic PWM based Backlight Driver"
@@ -160,6 +160,16 @@ config CONSOLE_TRUETYPE
With this option you can adjust the text size and use a variety of
fonts. Note that this is noticeably slower than with normal console.
+config DM_PANEL_HX8238D
+ bool "Enable Himax HX-8238D LCD driver"
+ depends on DM_VIDEO
+ help
+ Support for HX-8238D LCD Panel
+ The HX8238-D is a single chip controller and driver LSI that
+ integrates the power circuit.
+ It can drive a maximum 960x240 dot graphics on a-TFT panel
+ displays in 16M colors with dithering.
+
config CONSOLE_TRUETYPE_SIZE
int "TrueType font size"
depends on CONSOLE_TRUETYPE
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 494e414a31..933f06e9d8 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_VIDEO_MIPI_DSI) += dsi-host-uclass.o
obj-$(CONFIG_DM_VIDEO) += video-uclass.o vidconsole-uclass.o
obj-$(CONFIG_DM_VIDEO) += video_bmp.o
obj-$(CONFIG_PANEL) += panel-uclass.o
+obj-$(CONFIG_PANEL_HX8238D) += hx8238d.o
obj-$(CONFIG_SIMPLE_PANEL) += simple_panel.o
endif
@@ -57,7 +58,6 @@ obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o
obj-$(CONFIG_VIDEO_LCD_RAYDIUM_RM68200) += raydium-rm68200.o
obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
obj-$(CONFIG_VIDEO_LCD_TDO_TL070WSH30) += tdo-tl070wsh30.o
-obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
obj-${CONFIG_VIDEO_MESON} += meson/
obj-${CONFIG_VIDEO_MIPI_DSI} += mipi_dsi.o
obj-$(CONFIG_VIDEO_MVEBU) += mvebu_lcd.o
diff --git a/drivers/video/hx8238d.c b/drivers/video/hx8238d.c
new file mode 100644
index 0000000000..f7e7753a53
--- /dev/null
+++ b/drivers/video/hx8238d.c
@@ -0,0 +1,197 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copied from simple-panel
+ * Copyright (c) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ * Copyright (c) 2018 Sjoerd Simons <sjoerd.simons@collabora.co.uk>
+ * Modified by Moses Christopher <BollavarapuMoses.Christopher@in.bosch.com>
+ *
+ * Panel Initialization for HX8238D panel from Himax
+ * Resolution: 320x240
+ * Color-Mode: RGB
+ *
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <panel.h>
+#include <spi.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Register Address */
+#define HX8238D_OUTPUT_CTRL_ADDR 0x01
+#define HX8238D_LCD_AC_CTRL_ADDR 0x02
+#define HX8238D_POWER_CTRL_1_ADDR 0x03
+#define HX8238D_DATA_CLR_CTRL_ADDR 0X04
+#define HX8238D_FUNCTION_CTRL_ADDR 0x05
+#define HX8238D_LED_CTRL_ADDR 0x08
+#define HX8238D_CONT_BRIGHT_CTRL_ADDR 0x0A
+#define HX8238D_FRAME_CYCLE_CTRL_ADDR 0x0B
+#define HX8238D_POWER_CTRL_2_ADDR 0x0D
+#define HX8238D_POWER_CTRL_3_ADDR 0x0E
+#define HX8238D_GATE_SCAN_POS_ADDR 0x0F
+#define HX8238D_HORIZONTAL_PORCH_ADDR 0x16
+#define HX8238D_VERTICAL_PORCH_ADDR 0x17
+#define HX8238D_POWER_CTRL_4_ADDR 0x1E
+#define HX8238D_GAMMA_CTRL_1_ADDR 0x30
+#define HX8238D_GAMMA_CTRL_2_ADDR 0x31
+#define HX8238D_GAMMA_CTRL_3_ADDR 0x32
+#define HX8238D_GAMMA_CTRL_4_ADDR 0x33
+#define HX8238D_GAMMA_CTRL_5_ADDR 0x34
+#define HX8238D_GAMMA_CTRL_6_ADDR 0x35
+#define HX8238D_GAMMA_CTRL_7_ADDR 0x36
+#define HX8238D_GAMMA_CTRL_8_ADDR 0x37
+#define HX8238D_GAMMA_CTRL_9_ADDR 0x3A
+#define HX8238D_GAMMA_CTRL_10_ADDR 0x3B
+
+/* Register Data */
+#define HX8238D_OUTPUT_CTRL 0x6300
+#define HX8238D_LCD_AC_CTRL 0x0200
+#define HX8238D_POWER_CTRL_1 0x6564
+#define HX8238D_DATA_CLR_CTRL 0x04C7
+#define HX8238D_FUNCTION_CTRL 0xA884
+#define HX8238D_LED_CTRL 0x00CE
+#define HX8238D_CONT_BRIGHT_CTRL 0x4008
+#define HX8238D_FRAME_CYCLE_CTRL 0xD400
+#define HX8238D_POWER_CTRL_2 0x3229
+#define HX8238D_POWER_CTRL_3 0x1200
+#define HX8238D_GATE_SCAN_POS 0x0000
+#define HX8238D_HORIZONTAL_PORCH 0x9F80
+#define HX8238D_VERTICAL_PORCH 0x3F02
+#define HX8238D_POWER_CTRL_4 0x005C
+
+/* Gamma Control */
+#define HX8238D_GAMMA_CTRL_1 0x0103
+#define HX8238D_GAMMA_CTRL_2 0x0407
+#define HX8238D_GAMMA_CTRL_3 0x0705
+#define HX8238D_GAMMA_CTRL_4 0x0002
+#define HX8238D_GAMMA_CTRL_5 0x0505
+#define HX8238D_GAMMA_CTRL_6 0x0303
+#define HX8238D_GAMMA_CTRL_7 0x0707
+#define HX8238D_GAMMA_CTRL_8 0x0100
+#define HX8238D_GAMMA_CTRL_9 0x1F00
+#define HX8238D_GAMMA_CTRL_10 0x000F
+
+/* Primary SPI register identification, 011100 */
+/* Select register, RS=0, RS=0 */
+/* Write register, RS=1, RW=0 */
+#define HX8238D_PRIMARY_SELECT_REG 0x70
+#define HX8238D_PRIMARY_WRITE_REG (HX8238D_PRIMARY_SELECT_REG | (0x1 << 1))
+
+#define HX8238D_REG_BIT_LEN 24
+
+struct hx8238d_priv {
+ struct spi_slave *spi;
+};
+
+static int hx8238d_ofdata_to_platdata(struct udevice *dev)
+{
+ struct hx8238d_priv *priv = dev_get_priv(dev);
+
+ priv->spi = dev_get_parent_priv(dev);
+
+ return 0;
+}
+
+/* data[0] => REGISTER ADDRESS */
+/* data[1] => REGISTER VALUE */
+struct hx8238d_command {
+ u16 data[2];
+};
+
+static struct hx8238d_command hx8238d_init_commands[] = {
+ { .data = { HX8238D_OUTPUT_CTRL_ADDR, HX8238D_OUTPUT_CTRL } },
+ { .data = { HX8238D_LCD_AC_CTRL_ADDR, HX8238D_LCD_AC_CTRL } },
+ { .data = { HX8238D_POWER_CTRL_1_ADDR, HX8238D_POWER_CTRL_1 } },
+ { .data = { HX8238D_DATA_CLR_CTRL_ADDR, HX8238D_DATA_CLR_CTRL } },
+ { .data = { HX8238D_FUNCTION_CTRL_ADDR, HX8238D_FUNCTION_CTRL } },
+ { .data = { HX8238D_LED_CTRL_ADDR, HX8238D_LED_CTRL } },
+ { .data = { HX8238D_CONT_BRIGHT_CTRL_ADDR, HX8238D_CONT_BRIGHT_CTRL } },
+ { .data = { HX8238D_FRAME_CYCLE_CTRL_ADDR, HX8238D_FRAME_CYCLE_CTRL } },
+ { .data = { HX8238D_POWER_CTRL_2_ADDR, HX8238D_POWER_CTRL_2 } },
+ { .data = { HX8238D_POWER_CTRL_3_ADDR, HX8238D_POWER_CTRL_3 } },
+ { .data = { HX8238D_GATE_SCAN_POS_ADDR, HX8238D_GATE_SCAN_POS } },
+ { .data = { HX8238D_HORIZONTAL_PORCH_ADDR, HX8238D_HORIZONTAL_PORCH } },
+ { .data = { HX8238D_VERTICAL_PORCH_ADDR, HX8238D_VERTICAL_PORCH } },
+ { .data = { HX8238D_POWER_CTRL_4_ADDR, HX8238D_POWER_CTRL_4 } },
+ { .data = { HX8238D_GAMMA_CTRL_1_ADDR, HX8238D_GAMMA_CTRL_1 } },
+ { .data = { HX8238D_GAMMA_CTRL_2_ADDR, HX8238D_GAMMA_CTRL_2 } },
+ { .data = { HX8238D_GAMMA_CTRL_3_ADDR, HX8238D_GAMMA_CTRL_3 } },
+ { .data = { HX8238D_GAMMA_CTRL_4_ADDR, HX8238D_GAMMA_CTRL_4 } },
+ { .data = { HX8238D_GAMMA_CTRL_5_ADDR, HX8238D_GAMMA_CTRL_5 } },
+ { .data = { HX8238D_GAMMA_CTRL_6_ADDR, HX8238D_GAMMA_CTRL_6 } },
+ { .data = { HX8238D_GAMMA_CTRL_7_ADDR, HX8238D_GAMMA_CTRL_7 } },
+ { .data = { HX8238D_GAMMA_CTRL_8_ADDR, HX8238D_GAMMA_CTRL_8 } },
+ { .data = { HX8238D_GAMMA_CTRL_9_ADDR, HX8238D_GAMMA_CTRL_9 } },
+ { .data = { HX8238D_GAMMA_CTRL_10_ADDR, HX8238D_GAMMA_CTRL_10 } },
+};
+
+/*
+ * Generate Primary Register Buffer for Register Select and Register Write
+ * First 6 MSB bits of Primary Register is represented with 011100
+ *
+ */
+static void hx8238d_generate_reg_buffers(struct hx8238d_command command,
+ u8 *sr_buf, uint8_t *wr_buf)
+{
+ struct hx8238d_command cmd = command;
+
+ sr_buf[0] = HX8238D_PRIMARY_SELECT_REG;
+ sr_buf[1] = (cmd.data[0] >> 8) & 0xff;
+ sr_buf[2] = (cmd.data[0]) & 0xff;
+
+ wr_buf[0] = HX8238D_PRIMARY_WRITE_REG;
+ wr_buf[1] = (cmd.data[1] >> 8) & 0xff;
+ wr_buf[2] = (cmd.data[1]) & 0xff;
+}
+
+static int hx8238d_probe(struct udevice *dev)
+{
+ struct hx8238d_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = spi_claim_bus(priv->spi);
+ if (ret) {
+ debug("Failed to claim bus: %d\n", ret);
+ return ret;
+ }
+
+ for (int i = 0; i < ARRAY_SIZE(hx8238d_init_commands); i++) {
+ u8 sr_buf[3], wr_buf[3];
+ const struct hx8238d_command cmd = hx8238d_init_commands[i];
+
+ hx8238d_generate_reg_buffers(cmd, sr_buf, wr_buf);
+ ret = spi_xfer(priv->spi, HX8238D_REG_BIT_LEN, sr_buf, NULL,
+ SPI_XFER_BEGIN | SPI_XFER_END);
+ if (ret) {
+ debug("Failed to select register %d\n", ret);
+ goto free;
+ }
+
+ ret = spi_xfer(priv->spi, HX8238D_REG_BIT_LEN, wr_buf, NULL,
+ SPI_XFER_BEGIN | SPI_XFER_END);
+ if (ret) {
+ debug("Failed to write value %d\n", ret);
+ goto free;
+ }
+ }
+
+free:
+ spi_release_bus(priv->spi);
+ return ret;
+}
+
+static const struct udevice_id hx8238d_ids[] = {
+ { .compatible = "himax,hx8238d" },
+ { }
+};
+
+U_BOOT_DRIVER(hx8238d) = {
+ .name = "hx8238d",
+ .id = UCLASS_PANEL,
+ .of_match = hx8238d_ids,
+ .ofdata_to_platdata = hx8238d_ofdata_to_platdata,
+ .probe = hx8238d_probe,
+ .priv_auto_alloc_size = sizeof(struct hx8238d_priv),
+};
diff --git a/drivers/video/mb862xx.c b/drivers/video/mb862xx.c
deleted file mode 100644
index 04e435f913..0000000000
--- a/drivers/video/mb862xx.c
+++ /dev/null
@@ -1,486 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2007
- * DENX Software Engineering, Anatolij Gustschin, agust@denx.de
- */
-
-/*
- * mb862xx.c - Graphic interface for Fujitsu CoralP/Lime
- * PCI and video mode code was derived from smiLynxEM driver.
- */
-
-#include <common.h>
-#include <linux/delay.h>
-
-#include <asm/io.h>
-#include <env.h>
-#include <pci.h>
-#include <video_fb.h>
-#include "videomodes.h"
-#include <mb862xx.h>
-
-#if defined(CONFIG_POST)
-#include <post.h>
-#endif
-
-/*
- * Graphic Device
- */
-GraphicDevice mb862xx;
-
-/*
- * 32MB external RAM - 256K Chip MMIO = 0x1FC0000 ;
- */
-#define VIDEO_MEM_SIZE 0x01FC0000
-
-#if defined(CONFIG_PCI)
-#if defined(CONFIG_VIDEO_CORALP)
-
-static struct pci_device_id supported[] = {
- { PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_P },
- { PCI_VENDOR_ID_FUJITSU, PCI_DEVICE_ID_CORAL_PA },
- { }
-};
-
-/* Internal clock frequency divider table, index is mode number */
-unsigned int fr_div[] = { 0x00000f00, 0x00000900, 0x00000500 };
-#endif
-#endif
-
-#if defined(CONFIG_VIDEO_CORALP)
-#define rd_io in32r
-#define wr_io out32r
-#else
-#define rd_io(addr) in_be32((volatile unsigned *)(addr))
-#define wr_io(addr, val) out_be32((volatile unsigned *)(addr), (val))
-#endif
-
-#define HOST_RD_REG(off) rd_io((dev->frameAdrs + GC_HOST_BASE + (off)))
-#define HOST_WR_REG(off, val) wr_io((dev->frameAdrs + GC_HOST_BASE + (off)), \
- (val))
-#define DISP_RD_REG(off) rd_io((dev->frameAdrs + GC_DISP_BASE + (off)))
-#define DISP_WR_REG(off, val) wr_io((dev->frameAdrs + GC_DISP_BASE + (off)), \
- (val))
-#define DE_RD_REG(off) rd_io((dev->dprBase + (off)))
-#define DE_WR_REG(off, val) wr_io((dev->dprBase + (off)), (val))
-
-#if defined(CONFIG_VIDEO_CORALP)
-#define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_GEO_FIFO)), (val))
-#else
-#define DE_WR_FIFO(val) wr_io((dev->dprBase + (GC_FIFO)), (val))
-#endif
-
-#define L0PAL_WR_REG(idx, val) wr_io((dev->frameAdrs + \
- (GC_DISP_BASE | GC_L0PAL0) + \
- ((idx) << 2)), (val))
-
-#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
-static void gdc_sw_reset (void)
-{
- GraphicDevice *dev = &mb862xx;
-
- HOST_WR_REG (GC_SRST, 0x1);
- udelay(500);
- video_hw_init ();
-}
-
-
-static void de_wait (void)
-{
- GraphicDevice *dev = &mb862xx;
- int lc = 0x10000;
-
- /*
- * Sync with software writes to framebuffer,
- * try to reset if engine locked
- */
- while (DE_RD_REG (GC_CTR) & 0x00000131)
- if (lc-- < 0) {
- gdc_sw_reset ();
- puts ("gdc reset done after drawing engine lock.\n");
- break;
- }
-}
-
-static void de_wait_slots (int slots)
-{
- GraphicDevice *dev = &mb862xx;
- int lc = 0x10000;
-
- /* Wait for free fifo slots */
- while (DE_RD_REG (GC_IFCNT) < slots)
- if (lc-- < 0) {
- gdc_sw_reset ();
- puts ("gdc reset done after drawing engine lock.\n");
- break;
- }
-}
-#endif
-
-#if !defined(CONFIG_VIDEO_CORALP)
-static void board_disp_init (void)
-{
- GraphicDevice *dev = &mb862xx;
- const gdc_regs *regs = board_get_regs ();
-
- while (regs->index) {
- DISP_WR_REG (regs->index, regs->value);
- regs++;
- }
-}
-#endif
-
-/*
- * Init drawing engine if accel enabled.
- * Also clears visible framebuffer.
- */
-static void de_init (void)
-{
- GraphicDevice *dev = &mb862xx;
-#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
- int cf = (dev->gdfBytesPP == 1) ? 0x0000 : 0x8000;
-
- dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
-
- /* Setup mode and fbbase, xres, fg, bg */
- de_wait_slots (2);
- DE_WR_FIFO (0xf1010108);
- DE_WR_FIFO (cf | 0x0300);
- DE_WR_REG (GC_FBR, 0x0);
- DE_WR_REG (GC_XRES, dev->winSizeX);
- DE_WR_REG (GC_FC, 0x0);
- DE_WR_REG (GC_BC, 0x0);
- /* Reset clipping */
- DE_WR_REG (GC_CXMIN, 0x0);
- DE_WR_REG (GC_CXMAX, dev->winSizeX);
- DE_WR_REG (GC_CYMIN, 0x0);
- DE_WR_REG (GC_CYMAX, dev->winSizeY);
-
- /* Clear framebuffer using drawing engine */
- de_wait_slots (3);
- DE_WR_FIFO (0x09410000);
- DE_WR_FIFO (0x00000000);
- DE_WR_FIFO (dev->winSizeY << 16 | dev->winSizeX);
- /* sync with SW access to framebuffer */
- de_wait ();
-#else
- unsigned int i, *p;
-
- i = dev->winSizeX * dev->winSizeY;
- p = (unsigned int *)dev->frameAdrs;
- while (i--)
- *p++ = 0;
-#endif
-}
-
-#if defined(CONFIG_VIDEO_CORALP)
-/* use CCF and MMR parameters for Coral-P Eval. Board as default */
-#ifndef CONFIG_SYS_MB862xx_CCF
-#define CONFIG_SYS_MB862xx_CCF 0x00090000
-#endif
-#ifndef CONFIG_SYS_MB862xx_MMR
-#define CONFIG_SYS_MB862xx_MMR 0x11d7fa13
-#endif
-
-unsigned int pci_video_init (void)
-{
- GraphicDevice *dev = &mb862xx;
- pci_dev_t devbusfn;
- u16 device;
-
- if ((devbusfn = pci_find_devices (supported, 0)) < 0) {
- puts("controller not present\n");
- return 0;
- }
-
- /* PCI setup */
- pci_write_config_dword (devbusfn, PCI_COMMAND,
- (PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
- pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &dev->frameAdrs);
- dev->frameAdrs = pci_mem_to_phys (devbusfn, dev->frameAdrs);
-
- if (dev->frameAdrs == 0) {
- puts ("PCI config: failed to get base address\n");
- return 0;
- }
-
- dev->pciBase = dev->frameAdrs;
-
- puts("Coral-");
-
- pci_read_config_word(devbusfn, PCI_DEVICE_ID, &device);
- switch (device) {
- case PCI_DEVICE_ID_CORAL_P:
- puts("P\n");
- break;
- case PCI_DEVICE_ID_CORAL_PA:
- puts("PA\n");
- break;
- default:
- puts("Unknown\n");
- return 0;
- }
-
- /* Setup clocks and memory mode for Coral-P(A) */
- HOST_WR_REG(GC_CCF, CONFIG_SYS_MB862xx_CCF);
- udelay(200);
- HOST_WR_REG(GC_MMR, CONFIG_SYS_MB862xx_MMR);
- udelay(100);
- return dev->frameAdrs;
-}
-
-unsigned int card_init (void)
-{
- GraphicDevice *dev = &mb862xx;
- unsigned int cf, videomode, div = 0;
- unsigned long t1, hsync, vsync;
- char *penv;
- int tmp, i, bpp;
- struct ctfb_res_modes *res_mode;
- struct ctfb_res_modes var_mode;
-
- memset (dev, 0, sizeof (GraphicDevice));
-
- if (!pci_video_init ())
- return 0;
-
- tmp = 0;
- videomode = 0x310;
- /* get video mode via environment */
- penv = env_get("videomode");
- if (penv) {
- /* decide if it is a string */
- if (penv[0] <= '9') {
- videomode = (int) simple_strtoul (penv, NULL, 16);
- tmp = 1;
- }
- } else {
- tmp = 1;
- }
-
- if (tmp) {
- /* parameter are vesa modes, search params */
- for (i = 0; i < VESA_MODES_COUNT; i++) {
- if (vesa_modes[i].vesanr == videomode)
- break;
- }
- if (i == VESA_MODES_COUNT) {
- printf ("\tno VESA Mode found, fallback to mode 0x%x\n",
- videomode);
- i = 0;
- }
- res_mode = (struct ctfb_res_modes *)
- &res_mode_init[vesa_modes[i].resindex];
- if (vesa_modes[i].resindex > 2) {
- puts ("\tUnsupported resolution, using default\n");
- bpp = vesa_modes[1].bits_per_pixel;
- div = fr_div[1];
- }
- bpp = vesa_modes[i].bits_per_pixel;
- div = fr_div[vesa_modes[i].resindex];
- } else {
- res_mode = (struct ctfb_res_modes *) &var_mode;
- bpp = video_get_params (res_mode, penv);
- }
-
- /* calculate hsync and vsync freq (info only) */
- t1 = (res_mode->left_margin + res_mode->xres +
- res_mode->right_margin + res_mode->hsync_len) / 8;
- t1 *= 8;
- t1 *= res_mode->pixclock;
- t1 /= 1000;
- hsync = 1000000000L / t1;
- t1 *= (res_mode->upper_margin + res_mode->yres +
- res_mode->lower_margin + res_mode->vsync_len);
- t1 /= 1000;
- vsync = 1000000000L / t1;
-
- /* fill in Graphic device struct */
- sprintf (dev->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,
- res_mode->yres, bpp, (hsync / 1000), (vsync / 1000));
- printf ("\t%s\n", dev->modeIdent);
- dev->winSizeX = res_mode->xres;
- dev->winSizeY = res_mode->yres;
- dev->memSize = VIDEO_MEM_SIZE;
-
- switch (bpp) {
- case 8:
- dev->gdfIndex = GDF__8BIT_INDEX;
- dev->gdfBytesPP = 1;
- break;
- case 15:
- case 16:
- dev->gdfIndex = GDF_15BIT_555RGB;
- dev->gdfBytesPP = 2;
- break;
- default:
- printf ("\t%d bpp configured, but only 8,15 and 16 supported\n",
- bpp);
- puts ("\tfallback to 15bpp\n");
- dev->gdfIndex = GDF_15BIT_555RGB;
- dev->gdfBytesPP = 2;
- }
-
- /* Setup dot clock (internal pll, division rate) */
- DISP_WR_REG (GC_DCM1, div);
- /* L0 init */
- cf = (dev->gdfBytesPP == 1) ? 0x00000000 : 0x80000000;
- DISP_WR_REG (GC_L0M, ((dev->winSizeX * dev->gdfBytesPP) / 64) << 16 |
- (dev->winSizeY - 1) | cf);
- DISP_WR_REG (GC_L0OA0, 0x0);
- DISP_WR_REG (GC_L0DA0, 0x0);
- DISP_WR_REG (GC_L0DY_L0DX, 0x0);
- DISP_WR_REG (GC_L0EM, 0x0);
- DISP_WR_REG (GC_L0WY_L0WX, 0x0);
- DISP_WR_REG (GC_L0WH_L0WW, (dev->winSizeY - 1) << 16 | dev->winSizeX);
-
- /* Display timing init */
- DISP_WR_REG (GC_HTP_A, (dev->winSizeX +
- res_mode->left_margin +
- res_mode->right_margin +
- res_mode->hsync_len - 1) << 16);
- DISP_WR_REG (GC_HDB_HDP_A, (dev->winSizeX - 1) << 16 |
- (dev->winSizeX - 1));
- DISP_WR_REG (GC_VSW_HSW_HSP_A, (res_mode->vsync_len - 1) << 24 |
- (res_mode->hsync_len - 1) << 16 |
- (dev->winSizeX +
- res_mode->right_margin - 1));
- DISP_WR_REG (GC_VTR_A, (dev->winSizeY + res_mode->lower_margin +
- res_mode->upper_margin +
- res_mode->vsync_len - 1) << 16);
- DISP_WR_REG (GC_VDP_VSP_A, (dev->winSizeY-1) << 16 |
- (dev->winSizeY +
- res_mode->lower_margin - 1));
- DISP_WR_REG (GC_WY_WX, 0x0);
- DISP_WR_REG (GC_WH_WW, dev->winSizeY << 16 | dev->winSizeX);
- /* Display enable, L0 layer */
- DISP_WR_REG (GC_DCM1, 0x80010000 | div);
-
- return dev->frameAdrs;
-}
-#endif
-
-
-#if !defined(CONFIG_VIDEO_CORALP)
-int mb862xx_probe(unsigned int addr)
-{
- GraphicDevice *dev = &mb862xx;
- unsigned int reg;
-
- dev->frameAdrs = addr;
- dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
-
- /* Try to access GDC ID/Revision registers */
- reg = HOST_RD_REG (GC_CID);
- reg = HOST_RD_REG (GC_CID);
- if (reg == 0x303) {
- reg = DE_RD_REG(GC_REV);
- reg = DE_RD_REG(GC_REV);
- if ((reg & ~0xff) == 0x20050100)
- return MB862XX_TYPE_LIME;
- }
-
- return 0;
-}
-#endif
-
-void *video_hw_init (void)
-{
- GraphicDevice *dev = &mb862xx;
-
- puts ("Video: Fujitsu ");
-
- memset (dev, 0, sizeof (GraphicDevice));
-
-#if defined(CONFIG_VIDEO_CORALP)
- if (card_init () == 0)
- return NULL;
-#else
- /*
- * Preliminary init of the onboard graphic controller,
- * retrieve base address
- */
- if ((dev->frameAdrs = board_video_init ()) == 0) {
- puts ("Controller not found!\n");
- return NULL;
- } else {
- puts ("Lime\n");
-
- /* Set Change of Clock Frequency Register */
- HOST_WR_REG (GC_CCF, CONFIG_SYS_MB862xx_CCF);
- /* Delay required */
- udelay(300);
- /* Set Memory I/F Mode Register) */
- HOST_WR_REG (GC_MMR, CONFIG_SYS_MB862xx_MMR);
- }
-#endif
-
- de_init ();
-
-#if !defined(CONFIG_VIDEO_CORALP)
- board_disp_init ();
-#endif
-
-#if (defined(CONFIG_LWMON5) || \
- defined(CONFIG_SOCRATES)) && !(CONFIG_POST & CONFIG_SYS_POST_SYSMON)
- /* Lamp on */
- board_backlight_switch (1);
-#endif
-
- return dev;
-}
-
-/*
- * Set a RGB color in the LUT
- */
-void video_set_lut (unsigned int index, unsigned char r,
- unsigned char g, unsigned char b)
-{
- GraphicDevice *dev = &mb862xx;
-
- L0PAL_WR_REG (index, (r << 16) | (g << 8) | (b));
-}
-
-#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
-/*
- * Drawing engine Fill and BitBlt screen region
- */
-void video_hw_rectfill (unsigned int bpp, unsigned int dst_x,
- unsigned int dst_y, unsigned int dim_x,
- unsigned int dim_y, unsigned int color)
-{
- GraphicDevice *dev = &mb862xx;
-
- de_wait_slots (3);
- DE_WR_REG (GC_FC, color);
- DE_WR_FIFO (0x09410000);
- DE_WR_FIFO ((dst_y << 16) | dst_x);
- DE_WR_FIFO ((dim_y << 16) | dim_x);
- de_wait ();
-}
-
-void video_hw_bitblt (unsigned int bpp, unsigned int src_x,
- unsigned int src_y, unsigned int dst_x,
- unsigned int dst_y, unsigned int width,
- unsigned int height)
-{
- GraphicDevice *dev = &mb862xx;
- unsigned int ctrl = 0x0d000000L;
-
- if (src_x >= dst_x && src_y >= dst_y)
- ctrl |= 0x00440000L;
- else if (src_x >= dst_x && src_y <= dst_y)
- ctrl |= 0x00460000L;
- else if (src_x <= dst_x && src_y >= dst_y)
- ctrl |= 0x00450000L;
- else
- ctrl |= 0x00470000L;
-
- de_wait_slots (4);
- DE_WR_FIFO (ctrl);
- DE_WR_FIFO ((src_y << 16) | src_x);
- DE_WR_FIFO ((dst_y << 16) | dst_x);
- DE_WR_FIFO ((height << 16) | width);
- de_wait (); /* sync */
-}
-#endif
diff --git a/drivers/video/nexell_display.c b/drivers/video/nexell_display.c
index b47bef3578..c7621ef49c 100644
--- a/drivers/video/nexell_display.c
+++ b/drivers/video/nexell_display.c
@@ -15,7 +15,7 @@
#include <malloc.h>
#include <linux/compat.h>
#include <linux/err.h>
-#include <video.h> /* For struct video_uc_platdata */
+#include <video.h> /* For struct video_uc_plat */
#include <video_fb.h>
#include <lcd.h>
#include <asm/global_data.h>
diff --git a/drivers/video/simple_panel.c b/drivers/video/simple_panel.c
index 59e17f8f10..c8f7022ea6 100644
--- a/drivers/video/simple_panel.c
+++ b/drivers/video/simple_panel.c
@@ -108,6 +108,8 @@ static const struct udevice_id simple_panel_ids[] = {
{ .compatible = "auo,b133htn01" },
{ .compatible = "boe,nv140fhmn49" },
{ .compatible = "lg,lb070wv8" },
+ { .compatible = "sharp,lq123p1jx31" },
+ { .compatible = "boe,nv101wxmn51" },
{ }
};
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-23 23:26:50 +0000