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path: root/drivers/usb/dwc3/dwc3-generic.c
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Diffstat (limited to 'drivers/usb/dwc3/dwc3-generic.c')
-rw-r--r--drivers/usb/dwc3/dwc3-generic.c62
1 files changed, 57 insertions, 5 deletions
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 01bd0ca190..6cf844cb48 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -219,11 +219,62 @@ U_BOOT_DRIVER(dwc3_generic_host) = {
#endif
struct dwc3_glue_ops {
- void (*select_dr_mode)(struct udevice *dev, int index,
+ void (*glue_configure)(struct udevice *dev, int index,
enum usb_dr_mode mode);
};
-void dwc3_ti_select_dr_mode(struct udevice *dev, int index,
+void dwc3_imx8mp_glue_configure(struct udevice *dev, int index,
+ enum usb_dr_mode mode)
+{
+/* USB glue registers */
+#define USB_CTRL0 0x00
+#define USB_CTRL1 0x04
+
+#define USB_CTRL0_PORTPWR_EN BIT(12) /* 1 - PPC enabled (default) */
+#define USB_CTRL0_USB3_FIXED BIT(22) /* 1 - USB3 permanent attached */
+#define USB_CTRL0_USB2_FIXED BIT(23) /* 1 - USB2 permanent attached */
+
+#define USB_CTRL1_OC_POLARITY BIT(16) /* 0 - HIGH / 1 - LOW */
+#define USB_CTRL1_PWR_POLARITY BIT(17) /* 0 - HIGH / 1 - LOW */
+ fdt_addr_t regs = dev_read_addr_index(dev, 1);
+ void *base = map_physmem(regs, 0x8, MAP_NOCACHE);
+ u32 value;
+
+ value = readl(base + USB_CTRL0);
+
+ if (dev_read_bool(dev, "fsl,permanently-attached"))
+ value |= (USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
+ else
+ value &= ~(USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED);
+
+ if (dev_read_bool(dev, "fsl,disable-port-power-control"))
+ value &= ~(USB_CTRL0_PORTPWR_EN);
+ else
+ value |= USB_CTRL0_PORTPWR_EN;
+
+ writel(value, base + USB_CTRL0);
+
+ value = readl(base + USB_CTRL1);
+ if (dev_read_bool(dev, "fsl,over-current-active-low"))
+ value |= USB_CTRL1_OC_POLARITY;
+ else
+ value &= ~USB_CTRL1_OC_POLARITY;
+
+ if (dev_read_bool(dev, "fsl,power-active-low"))
+ value |= USB_CTRL1_PWR_POLARITY;
+ else
+ value &= ~USB_CTRL1_PWR_POLARITY;
+
+ writel(value, base + USB_CTRL1);
+
+ unmap_physmem(base, MAP_NOCACHE);
+}
+
+struct dwc3_glue_ops imx8mp_ops = {
+ .glue_configure = dwc3_imx8mp_glue_configure,
+};
+
+void dwc3_ti_glue_configure(struct udevice *dev, int index,
enum usb_dr_mode mode)
{
#define USBOTGSS_UTMI_OTG_STATUS 0x0084
@@ -304,7 +355,7 @@ enum dwc3_omap_utmi_mode {
}
struct dwc3_glue_ops ti_ops = {
- .select_dr_mode = dwc3_ti_select_dr_mode,
+ .glue_configure = dwc3_ti_glue_configure,
};
static int dwc3_glue_bind(struct udevice *parent)
@@ -435,8 +486,8 @@ static int dwc3_glue_probe(struct udevice *dev)
dr_mode = usb_get_dr_mode(dev_ofnode(child));
device_find_next_child(&child);
- if (ops && ops->select_dr_mode)
- ops->select_dr_mode(dev, index, dr_mode);
+ if (ops && ops->glue_configure)
+ ops->glue_configure(dev, index, dr_mode);
index++;
}
@@ -464,6 +515,7 @@ static const struct udevice_id dwc3_glue_ids[] = {
{ .compatible = "rockchip,rk3328-dwc3" },
{ .compatible = "rockchip,rk3399-dwc3" },
{ .compatible = "qcom,dwc3" },
+ { .compatible = "fsl,imx8mp-dwc3", .data = (ulong)&imx8mp_ops },
{ .compatible = "fsl,imx8mq-dwc3" },
{ .compatible = "intel,tangier-dwc3" },
{ }