diff options
Diffstat (limited to 'drivers/net')
| -rw-r--r-- | drivers/net/fsl-mc/Kconfig | 4 | ||||
| -rw-r--r-- | drivers/net/ldpaa_eth/Makefile | 1 | ||||
| -rw-r--r-- | drivers/net/pfe_eth/pfe_firmware.c | 48 | ||||
| -rw-r--r-- | drivers/net/phy/Kconfig | 9 | ||||
| -rw-r--r-- | drivers/net/phy/cortina.c | 8 |
5 files changed, 60 insertions, 10 deletions
diff --git a/drivers/net/fsl-mc/Kconfig b/drivers/net/fsl-mc/Kconfig index 2cf651d3b3..ae4c35799b 100644 --- a/drivers/net/fsl-mc/Kconfig +++ b/drivers/net/fsl-mc/Kconfig @@ -4,7 +4,7 @@ menuconfig FSL_MC_ENET bool "NXP Management Complex" - depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A + depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A || ARCH_LX2162A default y select RESV_RAM help @@ -17,7 +17,7 @@ if FSL_MC_ENET config SYS_MC_RSV_MEM_ALIGN hex "Management Complex reserved memory alignment" depends on RESV_RAM - default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A + default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A || ARCH_LX2162A help Reserved memory needs to be aligned for MC to use. Default value is 512MB. diff --git a/drivers/net/ldpaa_eth/Makefile b/drivers/net/ldpaa_eth/Makefile index 1d85b2cfa8..52ab828f0b 100644 --- a/drivers/net/ldpaa_eth/Makefile +++ b/drivers/net/ldpaa_eth/Makefile @@ -7,3 +7,4 @@ obj-y += ldpaa_eth.o obj-$(CONFIG_ARCH_LS2080A) += ls2080a.o obj-$(CONFIG_ARCH_LS1088A) += ls1088a.o obj-$(CONFIG_ARCH_LX2160A) += lx2160a.o +obj-$(CONFIG_ARCH_LX2162A) += lx2160a.o diff --git a/drivers/net/pfe_eth/pfe_firmware.c b/drivers/net/pfe_eth/pfe_firmware.c index d414c750d4..41999e176d 100644 --- a/drivers/net/pfe_eth/pfe_firmware.c +++ b/drivers/net/pfe_eth/pfe_firmware.c @@ -10,6 +10,8 @@ * files. */ +#include <dm.h> +#include <dm/device-internal.h> #include <image.h> #include <log.h> #include <malloc.h> @@ -24,6 +26,9 @@ #define PFE_FIRMWARE_FIT_CNF_NAME "config@1" static const void *pfe_fit_addr; +#ifdef CONFIG_CHAIN_OF_TRUST +static const void *pfe_esbc_hdr_addr; +#endif /* * PFE elf firmware loader. @@ -169,7 +174,7 @@ int pfe_spi_flash_init(void) struct spi_flash *pfe_flash; struct udevice *new; int ret = 0; - void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); + void *addr = malloc(CONFIG_SYS_LS_PFE_FW_LENGTH); if (!addr) return -ENOMEM; @@ -179,21 +184,56 @@ int pfe_spi_flash_init(void) CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE, &new); + if (ret) { + printf("SF: failed to probe spi\n"); + free(addr); + device_remove(new, DM_REMOVE_NORMAL); + return ret; + } + pfe_flash = dev_get_uclass_priv(new); if (!pfe_flash) { printf("SF: probe for pfe failed\n"); free(addr); + device_remove(new, DM_REMOVE_NORMAL); return -ENODEV; } ret = spi_flash_read(pfe_flash, CONFIG_SYS_LS_PFE_FW_ADDR, - CONFIG_SYS_QE_FMAN_FW_LENGTH, + CONFIG_SYS_LS_PFE_FW_LENGTH, addr); - if (ret) + if (ret) { printf("SF: read for pfe failed\n"); + free(addr); + spi_flash_free(pfe_flash); + return ret; + } +#ifdef CONFIG_CHAIN_OF_TRUST + void *hdr_addr = malloc(CONFIG_SYS_LS_PFE_ESBC_LENGTH); + + if (!hdr_addr) { + free(addr); + spi_flash_free(pfe_flash); + return -ENOMEM; + } + + ret = spi_flash_read(pfe_flash, + CONFIG_SYS_LS_PFE_ESBC_ADDR, + CONFIG_SYS_LS_PFE_ESBC_LENGTH, + hdr_addr); + if (ret) { + printf("SF: failed to read pfe esbc header\n"); + free(addr); + free(hdr_addr); + spi_flash_free(pfe_flash); + return ret; + } + + pfe_esbc_hdr_addr = hdr_addr; +#endif pfe_fit_addr = addr; spi_flash_free(pfe_flash); @@ -233,7 +273,7 @@ int pfe_firmware_init(void) goto err; #ifdef CONFIG_CHAIN_OF_TRUST - pfe_esbc_hdr = CONFIG_SYS_LS_PFE_ESBC_ADDR; + pfe_esbc_hdr = (uintptr_t)pfe_esbc_hdr_addr; pfe_img_addr = (uintptr_t)pfe_fit_addr; if (fsl_check_boot_mode_secure() != 0) { /* diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 4e1a93be22..51733dd123 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -100,6 +100,15 @@ config PHY_BROADCOM config PHY_CORTINA bool "Cortina Ethernet PHYs support" +config SYS_CORTINA_NO_FW_UPLOAD + bool "Cortina firmware loading support" + default n + depends on PHY_CORTINA + help + Cortina phy has provision to store phy firmware in attached dedicated + EEPROM. And boards designed with such EEPROM does not require firmware + upload. + choice prompt "Location of the Cortina firmware" default SYS_CORTINA_FW_IN_NOR diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c index dbc20b1405..b381a431fd 100644 --- a/drivers/net/phy/cortina.c +++ b/drivers/net/phy/cortina.c @@ -3,7 +3,7 @@ * Cortina CS4315/CS4340 10G PHY drivers * * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2018 NXP + * Copyright 2018, 2020 NXP * */ @@ -29,7 +29,7 @@ #error The Cortina PHY needs 10G support #endif -#ifndef CORTINA_NO_FW_UPLOAD +#ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD struct cortina_reg_config cortina_reg_cfg[] = { /* CS4315_enable_sr_mode */ {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004}, @@ -227,7 +227,7 @@ void cs4340_upload_firmware(struct phy_device *phydev) int cs4340_phy_init(struct phy_device *phydev) { -#ifndef CORTINA_NO_FW_UPLOAD +#ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD int timeout = 100; /* 100ms */ #endif int reg_value; @@ -238,7 +238,7 @@ int cs4340_phy_init(struct phy_device *phydev) * Boards designed with EEPROM attached to Cortina * does not require FW upload. */ -#ifndef CORTINA_NO_FW_UPLOAD +#ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD /* step1: BIST test */ phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL, 0x0004); phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000); |