diff options
Diffstat (limited to 'drivers/fpga/zynqpl.c')
| -rw-r--r-- | drivers/fpga/zynqpl.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 0c83df46da..53dd780a6c 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -36,8 +36,8 @@ #define DEVCFG_MCTRL_RFIFO_FLUSH 0x00000002 #define DEVCFG_MCTRL_WFIFO_FLUSH 0x00000001 -#ifndef CONFIG_SYS_FPGA_WAIT -#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ +#ifndef CFG_SYS_FPGA_WAIT +#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ #endif #ifndef CONFIG_SYS_FPGA_PROG_TIME @@ -232,7 +232,7 @@ static int zynq_dma_xfer_init(bitstream_type bstype) /* Polling the PCAP_INIT status for Reset */ ts = get_timer(0); while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) { - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT) { printf("%s: Timeout wait for INIT to clear\n", __func__); return FPGA_FAIL; @@ -246,7 +246,7 @@ static int zynq_dma_xfer_init(bitstream_type bstype) ts = get_timer(0); while (!(readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT)) { - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT) { printf("%s: Timeout wait for INIT to set\n", __func__); return FPGA_FAIL; @@ -400,7 +400,7 @@ static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize, /* Check FPGA configuration completion */ ts = get_timer(0); while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) { - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT) { printf("%s: Timeout wait for FPGA to config\n", __func__); return FPGA_FAIL; @@ -484,7 +484,7 @@ static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, /* Check FPGA configuration completion */ ts = get_timer(0); while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) { - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT) { printf("%s: Timeout wait for FPGA to config\n", __func__); return FPGA_FAIL; @@ -561,7 +561,7 @@ int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen, /* Check FPGA configuration completion */ ts = get_timer(0); while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) { - if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) { + if (get_timer(ts) > CFG_SYS_FPGA_WAIT) { printf("%s: Timeout wait for FPGA to config\n", __func__); return FPGA_FAIL; |