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-rw-r--r--drivers/ddr/fsl/arm_ddr_gen3.c10
-rw-r--r--drivers/ddr/fsl/ctrl_regs.c2
-rw-r--r--drivers/ddr/fsl/fsl_ddr_gen4.c10
-rw-r--r--drivers/ddr/fsl/fsl_mmdc.c2
-rw-r--r--drivers/ddr/fsl/main.c12
-rw-r--r--drivers/ddr/fsl/mpc85xx_ddr_gen1.c4
-rw-r--r--drivers/ddr/fsl/mpc85xx_ddr_gen2.c2
-rw-r--r--drivers/ddr/fsl/mpc85xx_ddr_gen3.c10
-rw-r--r--drivers/ddr/fsl/util.c26
9 files changed, 39 insertions, 39 deletions
diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c
index 629ba6784e..5e8fb7a89c 100644
--- a/drivers/ddr/fsl/arm_ddr_gen3.c
+++ b/drivers/ddr/fsl/arm_ddr_gen3.c
@@ -40,16 +40,16 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
switch (ctrl_num) {
case 0:
- ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
+#if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
- ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
+#if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
- ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR3_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 0b0b4e5cb7..df7ec48465 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -2590,7 +2590,7 @@ compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
void erratum_a009942_check_cpo(void)
{
struct ccsr_ddr __iomem *ddr =
- (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
+ (struct ccsr_ddr __iomem *)(CFG_SYS_FSL_DDR_ADDR);
u32 cpo, cpo_e, cpo_o, cpo_target, cpo_optimal;
u32 cpo_min = ddr_in32(&ddr->debug[9]) >> 24;
u32 cpo_max = cpo_min;
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index 89cb4d352e..3c1f7a1891 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -86,16 +86,16 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
#endif
switch (ctrl_num) {
case 0:
- ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
+#if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
- ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
+#if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
- ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR3_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
diff --git a/drivers/ddr/fsl/fsl_mmdc.c b/drivers/ddr/fsl/fsl_mmdc.c
index cbd625b7ee..28f2219b2a 100644
--- a/drivers/ddr/fsl/fsl_mmdc.c
+++ b/drivers/ddr/fsl/fsl_mmdc.c
@@ -28,7 +28,7 @@ static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
void mmdc_init(const struct fsl_mmdc_info *priv)
{
- struct mmdc_regs *mmdc = (struct mmdc_regs *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct mmdc_regs *mmdc = (struct mmdc_regs *)CFG_SYS_FSL_DDR_ADDR;
unsigned int tmp;
/* 1. set configuration request */
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index ed3313a531..fcff223b4f 100644
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -21,18 +21,18 @@
#include <asm/bitops.h>
/*
- * CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view
+ * CFG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view
* of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for
* all Power SoCs. But it could be different for ARM SoCs. For example,
* fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of
* 0x00_8000_0000 ~ 0x00_ffff_ffff
* 0x80_8000_0000 ~ 0xff_ffff_ffff
*/
-#ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
+#ifndef CFG_SYS_FSL_DDR_SDRAM_BASE_PHY
#ifdef CONFIG_MPC83xx
-#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE
+#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE
#else
-#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
#endif
#endif
@@ -898,7 +898,7 @@ phys_size_t fsl_ddr_sdram(void)
/* Reset info structure. */
memset(&info, 0, sizeof(fsl_ddr_info_t));
- info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
+ info.mem_base = CFG_SYS_FSL_DDR_SDRAM_BASE_PHY;
info.first_ctrl = 0;
info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
@@ -946,7 +946,7 @@ fsl_ddr_sdram_size(void)
unsigned long long total_memory = 0;
memset(&info, 0 , sizeof(fsl_ddr_info_t));
- info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
+ info.mem_base = CFG_SYS_FSL_DDR_SDRAM_BASE_PHY;
info.first_ctrl = 0;
info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
index 9c2ddeaf93..0f1e99eeb0 100644
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c
@@ -18,7 +18,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
{
unsigned int i;
struct ccsr_ddr __iomem *ddr =
- (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
+ (struct ccsr_ddr __iomem *)CFG_SYS_FSL_DDR_ADDR;
if (ctrl_num != 0) {
printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
@@ -71,7 +71,7 @@ void
ddr_enable_ecc(unsigned int dram_size)
{
struct ccsr_ddr __iomem *ddr =
- (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
+ (struct ccsr_ddr __iomem *)(CFG_SYS_FSL_DDR_ADDR);
dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c
index 9ed80d63ef..b830e7cbd1 100644
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c
@@ -18,7 +18,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
{
unsigned int i;
struct ccsr_ddr __iomem *ddr =
- (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
+ (struct ccsr_ddr __iomem *)CFG_SYS_FSL_DDR_ADDR;
#if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85xx)
ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
index 47339c5973..0f2dc243cb 100644
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
@@ -52,16 +52,16 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
switch (ctrl_num) {
case 0:
- ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
+#if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
- ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
+#if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
- ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR3_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c
index 589d7df731..e49cf6e8e3 100644
--- a/drivers/ddr/fsl/util.c
+++ b/drivers/ddr/fsl/util.c
@@ -34,16 +34,16 @@ u32 fsl_ddr_get_version(unsigned int ctrl_num)
switch (ctrl_num) {
case 0:
- ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
+#if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
- ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
+#if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
- ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR3_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
@@ -181,7 +181,7 @@ u32 fsl_ddr_get_intl3r(void)
void print_ddr_info(unsigned int start_ctrl)
{
struct ccsr_ddr __iomem *ddr =
- (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
+ (struct ccsr_ddr __iomem *)(CFG_SYS_FSL_DDR_ADDR);
#if defined(CONFIG_E6500) && (CONFIG_SYS_NUM_DDR_CTLRS == 3)
u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
@@ -195,14 +195,14 @@ void print_ddr_info(unsigned int start_ctrl)
#if CONFIG_SYS_NUM_DDR_CTLRS >= 2
if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
(start_ctrl == 1)) {
- ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR;
+ ddr = (void __iomem *)CFG_SYS_FSL_DDR2_ADDR;
sdram_cfg = ddr_in32(&ddr->sdram_cfg);
}
#endif
#if CONFIG_SYS_NUM_DDR_CTLRS >= 3
if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) ||
(start_ctrl == 2)) {
- ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR;
+ ddr = (void __iomem *)CFG_SYS_FSL_DDR3_ADDR;
sdram_cfg = ddr_in32(&ddr->sdram_cfg);
}
#endif
@@ -353,16 +353,16 @@ void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
for (i = first_ctrl; i <= last_ctrl; i++) {
switch (i) {
case 0:
- ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
+#if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
- ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
+#if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
- ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+ ddr = (void *)CFG_SYS_FSL_DDR3_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-12 21:10:39 +0000