aboutsummaryrefslogtreecommitdiff
path: root/board/freescale/common/p_corenet/tlb.c
diff options
context:
space:
mode:
Diffstat (limited to 'board/freescale/common/p_corenet/tlb.c')
-rw-r--r--board/freescale/common/p_corenet/tlb.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c
index 3d9459b133..c0ab1a5fd1 100644
--- a/board/freescale/common/p_corenet/tlb.c
+++ b/board/freescale/common/p_corenet/tlb.c
@@ -43,7 +43,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
/* *I*** - Covers boot page */
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
-#if !defined(CONFIG_SECURE_BOOT)
+#if !defined(CONFIG_NXP_ESBC)
/*
* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
* SRAM is at 0xfff00000, it covered the 0xfffff000.