6 files changed, 26 insertions, 40 deletions
diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp
index 805fe934a1..ad61dabb31 100644
--- a/arch/Kconfig.nxp
+++ b/arch/Kconfig.nxp
@@ -1,5 +1,10 @@
+config FSL_TRUST_ARCH_v1
+	bool
+
 config NXP_ESBC
 	bool "NXP ESBC (secure boot) functionality"
+	select FSL_TRUST_ARCH_v1 if ARCH_P3041 || ARCH_P4080 || \
+		ARCH_P5040 || ARCH_P2041
 	help
 	  Enable Freescale Secure Boot feature. Normally selected by defconfig.
 	  If unsure, do not change.
@@ -10,6 +15,7 @@ menu "Chain of trust / secure boot options"
 config CHAIN_OF_TRUST
 	select FSL_CAAM
 	select ARCH_MISC_INIT
+	select FSL_ISBC_KEY_EXT if (ARM || FSL_CORENET) && !SYS_RAMBOOT
 	select FSL_SEC_MON
 	select SPL_BOARD_INIT if (ARM && SPL)
 	select SPL_HASH if (ARM && SPL)
@@ -41,6 +47,17 @@ config ESBC_ADDR_64BIT
 	help
 	  For Layerscape based platforms, ESBC image Address in Header is 64bit.
 
+config FSL_ISBC_KEY_EXT
+	bool
+	help
+	  The key used for verification of next level images is picked up from
+	  an Extension Table which has been verified by the ISBC (Internal
+	  Secure boot Code) in boot ROM of the SoC.  The feature is only
+	  applicable in case of NOR boot and is not applicable in case of
+	  RAMBOOT (NAND, SD, SPI).  For Layerscape, this feature is available
+	  for all device if IE Table is copied to XIP memory Also, for
+	  Layerscape, ISBC doesn't verify this table.
+
 config SYS_FSL_SFP_BE
 	def_bool y
 	depends on PPC || FSL_LSCH2 || ARCH_LS1021A
diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h
index a4f4961fc8..6a9d198cb8 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -9,21 +9,6 @@
 
 #ifdef CONFIG_CHAIN_OF_TRUST
 #ifndef CONFIG_SPL_BUILD
-#ifndef CONFIG_SYS_RAMBOOT
-/* The key used for verification of next level images
- * is picked up from an Extension Table which has
- * been verified by the ISBC (Internal Secure boot Code)
- * in boot ROM of the SoC.
- * The feature is only applicable in case of NOR boot and is
- * not applicable in case of RAMBOOT (NAND, SD, SPI).
- * For LS, this feature is available for all device if IE Table
- * is copied to XIP memory
- * Also, for LS, ISBC doesn't verify this table.
- */
-#define CONFIG_FSL_ISBC_KEY_EXT
-
-#endif
-
 #ifdef CONFIG_FSL_LS_PPA
 /* Define the key hash here if SRK used for signing PPA image is
  * different from SRK hash put in SFP used for U-Boot.
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 383af83066..8f3aee052c 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -4,6 +4,9 @@ config BOARD_COMMON
 	def_bool y
 	depends on !TARGET_SMDKV310 && !TARGET_ARNDALE
 
+config SPI_BOOTING
+	bool
+
 config USB_BOOTING
 	bool
 
@@ -27,6 +30,7 @@ config ARCH_EXYNOS5
 	select BOARD_EARLY_INIT_F
 	select CPU_V7A
 	select SHA_HW_ACCEL
+	select SPI_BOOTING if EXYNOS5_DT
 	select USB_BOOTING
 	imply CMD_HASH
 	imply CRC32_VERIFY
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index f2361560e9..721dafc5ab 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -1324,6 +1324,11 @@ config SYS_ULB_CLK
 config SYS_ETVPE_CLK
 	int
 	default 1
+
+config MAX_DSP_CPUS
+	int
+	default 12 if ARCH_B4860
+	default 2 if ARCH_B4420
 endif
 
 config SYS_L2_SIZE_256KB
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 1b5b4947f1..edaf8baaae 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -23,7 +23,6 @@
 #define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
 
 #elif defined(CONFIG_ARCH_P1010)
-#define CONFIG_FSL_SDHC_V2_3
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	4
 
 #elif defined(CONFIG_ARCH_P1021)
@@ -93,11 +92,9 @@
 #define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 
 #elif defined(CONFIG_ARCH_BSC9131)
-#define CONFIG_FSL_SDHC_V2_3
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	3
 
 #elif defined(CONFIG_ARCH_BSC9132)
-#define CONFIG_FSL_SDHC_V2_3
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	3
 
 #elif defined(CONFIG_ARCH_T4240)
@@ -136,7 +133,6 @@
 #define CFG_SYS_FM_MURAM_SIZE	0x60000
 
 #ifdef CONFIG_ARCH_B4860
-#define CONFIG_MAX_DSP_CPUS		12
 #define CONFIG_NUM_DSP_CPUS		6
 #define CFG_SYS_FSL_CLUSTER_CLOCKS	{ 1, 4, 4, 4 }
 #define CFG_SYS_NUM_FM1_DTSEC	6
@@ -145,7 +141,6 @@
 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM	5
 #else
-#define CONFIG_MAX_DSP_CPUS		2
 #define CFG_SYS_FSL_CLUSTER_CLOCKS	{ 1, 4 }
 #define CFG_SYS_NUM_FM1_DTSEC	4
 #define CFG_SYS_NUM_FM1_10GEC	0
@@ -173,7 +168,6 @@
 #define CFG_SYS_NUM_FMAN		1
 #define CFG_SYS_NUM_FM1_DTSEC	4
 #define CFG_SYS_NUM_FM1_10GEC	1
-#define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CFG_SYS_FM1_CLK		0
 #define CONFIG_QBMAN_CLK_DIV		1
@@ -204,7 +198,6 @@
 
 
 #elif defined(CONFIG_ARCH_C29X)
-#define CONFIG_FSL_SDHC_V2_3
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CFG_SYS_FSL_SEC_IDX_OFFSET	0x20000
 
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
index e8b2680206..09f37ec3e4 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -35,24 +35,6 @@
 #define CFG_SYS_INIT_L3_ADDR		0xbff00000
 #endif
 #endif
-
-#if defined(CONFIG_ARCH_P3041)	||	\
-	defined(CONFIG_ARCH_P4080) ||	\
-	defined(CONFIG_ARCH_P5040) ||	\
-	defined(CONFIG_ARCH_P2041)
-	#define	CONFIG_FSL_TRUST_ARCH_v1
-#endif
-
-#if defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_RAMBOOT)
-/* The key used for verification of next level images
- * is picked up from an Extension Table which has
- * been verified by the ISBC (Internal Secure boot Code)
- * in boot ROM of the SoC.
- * The feature is only applicable in case of NOR boot and is
- * not applicable in case of RAMBOOT (NAND, SD, SPI).
- */
-#define CONFIG_FSL_ISBC_KEY_EXT
-#endif
 #endif /* #ifdef CONFIG_NXP_ESBC */
 
 #ifdef CONFIG_CHAIN_OF_TRUST