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-rw-r--r--arch/arm/dts/Makefile3
-rw-r--r--arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi6
-rw-r--r--arch/arm/dts/imx7d-pico-pi-u-boot.dtsi10
-rw-r--r--arch/arm/dts/imx7s-warp-u-boot.dtsi14
-rw-r--r--arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi6
-rw-r--r--arch/arm/dts/sun50i-h616-orangepi-zero.dtsi3
-rw-r--r--arch/arm/dts/sun50i-h616-orangepi-zero2.dts3
-rw-r--r--arch/arm/dts/sun50i-h618-orangepi-zero3.dts2
-rw-r--r--arch/arm/mach-apple/board.c48
-rw-r--r--arch/arm/mach-imx/imx8m/clock_imx8mm.c1
-rw-r--r--arch/riscv/dts/binman.dtsi14
-rw-r--r--arch/riscv/dts/jh7110.dtsi10
-rw-r--r--arch/riscv/lib/andes_plicsw.c33
-rw-r--r--arch/sandbox/dts/test.dts4
-rw-r--r--arch/sandbox/include/asm/clk.h1
15 files changed, 116 insertions, 42 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ef0e705f3d..e9e58c5478 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -835,6 +835,7 @@ dtb-$(CONFIG_MACH_SUN50I_H6) += \
sun50i-h6-tanix-tx6-mini.dtb
dtb-$(CONFIG_MACH_SUN50I_H616) += \
sun50i-h616-orangepi-zero2.dtb \
+ sun50i-h618-orangepi-zero3.dtb \
sun50i-h616-x96-mate.dtb
dtb-$(CONFIG_MACH_SUN50I) += \
sun50i-a64-amarula-relic.dtb \
@@ -1516,6 +1517,8 @@ targets += $(dtb-y)
# Add any required device tree compiler flags here
DTC_FLAGS += -a 0x8
+DTC_FLAGS_imx8mp-dhcom-pdk3-overlay-rev100 += -Wno-avoid_default_addr_size -Wno-reg_format
+
PHONY += dtbs
dtbs: $(addprefix $(obj)/, $(dtb-y))
@:
diff --git a/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi
index f2d6b183ed..c54a59e89c 100644
--- a/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi
+++ b/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi
@@ -93,6 +93,12 @@
&gpio4 {
bootph-some-ram;
+
+ usbh_en {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_HIGH>;
+ output-high;
+ };
};
&gpio5 {
diff --git a/arch/arm/dts/imx7d-pico-pi-u-boot.dtsi b/arch/arm/dts/imx7d-pico-pi-u-boot.dtsi
index 3dd01e36a4..3b5f14ecb0 100644
--- a/arch/arm/dts/imx7d-pico-pi-u-boot.dtsi
+++ b/arch/arm/dts/imx7d-pico-pi-u-boot.dtsi
@@ -7,6 +7,12 @@
usb0 = &usbotg1;
display0 = &lcdif;
};
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ bootph-pre-ram;
+ };
};
&usbotg1 {
@@ -46,6 +52,10 @@
};
};
+&wdog1 {
+ bootph-pre-ram;
+};
+
&iomuxc {
pinctrl_backlight: backlight {
fsl,pins = <
diff --git a/arch/arm/dts/imx7s-warp-u-boot.dtsi b/arch/arm/dts/imx7s-warp-u-boot.dtsi
index 49b992dccc..4f44598c9a 100644
--- a/arch/arm/dts/imx7s-warp-u-boot.dtsi
+++ b/arch/arm/dts/imx7s-warp-u-boot.dtsi
@@ -1,12 +1,12 @@
/ {
- aliases {
- mmc0 = &usdhc3;
- usb0 = &usbotg1;
- };
+ aliases {
+ mmc0 = &usdhc3;
+ usb0 = &usbotg1;
+ };
- chosen {
- stdout-path = &uart1;
- };
+ chosen {
+ stdout-path = &uart1;
+ };
};
&aips3 {
diff --git a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
index e0caf3179e..2bbc4a4941 100644
--- a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
@@ -39,11 +39,11 @@
};
&i2c1 {
- bootph-pre-ram;
+ bootph-all;
};
&pinctrl_i2c1 {
- bootph-pre-ram;
+ bootph-all;
};
&pinctrl_pmic {
@@ -83,5 +83,5 @@
};
&eeprom_som {
- bootph-pre-ram;
+ bootph-all;
};
diff --git a/arch/arm/dts/sun50i-h616-orangepi-zero.dtsi b/arch/arm/dts/sun50i-h616-orangepi-zero.dtsi
index 15290e6892..fc7315b944 100644
--- a/arch/arm/dts/sun50i-h616-orangepi-zero.dtsi
+++ b/arch/arm/dts/sun50i-h616-orangepi-zero.dtsi
@@ -68,10 +68,7 @@
&emac0 {
pinctrl-names = "default";
pinctrl-0 = <&ext_rgmii_pins>;
- phy-mode = "rgmii";
phy-handle = <&ext_rgmii_phy>;
- allwinner,rx-delay-ps = <3100>;
- allwinner,tx-delay-ps = <700>;
status = "okay";
};
diff --git a/arch/arm/dts/sun50i-h616-orangepi-zero2.dts b/arch/arm/dts/sun50i-h616-orangepi-zero2.dts
index d83852e72f..b5d713926a 100644
--- a/arch/arm/dts/sun50i-h616-orangepi-zero2.dts
+++ b/arch/arm/dts/sun50i-h616-orangepi-zero2.dts
@@ -13,6 +13,9 @@
};
&emac0 {
+ allwinner,rx-delay-ps = <3100>;
+ allwinner,tx-delay-ps = <700>;
+ phy-mode = "rgmii";
phy-supply = <&reg_dcdce>;
};
diff --git a/arch/arm/dts/sun50i-h618-orangepi-zero3.dts b/arch/arm/dts/sun50i-h618-orangepi-zero3.dts
index 00fe28caac..b3b1b86921 100644
--- a/arch/arm/dts/sun50i-h618-orangepi-zero3.dts
+++ b/arch/arm/dts/sun50i-h618-orangepi-zero3.dts
@@ -13,6 +13,8 @@
};
&emac0 {
+ allwinner,tx-delay-ps = <700>;
+ phy-mode = "rgmii-rxid";
phy-supply = <&reg_dldo1>;
};
diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c
index 47393babbc..7a6151a972 100644
--- a/arch/arm/mach-apple/board.c
+++ b/arch/arm/mach-apple/board.c
@@ -372,6 +372,22 @@ static struct mm_region t6020_mem_map[] = {
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
+ .virt = 0x400000000,
+ .phys = 0x400000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x480000000,
+ .phys = 0x480000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
.virt = 0x580000000,
.phys = 0x580000000,
.size = SZ_512M,
@@ -473,6 +489,22 @@ static struct mm_region t6022_mem_map[] = {
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
+ .virt = 0x400000000,
+ .phys = 0x400000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x480000000,
+ .phys = 0x480000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
.virt = 0x580000000,
.phys = 0x580000000,
.size = SZ_512M,
@@ -553,6 +585,22 @@ static struct mm_region t6022_mem_map[] = {
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* I/O */
+ .virt = 0x2400000000,
+ .phys = 0x2400000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x2480000000,
+ .phys = 0x2480000000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
.virt = 0x2580000000,
.phys = 0x2580000000,
.size = SZ_512M,
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 5cf97a5ea9..47219957b5 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -56,6 +56,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
PLL_1443X_RATE(1000000000U, 250, 3, 1, 0),
PLL_1443X_RATE(933000000U, 311, 4, 1, 0),
+ PLL_1443X_RATE(900000000U, 300, 8, 0, 0),
PLL_1443X_RATE(800000000U, 300, 9, 0, 0),
PLL_1443X_RATE(750000000U, 250, 8, 0, 0),
PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi
index 6b4eb8dc7b..9271de0ddf 100644
--- a/arch/riscv/dts/binman.dtsi
+++ b/arch/riscv/dts/binman.dtsi
@@ -5,9 +5,6 @@
#include <config.h>
-#define U64_TO_U32_H(addr) (((addr) >> 32) & 0xffffffff)
-#define U64_TO_U32_L(addr) ((addr) & 0xffffffff)
-
/ {
binman: binman {
multiple-images;
@@ -36,8 +33,7 @@
os = "U-Boot";
arch = "riscv";
compression = "none";
- load = <U64_TO_U32_H(CONFIG_TEXT_BASE)
- U64_TO_U32_L(CONFIG_TEXT_BASE)>;
+ load = /bits/ 64 <CONFIG_TEXT_BASE>;
uboot_blob: blob-ext {
filename = "u-boot-nodtb.bin";
@@ -50,7 +46,7 @@
os = "Linux";
arch = "riscv";
compression = "none";
- load = <CONFIG_TEXT_BASE>;
+ load = /bits/ 64 <CONFIG_TEXT_BASE>;
linux_blob: blob-ext {
filename = "Image";
@@ -64,10 +60,8 @@
os = "opensbi";
arch = "riscv";
compression = "none";
- load = <U64_TO_U32_H(CONFIG_SPL_OPENSBI_LOAD_ADDR)
- U64_TO_U32_L(CONFIG_SPL_OPENSBI_LOAD_ADDR)>;
- entry = <U64_TO_U32_H(CONFIG_SPL_OPENSBI_LOAD_ADDR)
- U64_TO_U32_L(CONFIG_SPL_OPENSBI_LOAD_ADDR)>;
+ load = /bits/ 64 <CONFIG_SPL_OPENSBI_LOAD_ADDR>;
+ entry = /bits/ 64 <CONFIG_SPL_OPENSBI_LOAD_ADDR>;
opensbi_blob: opensbi {
filename = "fw_dynamic.bin";
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index 13c47f7caa..6d2675d6ce 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -533,6 +533,16 @@
#gpio-cells = <2>;
};
+ watchdog@13070000 {
+ compatible = "starfive,jh7110-wdt";
+ reg = <0x0 0x13070000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_WDT_APB>,
+ <&syscrg JH7110_SYSCLK_WDT_CORE>;
+ clock-names = "apb", "core";
+ resets = <&syscrg JH7110_SYSRST_WDT_APB>,
+ <&syscrg JH7110_SYSRST_WDT_CORE>;
+ };
+
mmc0: mmc@16010000 {
compatible = "starfive,jh7110-mmc";
reg = <0x0 0x16010000 0x0 0x10000>;
diff --git a/arch/riscv/lib/andes_plicsw.c b/arch/riscv/lib/andes_plicsw.c
index 6a63661312..c09e5c69bc 100644
--- a/arch/riscv/lib/andes_plicsw.c
+++ b/arch/riscv/lib/andes_plicsw.c
@@ -21,41 +21,36 @@
#include <linux/err.h>
/* pending register */
-#define PENDING_REG(base) ((ulong)(base) + 0x1000)
+#define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + 4 * (((hart) + 1) / 32))
/* enable register */
-#define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80)
+#define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80 + 4 * (((hart) + 1) / 32))
/* claim register */
#define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000)
/* priority register */
#define PRIORITY_REG(base) ((ulong)(base) + PLICSW_PRIORITY_BASE)
/* Bit 0 of PLIC-SW pending array is hardwired to zero, so we start from bit 1 */
-#define FIRST_AVAILABLE_BIT 0x2
-#define SEND_IPI_TO_HART(hart) (FIRST_AVAILABLE_BIT << (hart))
#define PLICSW_PRIORITY_BASE 0x4
-#define PLICSW_INTERRUPT_PER_HART 0x1
DECLARE_GLOBAL_DATA_PTR;
static int enable_ipi(int hart)
{
- unsigned int en;
+ u32 enable_bit = (hart + 1) % 32;
- en = FIRST_AVAILABLE_BIT << hart;
- writel(en, (void __iomem *)ENABLE_REG(gd->arch.plicsw, hart));
+ writel(BIT(enable_bit), (void __iomem *)ENABLE_REG(gd->arch.plicsw, hart));
return 0;
}
static void init_priority_ipi(int hart_num)
{
- uint32_t *priority = (void *)PRIORITY_REG(gd->arch.plicsw);
+ u32 *priority = (void *)PRIORITY_REG(gd->arch.plicsw);
- for (int i = 0; i < hart_num * PLICSW_INTERRUPT_PER_HART; i++) {
- writel(1, &priority[i]);
- }
+ for (int i = 0; i < hart_num; i++)
+ writel(1, &priority[i]);
- return;
+ return;
}
int riscv_init_ipi(void)
@@ -104,9 +99,10 @@ int riscv_init_ipi(void)
int riscv_send_ipi(int hart)
{
- unsigned int ipi = SEND_IPI_TO_HART(hart);
+ u32 interrupt_id = hart + 1;
+ u32 pending_bit = interrupt_id % 32;
- writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plicsw));
+ writel(BIT(pending_bit), (void __iomem *)PENDING_REG(gd->arch.plicsw, hart));
return 0;
}
@@ -123,10 +119,11 @@ int riscv_clear_ipi(int hart)
int riscv_get_ipi(int hart, int *pending)
{
- unsigned int ipi = SEND_IPI_TO_HART(hart);
+ u32 interrupt_id = hart + 1;
+ u32 pending_bit = interrupt_id % 32;
- *pending = readl((void __iomem *)PENDING_REG(gd->arch.plicsw));
- *pending = !!(*pending & ipi);
+ *pending = readl((void __iomem *)PENDING_REG(gd->arch.plicsw, hart));
+ *pending = !!(*pending & BIT(pending_bit));
return 0;
}
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 9131eda970..4fe72664c4 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -631,9 +631,10 @@
clocks = <&clk_fixed>,
<&clk_sandbox 1>,
<&clk_sandbox 0>,
+ <&ccf 11>,
<&clk_sandbox 3>,
<&clk_sandbox 2>;
- clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
+ clock-names = "fixed", "i2c", "spi", "i2c_root", "uart2", "uart1";
};
clk-test2 {
@@ -654,6 +655,7 @@
ccf: clk-ccf {
compatible = "sandbox,clk-ccf";
+ #clock-cells = <1>;
};
efi-media {
diff --git a/arch/sandbox/include/asm/clk.h b/arch/sandbox/include/asm/clk.h
index 2b7dbca8f7..d4e04ad148 100644
--- a/arch/sandbox/include/asm/clk.h
+++ b/arch/sandbox/include/asm/clk.h
@@ -38,6 +38,7 @@ enum sandbox_clk_test_id {
SANDBOX_CLK_TEST_ID_FIXED,
SANDBOX_CLK_TEST_ID_SPI,
SANDBOX_CLK_TEST_ID_I2C,
+ SANDBOX_CLK_TEST_ID_I2C_ROOT,
SANDBOX_CLK_TEST_ID_DEVM1,
SANDBOX_CLK_TEST_ID_DEVM2,
SANDBOX_CLK_TEST_ID_DEVM_NULL,
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-10 08:52:00 +0000