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-rw-r--r--arch/riscv/Kconfig1
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index e291456530..8fc81fb284 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -68,7 +68,6 @@ config SPL_SYS_DCACHE_OFF
config SPL_ZERO_MEM_BEFORE_USE
bool "Zero memory before use"
depends on SPL
- default n
help
Zero stack/GD/malloc area in SPL before using them, this is needed for
Sifive core devices that uses L2 cache to store SPL.