diff options
Diffstat (limited to 'arch/riscv/cpu/andesv5/cpu.c')
| -rw-r--r-- | arch/riscv/cpu/andesv5/cpu.c | 33 |
1 files changed, 24 insertions, 9 deletions
diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c index 63bc24cdfc..d25ecba0e8 100644 --- a/arch/riscv/cpu/andesv5/cpu.c +++ b/arch/riscv/cpu/andesv5/cpu.c @@ -31,19 +31,34 @@ void harts_early_init(void) /* Enable I/D-cache in SPL */ if (CONFIG_IS_ENABLED(RISCV_MMODE)) { unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL); + unsigned long mmisc_ctl_val = csr_read(CSR_MMISC_CTL); - mcache_ctl_val |= (MCACHE_CTL_DC_COHEN | MCACHE_CTL_IC_EN | - MCACHE_CTL_DC_EN | MCACHE_CTL_CCTL_SUEN); + mcache_ctl_val |= (MCACHE_CTL_CCTL_SUEN | \ + MCACHE_CTL_IC_PREFETCH_EN | MCACHE_CTL_DC_PREFETCH_EN | \ + MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN | \ + MCACHE_CTL_IC_ECCEN | MCACHE_CTL_DC_ECCEN | MCACHE_CTL_TLB_ECCEN); + + if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF)) + mcache_ctl_val |= MCACHE_CTL_IC_EN; + + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + mcache_ctl_val |= (MCACHE_CTL_DC_EN | MCACHE_CTL_DC_COHEN); csr_write(CSR_MCACHE_CTL, mcache_ctl_val); - /* - * Check mcache_ctl.DC_COHEN, we assume this platform does - * not support CM if the bit is hard-wired to 0. - */ - if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) { - /* Wait for DC_COHSTA bit to be set */ - while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA)); + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) { + /* + * Check mcache_ctl.DC_COHEN, we assume this platform does + * not support CM if the bit is hard-wired to 0. + */ + if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) { + /* Wait for DC_COHSTA bit to be set */ + while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA)); + } } + + mmisc_ctl_val |= MMISC_CTL_NON_BLOCKING_EN; + + csr_write(CSR_MMISC_CTL, mmisc_ctl_val); } } |