diff options
Diffstat (limited to 'arch/arm/mach-socfpga/include/mach/system_manager_soc64.h')
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/system_manager_soc64.h | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index 1eb8e7a904..fc4e17821b 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -42,7 +42,10 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_SOC64_GPO 0xe4 #define SYSMGR_SOC64_GPI 0xe8 #define SYSMGR_SOC64_MPU 0xf0 -/* store qspi ref clock */ +/* + * Bits[31:28] reserved for N5X DDR retention, bits[27:0] reserved for SOC 64-bit + * storing qspi ref clock (kHz) + */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD0 0x200 /* store osc1 clock freq */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD1 0x204 @@ -85,6 +88,17 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_SOC64_HPS_OSC_CLK 0x1358 #define SYSMGR_SOC64_IODELAY0 0x1400 +/* + * Bits for SYSMGR_SOC64_BOOT_SCRATCH_COLD0 + * Bits[31:28] reserved for DM DDR retention, bits[27:0] reserved for SOC 64-bit + * storing qspi ref clock (kHz) + */ +#define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK GENMASK(27, 0) +#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASK BIT(31) +#define ALT_SYSMGR_SCRATCH_REG_0_DDR_SHA_MASK BIT(30) +#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK (BIT(29) | BIT(28)) +#define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT 28 + #define SYSMGR_SDMMC SYSMGR_SOC64_SDMMC #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) |