diff options
Diffstat (limited to 'arch/arm/mach-imx/imx8ulp')
| -rw-r--r-- | arch/arm/mach-imx/imx8ulp/cgc.c | 20 | ||||
| -rw-r--r-- | arch/arm/mach-imx/imx8ulp/clock.c | 2 |
2 files changed, 12 insertions, 10 deletions
diff --git a/arch/arm/mach-imx/imx8ulp/cgc.c b/arch/arm/mach-imx/imx8ulp/cgc.c index 494ddb0f32..ccd977f1a5 100644 --- a/arch/arm/mach-imx/imx8ulp/cgc.c +++ b/arch/arm/mach-imx/imx8ulp/cgc.c @@ -187,7 +187,7 @@ void cgc1_pll3_init(ulong freq) } } -void cgc2_pll4_init(void) +void cgc2_pll4_init(bool pll4_reset) { /* Disable PFD DIV and clear DIV */ writel(0x80808080, &cgc2_regs->pll4div_pfd0); @@ -196,16 +196,18 @@ void cgc2_pll4_init(void) /* Gate off and clear PFD */ writel(0x80808080, &cgc2_regs->pll4pfdcfg); - /* Disable PLL4 */ - writel(0x0, &cgc2_regs->pll4csr); + if (pll4_reset) { + /* Disable PLL4 */ + writel(0x0, &cgc2_regs->pll4csr); - /* Configure PLL4 to 528Mhz and clock source from SOSC */ - writel(22 << 16, &cgc2_regs->pll4cfg); - writel(0x1, &cgc2_regs->pll4csr); + /* Configure PLL4 to 528Mhz and clock source from SOSC */ + writel(22 << 16, &cgc2_regs->pll4cfg); + writel(0x1, &cgc2_regs->pll4csr); - /* wait for PLL4 output valid */ - while (!(readl(&cgc2_regs->pll4csr) & BIT(24))) - ; + /* wait for PLL4 output valid */ + while (!(readl(&cgc2_regs->pll4csr) & BIT(24))) + ; + } /* Enable all 4 PFDs */ setbits_le32(&cgc2_regs->pll4pfdcfg, 18 << 0); /* 528 */ diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c index 46971578a9..69cccafbce 100644 --- a/arch/arm/mach-imx/imx8ulp/clock.c +++ b/arch/arm/mach-imx/imx8ulp/clock.c @@ -101,7 +101,7 @@ void init_clk_ddr(void) writel(0xc0000000, PCC5_LPDDR4_ADDR); /* enable pll4 and ddrclk*/ - cgc2_pll4_init(); + cgc2_pll4_init(true); cgc2_ddrclk_config(4, 1); /* enable ddr pcc */ |