diff options
Diffstat (limited to 'arch/arm/include/asm')
| -rw-r--r-- | arch/arm/include/asm/arch-rk3308/cru_rk3308.h | 15 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-rockchip/cru.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-rockchip/cru_rk3568.h | 4 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-tegra/fuse.h | 7 |
4 files changed, 27 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-rk3308/cru_rk3308.h b/arch/arm/include/asm/arch-rk3308/cru_rk3308.h index 86c906bb0e..84b63e4d56 100644 --- a/arch/arm/include/asm/arch-rk3308/cru_rk3308.h +++ b/arch/arm/include/asm/arch-rk3308/cru_rk3308.h @@ -189,6 +189,21 @@ enum { DCLK_VOP_DIV_SHIFT = 0, DCLK_VOP_DIV_MASK = 0xff, + /* CRU_CLKSEL_CON10 */ + /* CRU_CLKSEL_CON13 */ + /* CRU_CLKSEL_CON16 */ + /* CRU_CLKSEL_CON19 */ + /* CRU_CLKSEL_CON22 */ + CLK_UART_PLL_SEL_SHIFT = 13, + CLK_UART_PLL_SEL_MASK = 0x7 << CLK_UART_PLL_SEL_SHIFT, + CLK_UART_PLL_SEL_DPLL = 0, + CLK_UART_PLL_SEL_VPLL0, + CLK_UART_PLL_SEL_VPLL1, + CLK_UART_PLL_SEL_480M, + CLK_UART_PLL_SEL_24M, + CLK_UART_DIV_CON_SHIFT = 0, + CLK_UART_DIV_CON_MASK = 0x1f << CLK_UART_DIV_CON_SHIFT, + /* CRU_CLK_SEL25_CON */ /* CRU_CLK_SEL26_CON */ /* CRU_CLK_SEL27_CON */ diff --git a/arch/arm/include/asm/arch-rockchip/cru.h b/arch/arm/include/asm/arch-rockchip/cru.h index 13ea4aba8e..9778790f34 100644 --- a/arch/arm/include/asm/arch-rockchip/cru.h +++ b/arch/arm/include/asm/arch-rockchip/cru.h @@ -15,6 +15,8 @@ # include <asm/arch-rockchip/cru_rk3288.h> #elif defined(CONFIG_ROCKCHIP_RK3399) # include <asm/arch-rockchip/cru_rk3399.h> +#elif defined(CONFIG_ROCKCHIP_RK3568) +#include <asm/arch-rockchip/cru_rk3568.h> #endif /* CRU_GLB_RST_ST */ diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h index 399f19ad21..9c7ddd751f 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h @@ -106,6 +106,8 @@ struct rk3568_cru { unsigned int emmc_con[2];/* Address Offset: 0x0598 */ }; +#define rockchip_cru rk3568_cru + check_member(rk3568_cru, mode_con00, 0xc0); check_member(rk3568_cru, softrst_con[0], 0x400); @@ -493,7 +495,7 @@ enum { /* CRU_CLK_SEL81_CON */ CPLL_25M_DIV_SHIFT = 8, - CPLL_25M_DIV_MASK = 0x1f << CPLL_25M_DIV_SHIFT, + CPLL_25M_DIV_MASK = 0x3f << CPLL_25M_DIV_SHIFT, CPLL_50M_DIV_SHIFT = 0, CPLL_50M_DIV_MASK = 0x1f << CPLL_50M_DIV_SHIFT, diff --git a/arch/arm/include/asm/arch-tegra/fuse.h b/arch/arm/include/asm/arch-tegra/fuse.h index 5b8e0bd8d1..f3f2ad8e3f 100644 --- a/arch/arm/include/asm/arch-tegra/fuse.h +++ b/arch/arm/include/asm/arch-tegra/fuse.h @@ -19,4 +19,11 @@ struct fuse_regs { u32 security_mode; /* 0x1A0: FUSE_SECURITY_MODE */ }; +/** + * Calculate SoC UID + * + * Return: uid if ok, 0 on error + */ +unsigned long long tegra_chip_uid(void); + #endif /* ifndef _FUSE_H_ */ |