diff options
| -rw-r--r-- | arch/riscv/cpu/jh7110/spl.c | 32 | ||||
| -rw-r--r-- | drivers/ram/starfive/starfive_ddr.c | 2 |
2 files changed, 31 insertions, 3 deletions
diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c index 104f0fe949..72adcefa0e 100644 --- a/arch/riscv/cpu/jh7110/spl.c +++ b/arch/riscv/cpu/jh7110/spl.c @@ -3,19 +3,49 @@ * Copyright (C) 2022 StarFive Technology Co., Ltd. * Author: Yanhong Wang<yanhong.wang@starfivetech.com> */ - +#include <common.h> +#include <asm/arch/eeprom.h> #include <asm/csr.h> #include <asm/sections.h> #include <dm.h> +#include <linux/sizes.h> #include <log.h> +#include <init.h> #define CSR_U74_FEATURE_DISABLE 0x7c1 #define L2_LIM_MEM_END 0x81FFFFFUL +DECLARE_GLOBAL_DATA_PTR; + +static bool check_ddr_size(phys_size_t size) +{ + switch (size) { + case SZ_2: + case SZ_4: + case SZ_8: + case SZ_16: + return true; + default: + return false; + } +} + int spl_soc_init(void) { int ret; struct udevice *dev; + phys_size_t size; + + ret = fdtdec_setup_mem_size_base(); + if (ret) + return ret; + + /* Read the definition of the DDR size from eeprom, and if not, + * use the definition in DT + */ + size = (get_ddr_size_from_eeprom() >> 16) & 0xFF; + if (check_ddr_size(size)) + gd->ram_size = size << 30; /* DDR init */ ret = uclass_get_device(UCLASS_RAM, 0, &dev); diff --git a/drivers/ram/starfive/starfive_ddr.c b/drivers/ram/starfive/starfive_ddr.c index 553f2ce6f4..a0a3d6b33d 100644 --- a/drivers/ram/starfive/starfive_ddr.c +++ b/drivers/ram/starfive/starfive_ddr.c @@ -72,8 +72,6 @@ static int starfive_ddr_probe(struct udevice *dev) u64 rate; int ret; - /* Read memory base and size from DT */ - fdtdec_setup_mem_size_base(); priv->info.base = gd->ram_base; priv->info.size = gd->ram_size; |