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| author | Swapnil Jakhade <sjakhade@cadence.com> | 2022-01-28 13:41:47 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-02-08 11:00:03 -0500 |
| commit | 960efc5edce88dda1350f2ca1f92d3f358762112 (patch) | |
| tree | 0df4cdad2ffb236b75470a28acfcf39d54a5cd00 /tools/buildman/control.py | |
| parent | f0cb8096d9226d30b95363244287b4524742144d (diff) | |
phy: cadence: Sierra: Update single link PCIe register configuration
Add single link PCIe register configurations for no SSC and internal
SSC. Also, add missing PMA lane registers for external SSC.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Diffstat (limited to 'tools/buildman/control.py')
0 files changed, 0 insertions, 0 deletions