Merge tag 'u-boot-imx-20230713' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20230713
-------------------

Merge for 2023.10.

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/16888

16 files changed, 254 insertions, 163 deletions

diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h
index d85ae21e23..fa20651d2d 100644
--- a/include/configs/imx8mm_beacon.h
+++ b/include/configs/imx8mm_beacon.h
@@ -9,8 +9,17 @@
 #include <linux/sizes.h>
 #include <asm/arch/imx-regs.h>
 
+#define UBOOT_ITB_OFFSET			0x57C00
+#define FSPI_CONF_BLOCK_SIZE		0x1000
+#define UBOOT_ITB_OFFSET_FSPI  \
+	(UBOOT_ITB_OFFSET + FSPI_CONF_BLOCK_SIZE)
+#ifdef CONFIG_FSPI_CONF_HEADER
+#define CFG_SYS_UBOOT_BASE  \
+	(QSPI0_AMBA_BASE + UBOOT_ITB_OFFSET_FSPI)
+#else
 #define CFG_SYS_UBOOT_BASE	\
 	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+#endif
 
 #ifdef CONFIG_SPL_BUILD
 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
@@ -19,56 +28,6 @@
 
 #endif
 
-/* Initial environment variables */
-#define CFG_EXTRA_ENV_SETTINGS		\
-	"script=boot.scr\0" \
-	"image=Image\0" \
-	"console=ttymxc1,115200\0" \
-	"fdt_addr=0x43000000\0"			\
-	"boot_fit=try\0" \
-	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
-	"initrd_addr=0x43800000\0"		\
-	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
-	"mmcpart=1\0" \
-	"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
-	"mmcautodetect=yes\0" \
-	"mmcargs=setenv bootargs console=${console},${baudrate}" \
-	" root=PARTUUID=${uuid} rootwait rw ${mtdparts} ${optargs}\0" \
-	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}" \
-	" ${script};\0" \
-	"bootscript=echo Running bootscript from mmc ...; " \
-		"source\0" \
-	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
-	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
-	"mmcboot=echo Booting from mmc ...; " \
-		"run finduuid; " \
-		"run mmcargs; " \
-		"if run loadfdt; then " \
-			"booti ${loadaddr} - ${fdt_addr}; " \
-		"else " \
-			"echo WARN: Cannot load the DT; " \
-		"fi; " \
-	"netargs=setenv bootargs console=${console} " \
-		"root=/dev/nfs " \
-		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
-	"netboot=echo Booting from net ...; " \
-		"run netargs;  " \
-		"if test ${ip_dyn} = yes; then " \
-			"setenv get_cmd dhcp; " \
-		"else " \
-			"setenv get_cmd tftp; " \
-		"fi; " \
-		"${get_cmd} ${loadaddr} ${image}; " \
-		"if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
-			"bootm ${loadaddr}; " \
-		"else " \
-			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
-				"booti ${loadaddr} - ${fdt_addr}; " \
-			"else " \
-				"echo WARN: Cannot load the DT; " \
-			"fi; " \
-		"fi;\0"
-
 /* Link Definitions */
 
 #define CFG_SYS_INIT_RAM_ADDR        0x40000000
diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h
index 5579a05d16..046d5685d0 100644
--- a/include/configs/imx8mm_venice.h
+++ b/include/configs/imx8mm_venice.h
@@ -26,16 +26,16 @@
 	func(DHCP, dhcp, na)
 #include <config_distro_bootcmd.h>
 #define CFG_EXTRA_ENV_SETTINGS \
-	"splblk=0x42\0" \
 	BOOTENV
 
 #define CFG_SYS_INIT_RAM_ADDR        0x40000000
 #define CFG_SYS_INIT_RAM_SIZE        SZ_2M
 
+/* SDRAM configuration: 4GiB */
 #define CFG_SYS_SDRAM_BASE           0x40000000
-
-/* SDRAM configuration */
-#define PHYS_SDRAM                      0x40000000
-#define PHYS_SDRAM_SIZE			SZ_4G
+#define PHYS_SDRAM                   0x40000000
+#define PHYS_SDRAM_SIZE              0x80000000      /* 2 GB */
+#define PHYS_SDRAM_2                 0xC0000000
+#define PHYS_SDRAM_2_SIZE            0x80000000      /* 2 GB */
 
 #endif
diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h
index 1880d0311e..699e209044 100644
--- a/include/configs/imx8mn_beacon.h
+++ b/include/configs/imx8mn_beacon.h
@@ -12,67 +12,6 @@
 #define CFG_SYS_UBOOT_BASE	\
 	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
 
-/* Initial environment variables */
-#define CFG_EXTRA_ENV_SETTINGS		\
-	"script=boot.scr\0" \
-	"image=Image\0" \
-	"ramdiskimage=rootfs.cpio.uboot\0" \
-	"console=ttymxc1,115200\0" \
-	"fdt_addr=0x43000000\0"			\
-	"ramdisk_addr=0x44000000\0" \
-	"boot_fdt=try\0" \
-	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
-	"initrd_addr=0x43800000\0"		\
-	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
-	"mmcpart=1\0" \
-	"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
-	"mmcautodetect=yes\0" \
-	"mmcargs=setenv bootargs console=${console} " \
-	" root=PARTUUID=${uuid} rootwait rw ${mtdparts} ${optargs}\0" \
-	"ramargs=setenv bootargs console=${console} root=/dev/ram rw " \
-	" ${optargs}\0" \
-	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
-	"bootscript=echo Running bootscript from mmc ...; " \
-		"source\0" \
-	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
-	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
-	"loadramdisk=load mmc ${mmcdev} ${ramdisk_addr} ${ramdiskimage}\0"\
-	"mmcboot=echo Booting from mmc ...; " \
-		"run finduuid; run mmcargs; " \
-		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-			"if run loadfdt; then " \
-				"booti ${loadaddr} - ${fdt_addr}; " \
-			"else " \
-				"echo WARN: Cannot load the DT; " \
-			"fi; " \
-		"else " \
-			"echo wait for boot; " \
-		"fi;\0" \
-	"netargs=setenv bootargs console=${console} " \
-		"root=/dev/nfs " \
-		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
-	"netboot=echo Booting from net ...; " \
-		"run netargs;  " \
-		"if test ${ip_dyn} = yes; then " \
-			"setenv get_cmd dhcp; " \
-		"else " \
-			"setenv get_cmd tftp; " \
-		"fi; " \
-		"${get_cmd} ${loadaddr} ${image}; " \
-		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
-				"booti ${loadaddr} - ${fdt_addr}; " \
-			"else " \
-				"echo WARN: Cannot load the DT; " \
-			"fi; " \
-		"else " \
-			"booti; " \
-		"fi;\0" \
-	"ramboot=echo Booting from RAMdisk...; "\
-		"run loadimage; run loadfdt; fdt addr $fdt_addr; "\
-		"run loadramdisk; run ramargs; " \
-		"booti ${loadaddr} ${ramdisk_addr} ${fdt_addr} ${optargs}\0"
-
 /* Link Definitions */
 
 #define CFG_SYS_INIT_RAM_ADDR        0x40000000
diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h
index 80c2df9f30..1cc054a82b 100644
--- a/include/configs/imx8mn_venice.h
+++ b/include/configs/imx8mn_venice.h
@@ -20,16 +20,16 @@
 	func(DHCP, dhcp, na)
 #include <config_distro_bootcmd.h>
 #define CFG_EXTRA_ENV_SETTINGS \
-	"splblk=0x40\0" \
 	BOOTENV
 
 #define CFG_SYS_INIT_RAM_ADDR        0x40000000
 #define CFG_SYS_INIT_RAM_SIZE        SZ_2M
 
+/* SDRAM configuration: 4GiB */
 #define CFG_SYS_SDRAM_BASE           0x40000000
-
-/* SDRAM configuration */
-#define PHYS_SDRAM                      0x40000000
-#define PHYS_SDRAM_SIZE			SZ_4G
+#define PHYS_SDRAM                   0x40000000
+#define PHYS_SDRAM_SIZE              0x80000000      /* 2 GB */
+#define PHYS_SDRAM_2                 0xC0000000
+#define PHYS_SDRAM_2_SIZE            0x80000000      /* 2 GB */
 
 #endif
diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h
index 4b32d5a77e..47413ecd7f 100644
--- a/include/configs/imx8mp_venice.h
+++ b/include/configs/imx8mp_venice.h
@@ -20,16 +20,16 @@
 	func(DHCP, dhcp, na)
 #include <config_distro_bootcmd.h>
 #define CFG_EXTRA_ENV_SETTINGS \
-	"splblk=0x40\0" \
 	BOOTENV
 
 #define CFG_SYS_INIT_RAM_ADDR        0x40000000
 #define CFG_SYS_INIT_RAM_SIZE        SZ_2M
 
+/* SDRAM configuration: 4GiB */
 #define CFG_SYS_SDRAM_BASE           0x40000000
-
-/* SDRAM configuration */
-#define PHYS_SDRAM                      0x40000000
-#define PHYS_SDRAM_SIZE			SZ_4G
+#define PHYS_SDRAM                   0x40000000
+#define PHYS_SDRAM_SIZE              0x80000000      /* 2 GB */
+#define PHYS_SDRAM_2                 0xC0000000
+#define PHYS_SDRAM_2_SIZE            0x80000000      /* 2 GB */
 
 #endif
diff --git a/include/dm/platform_data/serial_pl01x.h b/include/dm/platform_data/serial_pl01x.h
index e3d4e308a1..811697ce5c 100644
--- a/include/dm/platform_data/serial_pl01x.h
+++ b/include/dm/platform_data/serial_pl01x.h
@@ -20,7 +20,11 @@ enum pl01x_type {
  * @skip_init: Don't attempt to change port configuration (also means @clock
  * is ignored)
  */
+#include <dt-structs.h>
 struct pl01x_serial_plat {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	struct dtd_serial_pl01x dtplat;
+#endif
 	unsigned long base;
 	enum pl01x_type type;
 	unsigned int clock;
diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h
index 9d5cc2ddde..3f28ce685f 100644
--- a/include/dt-bindings/clock/imx8mp-clock.h
+++ b/include/dt-bindings/clock/imx8mp-clock.h
@@ -324,8 +324,18 @@
 #define IMX8MP_CLK_CLKOUT2_SEL			317
 #define IMX8MP_CLK_CLKOUT2_DIV			318
 #define IMX8MP_CLK_CLKOUT2			319
-
-#define IMX8MP_CLK_END				320
+#define IMX8MP_CLK_USB_SUSP			320
+#define IMX8MP_CLK_AUDIO_AHB_ROOT		IMX8MP_CLK_AUDIO_ROOT
+#define IMX8MP_CLK_AUDIO_AXI_ROOT		321
+#define IMX8MP_CLK_SAI1_ROOT			322
+#define IMX8MP_CLK_SAI2_ROOT			323
+#define IMX8MP_CLK_SAI3_ROOT			324
+#define IMX8MP_CLK_SAI5_ROOT			325
+#define IMX8MP_CLK_SAI6_ROOT			326
+#define IMX8MP_CLK_SAI7_ROOT			327
+#define IMX8MP_CLK_PDM_ROOT			328
+#define IMX8MP_CLK_MEDIA_LDB_ROOT		329
+#define IMX8MP_CLK_END				330
 
 #define IMX8MP_CLK_AUDIOMIX_SAI1_IPG		0
 #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1		1
diff --git a/include/firmware/imx/sci/rpc.h b/include/firmware/imx/sci/rpc.h
index 39de7f0e3e..85af6f3996 100644
--- a/include/firmware/imx/sci/rpc.h
+++ b/include/firmware/imx/sci/rpc.h
@@ -23,12 +23,12 @@
 #define RPC_FUNC(MSG)           ((MSG)->func)
 #define RPC_R8(MSG)             ((MSG)->func)
 #define RPC_I64(MSG, IDX)       ((s64)(RPC_U32((MSG), (IDX))) << 32ULL) | \
-				  (s64)(RPC_U32((MSG), (IDX) + 4U))
+				(s64)(RPC_U32((MSG), (IDX) + 4U))
 #define RPC_I32(MSG, IDX)       ((MSG)->DATA.i32[(IDX) / 4U])
 #define RPC_I16(MSG, IDX)       ((MSG)->DATA.i16[(IDX) / 2U])
 #define RPC_I8(MSG, IDX)        ((MSG)->DATA.i8[(IDX)])
 #define RPC_U64(MSG, IDX)       ((u64)(RPC_U32((MSG), (IDX))) << 32ULL) | \
-				  (u64)(RPC_U32((MSG), (IDX) + 4U))
+				(u64)(RPC_U32((MSG), (IDX) + 4U))
 #define RPC_U32(MSG, IDX)       ((MSG)->DATA.u32[(IDX) / 4U])
 #define RPC_U16(MSG, IDX)       ((MSG)->DATA.u16[(IDX) / 2U])
 #define RPC_U8(MSG, IDX)        ((MSG)->DATA.u8[(IDX)])
@@ -67,7 +67,9 @@ struct sc_rpc_msg_s {
 #define PM_FUNC_SET_SYS_POWER_MODE		19U
 #define PM_FUNC_SET_PARTITION_POWER_MODE	1U
 #define PM_FUNC_GET_SYS_POWER_MODE		2U
+#define PM_FUNC_PARTITION_WAKE			28U
 #define PM_FUNC_SET_RESOURCE_POWER_MODE		3U
+#define PM_FUNC_SET_RESOURCE_POWER_MODE_ALL	22U
 #define PM_FUNC_GET_RESOURCE_POWER_MODE		4U
 #define PM_FUNC_REQ_LOW_POWER_MODE		16U
 #define PM_FUNC_REQ_CPU_LOW_POWER_MODE		20U
@@ -81,13 +83,16 @@ struct sc_rpc_msg_s {
 #define PM_FUNC_GET_CLOCK_PARENT		15U
 #define PM_FUNC_RESET				13U
 #define PM_FUNC_RESET_REASON			10U
+#define PM_FUNC_GET_RESET_PART			26U
 #define PM_FUNC_BOOT				8U
+#define PM_FUNC_SET_BOOT_PARM			27U
 #define PM_FUNC_REBOOT				9U
 #define PM_FUNC_REBOOT_PARTITION		12U
+#define PM_FUNC_REBOOT_CONTINUE			25U
 #define PM_FUNC_CPU_START			11U
 #define PM_FUNC_CPU_RESET			23U
 #define PM_FUNC_RESOURCE_RESET			29U
-#define PM_FUNC_IS_PARTITION_STARTED 24U
+#define PM_FUNC_IS_PARTITION_STARTED		24U
 
 /* MISC RPC */
 #define MISC_FUNC_UNKNOWN			0
@@ -95,16 +100,10 @@ struct sc_rpc_msg_s {
 #define MISC_FUNC_GET_CONTROL			2U
 #define MISC_FUNC_SET_MAX_DMA_GROUP		4U
 #define MISC_FUNC_SET_DMA_GROUP			5U
-#define MISC_FUNC_SECO_IMAGE_LOAD		8U
-#define MISC_FUNC_SECO_AUTHENTICATE		9U
-#define MISC_FUNC_SECO_FUSE_WRITE		20U
-#define MISC_FUNC_SECO_ENABLE_DEBUG		21U
-#define MISC_FUNC_SECO_FORWARD_LIFECYCLE	22U
-#define MISC_FUNC_SECO_RETURN_LIFECYCLE		23U
-#define MISC_FUNC_SECO_BUILD_INFO		24U
 #define MISC_FUNC_DEBUG_OUT			10U
 #define MISC_FUNC_WAVEFORM_CAPTURE		6U
 #define MISC_FUNC_BUILD_INFO			15U
+#define MISC_FUNC_API_VER			35U
 #define MISC_FUNC_UNIQUE_ID			19U
 #define MISC_FUNC_SET_ARI			3U
 #define MISC_FUNC_BOOT_STATUS			7U
@@ -114,8 +113,11 @@ struct sc_rpc_msg_s {
 #define MISC_FUNC_SET_TEMP			12U
 #define MISC_FUNC_GET_TEMP			13U
 #define MISC_FUNC_GET_BOOT_DEV			16U
+#define MISC_FUNC_GET_BOOT_TYPE			33U
+#define MISC_FUNC_GET_BOOT_CONTAINER		36U
 #define MISC_FUNC_GET_BUTTON_STATUS		18U
-#define MISC_FUNC_GET_BOOT_CONTAINER	36U
+#define MISC_FUNC_ROMPATCH_CHECKSUM		26U
+#define MISC_FUNC_BOARD_IOCTL			34U
 
 /* PAD RPC */
 #define PAD_FUNC_UNKNOWN			0
@@ -160,6 +162,7 @@ struct sc_rpc_msg_s {
 #define RM_FUNC_GET_RESOURCE_INFO		16U
 #define RM_FUNC_MEMREG_ALLOC			17U
 #define RM_FUNC_MEMREG_SPLIT			29U
+#define RM_FUNC_MEMREG_FRAG			32U
 #define RM_FUNC_MEMREG_FREE			18U
 #define RM_FUNC_FIND_MEMREG			30U
 #define RM_FUNC_ASSIGN_MEMREG			19U
@@ -190,6 +193,7 @@ struct sc_rpc_msg_s {
 #define SECO_FUNC_UPDATE_MPMR 14U /* Index for seco_update_mpmr() RPC call */
 #define SECO_FUNC_GET_MP_SIGN 15U /* Index for seco_get_mp_sign() RPC call */
 #define SECO_FUNC_BUILD_INFO 16U /* Index for seco_build_info() RPC call */
+#define SECO_FUNC_V2X_BUILD_INFO 30U /* Index for sc_seco_v2x_build_info() RPC call */
 #define SECO_FUNC_CHIP_INFO 17U /* Index for seco_chip_info() RPC call */
 #define SECO_FUNC_ENABLE_DEBUG 18U /* Index for seco_enable_debug() RPC call */
 #define SECO_FUNC_GET_EVENT 19U /* Index for seco_get_event() RPC call */
@@ -210,6 +214,7 @@ struct sc_rpc_msg_s {
 #define TIMER_FUNC_UNKNOWN 0 /* Unknown function */
 #define TIMER_FUNC_SET_WDOG_TIMEOUT 1U /* Index for sc_timer_set_wdog_timeout() RPC call */
 #define TIMER_FUNC_SET_WDOG_PRE_TIMEOUT 12U /* Index for sc_timer_set_wdog_pre_timeout() RPC call */
+#define TIMER_FUNC_SET_WDOG_WINDOW 19U /* Index for sc_timer_set_wdog_window() RPC call */
 #define TIMER_FUNC_START_WDOG 2U /* Index for sc_timer_start_wdog() RPC call */
 #define TIMER_FUNC_STOP_WDOG 3U /* Index for sc_timer_stop_wdog() RPC call */
 #define TIMER_FUNC_PING_WDOG 4U /* Index for sc_timer_ping_wdog() RPC call */
diff --git a/include/firmware/imx/sci/sci.h b/include/firmware/imx/sci/sci.h
index 61c8211b44..f832982b3d 100644
--- a/include/firmware/imx/sci/sci.h
+++ b/include/firmware/imx/sci/sci.h
@@ -13,6 +13,7 @@
 #include <firmware/imx/sci/svc/pm/api.h>
 #include <firmware/imx/sci/svc/rm/api.h>
 #include <firmware/imx/sci/svc/seco/api.h>
+#include <firmware/imx/sci/svc/timer/api.h>
 #include <firmware/imx/sci/rpc.h>
 #include <dt-bindings/soc/imx_rsrc.h>
 #include <linux/errno.h>
@@ -73,6 +74,7 @@ int sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
 			   sc_pm_clk_parent_t parent);
 int sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable,
 		    sc_faddr_t address);
+void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type);
 sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt);
 int sc_pm_resource_reset(sc_ipc_t ipc, sc_rsrc_t resource);
 
@@ -88,6 +90,7 @@ void sc_misc_build_info(sc_ipc_t ipc, u32 *build, u32 *commit);
 int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val);
 int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp,
 		     s16 *celsius, s8 *tenths);
+void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status);
 
 /* RM API */
 sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr);
@@ -117,6 +120,9 @@ int sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val);
 /* SMMU API */
 int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid);
 
+/* Timer API */
+int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window);
+
 /* SECO API */
 int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd,
 			 sc_faddr_t addr);
@@ -124,6 +130,7 @@ int sc_seco_forward_lifecycle(sc_ipc_t ipc, u32 change);
 int sc_seco_chip_info(sc_ipc_t ipc, u16 *lc, u16 *monotonic, u32 *uid_l,
 		      u32 *uid_h);
 void sc_seco_build_info(sc_ipc_t ipc, u32 *version, u32 *commit);
+int sc_seco_v2x_build_info(sc_ipc_t ipc, u32 *version, u32 *commit);
 int sc_seco_get_event(sc_ipc_t ipc, u8 idx, u32 *event);
 int sc_seco_gen_key_blob(sc_ipc_t ipc, u32 id, sc_faddr_t load_addr,
 			 sc_faddr_t export_addr, u16 max_size);
@@ -374,6 +381,23 @@ static inline int sc_seco_secvio_config(sc_ipc_t ipc, u8 id, u8 access, u32 *dat
 	return -EOPNOTSUPP;
 }
 
+static inline void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type)
+{
+}
+
+static inline int sc_seco_v2x_build_info(sc_ipc_t ipc, u32 *version, u32 *commit)
+{
+	return -EOPNOTSUPP;
+}
+
+static inline void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status)
+{
+}
+
+static inline int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window)
+{
+	return -EOPNOTSUPP;
+}
 #endif
 
 #endif
diff --git a/include/firmware/imx/sci/svc/misc/api.h b/include/firmware/imx/sci/svc/misc/api.h
index 3629eb68d7..a4b92b86cc 100644
--- a/include/firmware/imx/sci/svc/misc/api.h
+++ b/include/firmware/imx/sci/svc/misc/api.h
@@ -5,27 +5,45 @@
 
 #ifndef SC_MISC_API_H
 #define SC_MISC_API_H
+/* Defines for type widths */
+#define SC_MISC_DMA_GRP_W       5U      /* Width of sc_misc_dma_group_t */
 
+/* Max DMA channel priority group */
+#define SC_MISC_DMA_GRP_MAX     31U
 /* Defines for sc_misc_boot_status_t */
 #define SC_MISC_BOOT_STATUS_SUCCESS	0U	/* Success */
 #define SC_MISC_BOOT_STATUS_SECURITY	1U	/* Security violation */
 
-/* Defines for sc_misc_seco_auth_cmd_t */
-#define SC_MISC_SECO_AUTH_SECO_FW	0U   /* SECO Firmware */
-#define SC_MISC_SECO_AUTH_HDMI_TX_FW	1U   /* HDMI TX Firmware */
-#define SC_MISC_SECO_AUTH_HDMI_RX_FW	2U   /* HDMI RX Firmware */
-
 /* Defines for sc_misc_temp_t */
-#define SC_MISC_TEMP			0U	/* Temp sensor */
-#define SC_MISC_TEMP_HIGH		1U	/* Temp high alarm */
-#define SC_MISC_TEMP_LOW		2U	/* Temp low alarm */
+#define SC_MISC_TEMP                    0U   /* Temp sensor */
+#define SC_MISC_TEMP_HIGH               1U   /* Temp high alarm */
+#define SC_MISC_TEMP_LOW                2U   /* Temp low alarm */
+
+/* Defines for sc_misc_bt_t */
+#define SC_MISC_BT_PRIMARY              0U   /* Primary boot */
+#define SC_MISC_BT_SECONDARY            1U   /* Secondary boot */
+#define SC_MISC_BT_RECOVERY             2U   /* Recovery boot */
+#define SC_MISC_BT_MANUFACTURE          3U   /* Manufacture boot */
+#define SC_MISC_BT_SERIAL               4U   /* Serial boot */
+/* Types */
 
-/* Defines for sc_misc_seco_auth_cmd_t */
-#define SC_MISC_AUTH_CONTAINER	0U	/* Authenticate container */
-#define SC_MISC_VERIFY_IMAGE	1U	/* Verify image */
-#define SC_MISC_REL_CONTAINER	2U	/* Release container */
+/*
+ * This type is used to store a DMA channel priority group.
+ */
+typedef u8 sc_misc_dma_group_t;
 
+/*
+ * This type is used report boot status.
+ */
 typedef u8 sc_misc_boot_status_t;
+
+/*
+ * This type is used report boot status.
+ */
 typedef u8 sc_misc_temp_t;
 
+/*
+ * This type is used report the boot type.
+ */
+typedef u8 sc_misc_bt_t;
 #endif /* SC_MISC_API_H */
diff --git a/include/firmware/imx/sci/svc/pm/api.h b/include/firmware/imx/sci/svc/pm/api.h
index 9008b85c6f..d1b085d7f8 100644
--- a/include/firmware/imx/sci/svc/pm/api.h
+++ b/include/firmware/imx/sci/svc/pm/api.h
@@ -6,6 +6,14 @@
 #ifndef SC_PM_API_H
 #define SC_PM_API_H
 
+#include <firmware/imx/sci/types.h>
+/* Defines for type widths */
+#define SC_PM_POWER_MODE_W      2U      /* Width of sc_pm_power_mode_t */
+#define SC_PM_CLOCK_MODE_W      3U      /* Width of sc_pm_clock_mode_t */
+#define SC_PM_RESET_TYPE_W      2U      /* Width of sc_pm_reset_type_t */
+#define SC_PM_RESET_REASON_W    4U      /* Width of sc_pm_reset_reason_t */
+/* Defines for ALL parameters */
+#define SC_PM_CLK_ALL   ((sc_pm_clk_t)UINT8_MAX)   /* All clocks */
 /* Defines for sc_pm_power_mode_t */
 #define SC_PM_PW_MODE_OFF	0U /* Power off */
 #define SC_PM_PW_MODE_STBY	1U /* Power in standby */
@@ -35,10 +43,96 @@
 #define SC_PM_CLK_MODE_AUTOGATE_HW	4U /* Clock is in HW autogate mode */
 #define SC_PM_CLK_MODE_AUTOGATE_SW_HW	5U /* Clock is in SW-HW autogate mode */
 
+/* Defines for sc_pm_clk_parent_t */
+#define SC_PM_PARENT_XTAL              0U    /*!< Parent is XTAL. */
+#define SC_PM_PARENT_PLL0              1U    /*!< Parent is PLL0 */
+#define SC_PM_PARENT_PLL1              2U    /*!< Parent is PLL1 or PLL0/2 */
+#define SC_PM_PARENT_PLL2              3U    /*!< Parent in PLL2 or PLL0/4 */
+#define SC_PM_PARENT_BYPS              4U    /*!< Parent is a bypass clock. */
+
+/* Defines for sc_pm_reset_type_t */
+#define SC_PM_RESET_TYPE_COLD          0U    /* Cold reset */
+#define SC_PM_RESET_TYPE_WARM          1U    /* Warm reset */
+#define SC_PM_RESET_TYPE_BOARD         2U    /* Board reset */
+
+/* Defines for sc_pm_reset_reason_t */
+#define SC_PM_RESET_REASON_POR         0U    /* Power on reset */
+#define SC_PM_RESET_REASON_JTAG        1U    /* JTAG reset */
+#define SC_PM_RESET_REASON_SW          2U    /* Software reset */
+#define SC_PM_RESET_REASON_WDOG        3U    /* Partition watchdog reset */
+#define SC_PM_RESET_REASON_LOCKUP      4U    /* SCU lockup reset */
+#define SC_PM_RESET_REASON_SNVS        5U    /* SNVS reset */
+#define SC_PM_RESET_REASON_TEMP        6U    /* Temp panic reset */
+#define SC_PM_RESET_REASON_MSI         7U    /* MSI reset */
+#define SC_PM_RESET_REASON_UECC        8U    /* ECC reset */
+#define SC_PM_RESET_REASON_SCFW_WDOG   9U    /* SCFW watchdog reset */
+#define SC_PM_RESET_REASON_ROM_WDOG    10U   /* SCU ROM watchdog reset */
+#define SC_PM_RESET_REASON_SECO        11U   /* SECO reset */
+#define SC_PM_RESET_REASON_SCFW_FAULT  12U   /* SCFW fault reset */
+
+/* Defines for sc_pm_sys_if_t */
+#define SC_PM_SYS_IF_INTERCONNECT       0U   /* System interconnect */
+#define SC_PM_SYS_IF_MU                 1U   /* AP -> SCU message units */
+#define SC_PM_SYS_IF_OCMEM              2U   /* On-chip memory (ROM/OCRAM) */
+#define SC_PM_SYS_IF_DDR                3U   /* DDR memory */
+
+/* Defines for sc_pm_wake_src_t */
+/* No wake source, used for self-kill */
+#define SC_PM_WAKE_SRC_NONE             0U
+/* Wakeup from SCU to resume CPU (IRQSTEER & GIC powered down) */
+#define SC_PM_WAKE_SRC_SCU              1U
+/* Wakeup from IRQSTEER to resume CPU (GIC powered down) */
+#define SC_PM_WAKE_SRC_IRQSTEER         2U
+/* Wakeup from IRQSTEER+GIC to wake CPU (GIC clock gated) */
+#define SC_PM_WAKE_SRC_IRQSTEER_GIC     3U
+/* Wakeup from GIC to wake CPU */
+#define SC_PM_WAKE_SRC_GIC              4U
+/* Types */
+
+/*
+ * This type is used to declare a power mode. Note resources only use
+ * SC_PM_PW_MODE_OFF and SC_PM_PW_MODE_ON. The other modes are used only
+ * as system power modes.
+ */
 typedef u8 sc_pm_power_mode_t;
+
+/*
+ * This type is used to declare a clock.
+ */
 typedef u8 sc_pm_clk_t;
+
+/*
+ * This type is used to declare a clock mode.
+ */
 typedef u8 sc_pm_clk_mode_t;
+
+/*
+ * This type is used to declare the clock parent.
+ */
 typedef u8 sc_pm_clk_parent_t;
+
+/*
+ * This type is used to declare clock rates.
+ */
 typedef u32 sc_pm_clock_rate_t;
 
+/*
+ * This type is used to declare a desired reset type.
+ */
+typedef u8 sc_pm_reset_type_t;
+
+/*
+ * This type is used to declare a reason for a reset.
+ */
+typedef u8 sc_pm_reset_reason_t;
+
+/*
+ * This type is used to specify a system-level interface to be power managed.
+ */
+typedef u8 sc_pm_sys_if_t;
+
+/*
+ * This type is used to specify a wake source for CPU resources.
+ */
+typedef u8 sc_pm_wake_src_t;
 #endif /* SC_PM_API_H */
diff --git a/include/firmware/imx/sci/svc/rm/api.h b/include/firmware/imx/sci/svc/rm/api.h
index 163d81403c..f4e9abcd9b 100644
--- a/include/firmware/imx/sci/svc/rm/api.h
+++ b/include/firmware/imx/sci/svc/rm/api.h
@@ -38,32 +38,36 @@
 
 /* Types */
 
-/*!
+/*
  * This type is used to declare a resource partition.
  */
 typedef u8 sc_rm_pt_t;
 
-/*!
+/*
  * This type is used to declare a memory region.
  */
 typedef u8 sc_rm_mr_t;
 
-/*!
+/*
  * This type is used to declare a resource domain ID used by the
  * isolation HW.
  */
 typedef u8 sc_rm_did_t;
 
-/*!
+/*
  * This type is used to declare an SMMU StreamID.
  */
 typedef u16 sc_rm_sid_t;
 
-/*!
+/*
  * This type is a used to declare master transaction attributes.
  */
 typedef u8 sc_rm_spa_t;
 
+/*
+ * This type is used to declare a resource/memory region access permission.
+ * Refer to the XRDC2 Block Guide for more information.
+ */
 typedef u8 sc_rm_perm_t;
 
 #endif /* SC_RM_API_H */
diff --git a/include/firmware/imx/sci/svc/seco/api.h b/include/firmware/imx/sci/svc/seco/api.h
index 6e9c302315..7d4b6b92e1 100644
--- a/include/firmware/imx/sci/svc/seco/api.h
+++ b/include/firmware/imx/sci/svc/seco/api.h
@@ -17,6 +17,7 @@
 #define SC_SECO_AUTH_SECO_FW            3U   /* SECO Firmware */
 #define SC_SECO_AUTH_HDMI_TX_FW         4U   /* HDMI TX Firmware */
 #define SC_SECO_AUTH_HDMI_RX_FW         5U   /* HDMI RX Firmware */
+#define SC_SECO_EVERIFY_IMAGE           6U   /* Enhanced verify image */
 
 #define SC_SECO_RNG_STAT_UNAVAILABLE    0U  /* Unable to initialize the RNG */
 #define SC_SECO_RNG_STAT_INPROGRESS     1U  /* Initialization is on-going */
@@ -24,12 +25,12 @@
 
 /* Types */
 
-/*!
+/*
  * This type is used to issue SECO authenticate commands.
  */
 typedef u8 sc_seco_auth_cmd_t;
 
-/*!
+/*
  * This type is used to return the RNG initialization status.
  */
 typedef u32 sc_seco_rng_stat_t;
diff --git a/include/firmware/imx/sci/svc/timer/api.h b/include/firmware/imx/sci/svc/timer/api.h
new file mode 100644
index 0000000000..c2fe34aa75
--- /dev/null
+++ b/include/firmware/imx/sci/svc/timer/api.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier:     GPL-2.0+ */
+/*
+ * Copyright 2018-2019 NXP
+ */
+
+#ifndef SC_TIMER_API_H
+#define SC_TIMER_API_H
+
+/* Defines */
+
+/* Defines for type widths */
+#define SC_TIMER_ACTION_W   3U      /* Width of sc_timer_wdog_action_t */
+
+/* Defines for sc_timer_wdog_action_t */
+#define SC_TIMER_WDOG_ACTION_PARTITION      0U   /* Reset partition */
+#define SC_TIMER_WDOG_ACTION_WARM           1U   /* Warm reset system */
+#define SC_TIMER_WDOG_ACTION_COLD           2U   /* Cold reset system */
+#define SC_TIMER_WDOG_ACTION_BOARD          3U   /* Reset board */
+#define SC_TIMER_WDOG_ACTION_IRQ            4U   /* Only generate IRQs */
+
+/* Types */
+
+/*
+ * This type is used to configure the watchdog action.
+ */
+typedef u8 sc_timer_wdog_action_t;
+
+/*
+ * This type is used to declare a watchdog time value in milliseconds.
+ */
+typedef u32 sc_timer_wdog_time_t;
+
+#endif /* SC_TIMER_API_H */
diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index d8861d1d0b..9dad1d1ec4 100644
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -13,8 +13,8 @@
 #include <asm/io.h>
 
 #ifdef CONFIG_SYS_FSL_SEC_LE
-#define sec_in32(a)       in_le32((ulong *)(ulong)a)
-#define sec_out32(a, v)   out_le32((ulong *)(ulong)a, v)
+#define sec_in32(a)       in_le32((ulong *)(ulong)(a))
+#define sec_out32(a, v)   out_le32((ulong *)(ulong)(a), v)
 #define sec_in16(a)       in_le16(a)
 #define sec_clrbits32     clrbits_le32
 #define sec_setbits32     setbits_le32
diff --git a/include/imx_sip.h b/include/imx_sip.h
index ebbb3a16d7..8a5ca34f39 100644
--- a/include/imx_sip.h
+++ b/include/imx_sip.h
@@ -13,8 +13,8 @@
 #define IMX_SIP_BUILDINFO_GET_COMMITHASH	0x00
 
 #define IMX_SIP_SRC		0xC2000005
-#define IMX_SIP_SRC_M4_START	0x00
-#define IMX_SIP_SRC_M4_STARTED	0x01
-#define	IMX_SIP_SRC_M4_STOP	0x02
+#define IMX_SIP_SRC_MCU_START	0x00
+#define IMX_SIP_SRC_MCU_STARTED	0x01
+#define	IMX_SIP_SRC_MCU_STOP	0x02
 
 #endif