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author | Tom Rini <trini@konsulko.com> | 2016-05-24 13:42:03 -0400 |
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committer | Tom Rini <trini@konsulko.com> | 2016-05-24 13:42:03 -0400 |
commit | fc15b9beed05dec6cc092c265042381a0eadb0e9 (patch) | |
tree | 2b256906815661689177279d7cd23e30827c377b /include/fsl_ddr_sdram.h | |
parent | 2ee490a0245b65826a8ce8e42e34c9bf805d3656 (diff) | |
parent | bc323b3fa7cbf1008f02d342c0505231961b5fa6 (diff) |
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
Diffstat (limited to 'include/fsl_ddr_sdram.h')
-rw-r--r-- | include/fsl_ddr_sdram.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index cf316a4665..486e47e508 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -146,6 +146,10 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define WR_DATA_DELAY_SHIFT 10 #endif +/* DDR_EOR register */ +#define DDR_EOR_RD_REOD_DIS 0x07000000 +#define DDR_EOR_WD_REOD_DIS 0x00100000 + /* DDR_MD_CNTL */ #define MD_CNTL_MD_EN 0x80000000 #define MD_CNTL_CS_SEL_CS0 0x00000000 @@ -185,6 +189,13 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define DDR_MR5_CA_PARITY_LAT_4_CLK 0x1 /* for DDR4-1600/1866/2133 */ #define DDR_MR5_CA_PARITY_LAT_5_CLK 0x2 /* for DDR4-2400 */ +/* DEBUG_26 register */ +#define DDR_CAS_TO_PRE_SUB_MASK 0x0000f000 /* CAS to preamble subtract value */ +#define DDR_CAS_TO_PRE_SUB_SHIFT 12 + +/* DEBUG_29 register */ +#define DDR_TX_BD_DIS (1 << 10) /* Transmit Bit Deskew Disable */ + #if (defined(CONFIG_SYS_FSL_DDR_VER) && \ (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)) |