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authorJim Liu <jim.t90615@gmail.com>2022-09-27 16:45:15 +0800
committerTom Rini <trini@konsulko.com>2022-10-06 21:05:17 -0400
commit9ca71c9c19d83032a16c7df005cdb77f003ee438 (patch)
treeac6e7ba2cf9f2e3766bb727be4775f52d5a6d1c7 /include/dt-bindings/clock
parentd0fc8182596167ff71c73d9c9e4db69cf84c6071 (diff)
arm: nuvoton: Add support for Nuvoton NPCM845 BMC
Add basic support for the Nuvoton NPCM845 EVB (Arbel). Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
Diffstat (limited to 'include/dt-bindings/clock')
-rw-r--r--include/dt-bindings/clock/nuvoton,npcm845-clk.h52
1 files changed, 52 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/nuvoton,npcm845-clk.h b/include/dt-bindings/clock/nuvoton,npcm845-clk.h
new file mode 100644
index 0000000000..7f754f722c
--- /dev/null
+++ b/include/dt-bindings/clock/nuvoton,npcm845-clk.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2022 Nuvoton Technology Corp.
+ *
+ * Device Tree binding constants for NPCM8XX clock controller.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_NPCM8XX_H
+#define __DT_BINDINGS_CLOCK_NPCM8XX_H
+
+#define NPCM8XX_CLK_CPU 0
+#define NPCM8XX_CLK_GFX_PIXEL 1
+#define NPCM8XX_CLK_MC 2
+#define NPCM8XX_CLK_ADC 3
+#define NPCM8XX_CLK_AHB 4
+#define NPCM8XX_CLK_TIMER 5
+#define NPCM8XX_CLK_UART 6
+#define NPCM8XX_CLK_UART2 7
+#define NPCM8XX_CLK_MMC 8
+#define NPCM8XX_CLK_SPI3 9
+#define NPCM8XX_CLK_PCI 10
+#define NPCM8XX_CLK_AXI 11
+#define NPCM8XX_CLK_APB4 12
+#define NPCM8XX_CLK_APB3 13
+#define NPCM8XX_CLK_APB2 14
+#define NPCM8XX_CLK_APB1 15
+#define NPCM8XX_CLK_APB5 16
+#define NPCM8XX_CLK_CLKOUT 17
+#define NPCM8XX_CLK_GFX 18
+#define NPCM8XX_CLK_SU 19
+#define NPCM8XX_CLK_SU48 20
+#define NPCM8XX_CLK_SDHC 21
+#define NPCM8XX_CLK_SPI0 22
+#define NPCM8XX_CLK_SPI1 23
+#define NPCM8XX_CLK_SPIX 24
+#define NPCM8XX_CLK_RG 25
+#define NPCM8XX_CLK_RCP 26
+#define NPCM8XX_CLK_PRE_ADC 27
+#define NPCM8XX_CLK_ATB 28
+#define NPCM8XX_CLK_PRE_CLK 29
+#define NPCM8XX_CLK_TH 30
+#define NPCM8XX_CLK_REFCLK 31
+#define NPCM8XX_CLK_SYSBYPCK 32
+#define NPCM8XX_CLK_MCBYPCK 33
+#define NPCM8XX_CLK_PLL0 34
+#define NPCM8XX_CLK_PLL1 35
+#define NPCM8XX_CLK_PLL2 36
+#define NPCM8XX_CLK_PLL2DIV2 37
+
+#define NPCM8XX_NUM_CLOCKS (NPCM8XX_CLK_PLL2DIV2 + 1)
+
+#endif