Merge tag 'u-boot-stm32-20231215' of https://source.denx.de/u-boot/custodians/u-boot-stm into next

_ run savedefconfig on all STM32 defconfig

STM32 MCU:
_ Sync stm32f469-disco DT with Linux 6.5
_ rework ltdc node for stm32f769-disco
_ clk: stm32f: Fix settings for LCD_CLK
_ Support display on stm32f469-disco board

STM32 MPU:
_ stm32mp_dfu : Fix board_get_alt_info_mtd()
_ stm32mp_dfu : Simplify MTD device parsing

2 files changed, 45 insertions, 11 deletions

diff --git a/drivers/clk/stm32/clk-stm32f.c b/drivers/clk/stm32/clk-stm32f.c
index ed7660196e..d68c75ed20 100644
--- a/drivers/clk/stm32/clk-stm32f.c
+++ b/drivers/clk/stm32/clk-stm32f.c
@@ -522,17 +522,20 @@ static ulong stm32_set_rate(struct clk *clk, ulong rate)
 
 	/* get the current PLLSAIR output freq */
 	pllsair_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR);
-	best_div = pllsair_rate / rate;
-
-	/* look into pllsaidivr_table if this divider is available*/
-	for (i = 0 ; i < sizeof(pllsaidivr_table); i++)
-		if (best_div == pllsaidivr_table[i]) {
-			/* set pll_saidivr with found value */
-			clrsetbits_le32(&regs->dckcfgr,
-					RCC_DCKCFGR_PLLSAIDIVR_MASK,
-					pllsaidivr_table[i]);
-			return rate;
-		}
+	if ((pllsair_rate % rate) == 0) {
+		best_div = pllsair_rate / rate;
+
+		/* look into pllsaidivr_table if this divider is available */
+		for (i = 0 ; i < sizeof(pllsaidivr_table); i++)
+			if (best_div == pllsaidivr_table[i]) {
+				/* set pll_saidivr with found value */
+				clrsetbits_le32(&regs->dckcfgr,
+						RCC_DCKCFGR_PLLSAIDIVR_MASK,
+						pllsaidivr_table[i] <<
+						RCC_DCKCFGR_PLLSAIDIVR_SHIFT);
+				return rate;
+			}
+	}
 
 	/*
 	 * As no pllsaidivr value is suitable to obtain requested freq,
diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index 6fd90e3391..4f60ba8ebe 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -495,6 +495,33 @@ static void stm32_ltdc_set_layer1(struct stm32_ltdc_priv *priv, ulong fb_addr)
 	setbits_le32(priv->regs + LTDC_L1CR, LXCR_LEN);
 }
 
+#if IS_ENABLED(CONFIG_TARGET_STM32F469_DISCOVERY)
+static int stm32_ltdc_alloc_fb(struct udevice *dev)
+{
+	u32 sdram_size = gd->ram_size;
+	struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
+	phys_addr_t cpu;
+	dma_addr_t bus;
+	u64 dma_size;
+	int ret;
+
+	ret = dev_get_dma_range(dev, &cpu, &bus, &dma_size);
+	if (ret) {
+		dev_err(dev, "failed to get dma address\n");
+		return ret;
+	}
+
+	uc_plat->base = bus + sdram_size - ALIGN(uc_plat->size, uc_plat->align);
+	return 0;
+}
+#else
+static inline int stm32_ltdc_alloc_fb(struct udevice *dev)
+{
+	/* Delegate framebuffer allocation to video-uclass */
+	return 0;
+}
+#endif
+
 static int stm32_ltdc_probe(struct udevice *dev)
 {
 	struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
@@ -605,6 +632,10 @@ static int stm32_ltdc_probe(struct udevice *dev)
 	priv->crop_h = timings.vactive.typ;
 	priv->alpha = 0xFF;
 
+	ret = stm32_ltdc_alloc_fb(dev);
+	if (ret)
+		return ret;
+
 	dev_dbg(dev, "%dx%d %dbpp frame buffer at 0x%lx\n",
 		timings.hactive.typ, timings.vactive.typ,
 		VNBITS(priv->l2bpp), uc_plat->base);