diff options
| author | Bin Meng <bmeng@tinylab.org> | 2023-06-21 23:11:46 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2023-07-12 13:21:40 +0800 |
| commit | 9675d9202780fd996c00ad34f0360c89376205b3 (patch) | |
| tree | 45a6e78f33e00d2a1bbe996d5895162c7f9dbf05 /drivers | |
| parent | 7f1a30fdeb6b51ddeb8ca8ecbfcc8069721db186 (diff) | |
riscv: Rename SiFive CLINT to RISC-V ALINT
As the RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V
ALINT in the source tree to be future-proof.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/timer/Makefile | 2 | ||||
| -rw-r--r-- | drivers/timer/riscv_aclint_timer.c (renamed from drivers/timer/sifive_clint_timer.c) | 20 |
2 files changed, 11 insertions, 11 deletions
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index cdc20f5e94..1ca74805fd 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -25,7 +25,7 @@ obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o obj-$(CONFIG_SP804_TIMER) += sp804_timer.o -obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint_timer.o +obj-$(CONFIG_$(SPL_)RISCV_ACLINT) += riscv_aclint_timer.o obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o obj-$(CONFIG_STM32_TIMER) += stm32_timer.o obj-$(CONFIG_TEGRA_TIMER) += tegra-timer.o diff --git a/drivers/timer/sifive_clint_timer.c b/drivers/timer/riscv_aclint_timer.c index be45f17ddf..e29d527c8d 100644 --- a/drivers/timer/sifive_clint_timer.c +++ b/drivers/timer/riscv_aclint_timer.c @@ -18,7 +18,7 @@ /* mtime register */ #define MTIME_REG(base, offset) ((ulong)(base) + (offset)) -static u64 notrace sifive_clint_get_count(struct udevice *dev) +static u64 notrace riscv_aclint_timer_get_count(struct udevice *dev) { return readq((void __iomem *)MTIME_REG(dev_get_priv(dev), dev_get_driver_data(dev))); @@ -44,11 +44,11 @@ u64 notrace timer_early_get_count(void) } #endif -static const struct timer_ops sifive_clint_ops = { - .get_count = sifive_clint_get_count, +static const struct timer_ops riscv_aclint_timer_ops = { + .get_count = riscv_aclint_timer_get_count, }; -static int sifive_clint_probe(struct udevice *dev) +static int riscv_aclint_timer_probe(struct udevice *dev) { dev_set_priv(dev, dev_read_addr_ptr(dev)); if (!dev_get_priv(dev)) @@ -57,18 +57,18 @@ static int sifive_clint_probe(struct udevice *dev) return timer_timebase_fallback(dev); } -static const struct udevice_id sifive_clint_ids[] = { +static const struct udevice_id riscv_aclint_timer_ids[] = { { .compatible = "riscv,clint0", .data = CLINT_MTIME_OFFSET }, { .compatible = "sifive,clint0", .data = CLINT_MTIME_OFFSET }, { .compatible = "riscv,aclint-mtimer", .data = ACLINT_MTIME_OFFSET }, { } }; -U_BOOT_DRIVER(sifive_clint) = { - .name = "sifive_clint", +U_BOOT_DRIVER(riscv_aclint_timer) = { + .name = "riscv_aclint_timer", .id = UCLASS_TIMER, - .of_match = sifive_clint_ids, - .probe = sifive_clint_probe, - .ops = &sifive_clint_ops, + .of_match = riscv_aclint_timer_ids, + .probe = riscv_aclint_timer_probe, + .ops = &riscv_aclint_timer_ops, .flags = DM_FLAG_PRE_RELOC, }; |