Merge branch '2021-04-11-remove-non-migrated-boards'

- Remove a large number of boards that have not migrated to DM_MMC, for
  which the migration deadline with 2 years ago at v2019.04.

10 files changed, 4 insertions, 215 deletions

diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index f2f8275aec..9ff4b8736c 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -62,6 +62,7 @@ config DWC_AHCI
 config DWC_AHSATA
 	bool "Enable DWC AHSATA driver support"
 	select LIBATA
+	depends on BLK
 	help
 	  Enable this driver to support the DWC AHSATA SATA controller found
 	  in i.MX5 and i.MX6 SoCs.
@@ -82,12 +83,6 @@ config FSL_SATA
 	  Enable this driver to support the SATA controller found in
 	  some Freescale PowerPC SoCs.
 
-config MVSATA_IDE
-	bool "Enable Marvell SATA controller driver support via IDE interface"
-	help
-	  Enable this driver to support the SATA controller found in
-	  some Marvell SoCs, running in IDE compatibility mode using PIO.
-
 config SATA_MV
 	bool "Enable Marvell SATA controller driver support"
 	select AHCI
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 98fb480700..4811b2f82c 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -10,7 +10,6 @@ obj-$(CONFIG_SCSI_AHCI) += ahci.o
 obj-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o
 obj-$(CONFIG_FSL_SATA) += fsl_sata.o
 obj-$(CONFIG_LIBATA) += libata.o
-obj-$(CONFIG_MVSATA_IDE) += mvsata_ide.o
 obj-$(CONFIG_SATA) += sata.o
 obj-$(CONFIG_SATA_CEVA) += sata_ceva.o
 obj-$(CONFIG_SATA_MV) += sata_mv.o
diff --git a/drivers/ata/mvsata_ide.c b/drivers/ata/mvsata_ide.c
deleted file mode 100644
index 41f9a91617..0000000000
--- a/drivers/ata/mvsata_ide.c
+++ /dev/null
@@ -1,199 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
- *
- * Written-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-
-#if defined(CONFIG_ARCH_ORION5X)
-#include <asm/arch/orion5x.h>
-#elif defined(CONFIG_ARCH_KIRKWOOD)
-#include <asm/arch/soc.h>
-#elif defined(CONFIG_ARCH_MVEBU)
-#include <linux/mbus.h>
-#endif
-
-/* SATA port registers */
-struct mvsata_port_registers {
-	u32 reserved0[10];
-	u32 edma_cmd;
-	u32 reserved1[181];
-	/* offset 0x300 : ATA Interface registers */
-	u32 sstatus;
-	u32 serror;
-	u32 scontrol;
-	u32 ltmode;
-	u32 phymode3;
-	u32 phymode4;
-	u32 reserved2[5];
-	u32 phymode1;
-	u32 phymode2;
-	u32 bist_cr;
-	u32 bist_dw1;
-	u32 bist_dw2;
-	u32 serrorintrmask;
-};
-
-/*
- * Sanity checks:
- * - to compile at all, we need CONFIG_SYS_ATA_BASE_ADDR.
- * - for ide_preinit to make sense, we need at least one of
- *   CONFIG_SYS_ATA_IDE0_OFFSET or CONFIG_SYS_ATA_IDE1_OFFSET;
- * - for ide_preinit to be called, we need CONFIG_IDE_PREINIT.
- * Fail with an explanation message if these conditions are not met.
- * This is particularly important for CONFIG_IDE_PREINIT, because
- * its lack would not cause a build error.
- */
-
-#if !defined(CONFIG_SYS_ATA_BASE_ADDR)
-#error CONFIG_SYS_ATA_BASE_ADDR must be defined
-#elif !defined(CONFIG_SYS_ATA_IDE0_OFFSET) \
-   && !defined(CONFIG_SYS_ATA_IDE1_OFFSET)
-#error CONFIG_SYS_ATA_IDE0_OFFSET or CONFIG_SYS_ATA_IDE1_OFFSET \
-   must be defined
-#elif !defined(CONFIG_IDE_PREINIT)
-#error CONFIG_IDE_PREINIT must be defined
-#endif
-
-/*
- * Masks and values for SControl DETection and Interface Power Management,
- * and for SStatus DETection.
- */
-
-#define MVSATA_EDMA_CMD_ATA_RST		0x00000004
-#define MVSATA_SCONTROL_DET_MASK		0x0000000F
-#define MVSATA_SCONTROL_DET_NONE		0x00000000
-#define MVSATA_SCONTROL_DET_INIT		0x00000001
-#define MVSATA_SCONTROL_IPM_MASK		0x00000F00
-#define MVSATA_SCONTROL_IPM_NO_LP_ALLOWED	0x00000300
-#define MVSATA_SCONTROL_MASK \
-	(MVSATA_SCONTROL_DET_MASK|MVSATA_SCONTROL_IPM_MASK)
-#define MVSATA_PORT_INIT \
-	(MVSATA_SCONTROL_DET_INIT|MVSATA_SCONTROL_IPM_NO_LP_ALLOWED)
-#define MVSATA_PORT_USE \
-	(MVSATA_SCONTROL_DET_NONE|MVSATA_SCONTROL_IPM_NO_LP_ALLOWED)
-#define MVSATA_SSTATUS_DET_MASK			0x0000000F
-#define MVSATA_SSTATUS_DET_DEVCOMM		0x00000003
-
-/*
- * Status codes to return to client callers. Currently, callers ignore
- * exact value and only care for zero or nonzero, so no need to make this
- * public, it is only #define'd for clarity.
- * If/when standard negative codes are implemented in U-Boot, then these
- * #defines should be moved to, or replaced by ones from, the common list
- * of status codes.
- */
-
-#define MVSATA_STATUS_OK	0
-#define MVSATA_STATUS_TIMEOUT	-1
-
-/*
- * Registers for SATA MBUS memory windows
- */
-
-#define MVSATA_WIN_CONTROL(w)	(MVEBU_AXP_SATA_BASE + 0x30 + ((w) << 4))
-#define MVSATA_WIN_BASE(w)	(MVEBU_AXP_SATA_BASE + 0x34 + ((w) << 4))
-
-/*
- * Initialize SATA memory windows for Armada XP
- */
-
-#ifdef CONFIG_ARCH_MVEBU
-static void mvsata_ide_conf_mbus_windows(void)
-{
-	const struct mbus_dram_target_info *dram;
-	int i;
-
-	dram = mvebu_mbus_dram_info();
-
-	/* Disable windows, Set Size/Base to 0  */
-	for (i = 0; i < 4; i++) {
-		writel(0, MVSATA_WIN_CONTROL(i));
-		writel(0, MVSATA_WIN_BASE(i));
-	}
-
-	for (i = 0; i < dram->num_cs; i++) {
-		const struct mbus_dram_window *cs = dram->cs + i;
-		writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
-				(dram->mbus_dram_target_id << 4) | 1,
-				MVSATA_WIN_CONTROL(i));
-		writel(cs->base & 0xffff0000, MVSATA_WIN_BASE(i));
-	}
-}
-#endif
-
-/*
- * Initialize one MVSATAHC port: set SControl's IPM to "always active"
- * and DET to "reset", then wait for SStatus's DET to become "device and
- * comm ok" (or time out after 50 us if no device), then set SControl's
- * DET back to "no action".
- */
-
-static int mvsata_ide_initialize_port(struct mvsata_port_registers *port)
-{
-	u32 control;
-	u32 status;
-	u32 timeleft = 10000; /* wait at most 10 ms for SATA reset to complete */
-
-	/* Hard reset */
-	writel(MVSATA_EDMA_CMD_ATA_RST, &port->edma_cmd);
-	udelay(25); /* taken from original marvell port */
-	writel(0, &port->edma_cmd);
-
-	/* Set control IPM to 3 (no low power) and DET to 1 (initialize) */
-	control = readl(&port->scontrol);
-	control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_INIT;
-	writel(control, &port->scontrol);
-	/* Toggle control DET back to 0 (normal operation) */
-	control = (control & ~MVSATA_SCONTROL_MASK) | MVSATA_PORT_USE;
-	writel(control, &port->scontrol);
-	/* wait for status DET to become 3 (device and communication OK) */
-	while (--timeleft) {
-		status = readl(&port->sstatus) & MVSATA_SSTATUS_DET_MASK;
-		if (status == MVSATA_SSTATUS_DET_DEVCOMM)
-			break;
-		udelay(1);
-	}
-	/* return success or time-out error depending on time left */
-	if (!timeleft)
-		return MVSATA_STATUS_TIMEOUT;
-	return MVSATA_STATUS_OK;
-}
-
-/*
- * ide_preinit() will be called by ide_init in cmd_ide.c and will
- * reset the MVSTATHC ports needed by the board.
- */
-
-int ide_preinit(void)
-{
-	int ret = MVSATA_STATUS_TIMEOUT;
-	int status;
-
-#ifdef CONFIG_ARCH_MVEBU
-	mvsata_ide_conf_mbus_windows();
-#endif
-
-	/* Enable ATA port 0 (could be SATA port 0 or 1) if declared */
-#if defined(CONFIG_SYS_ATA_IDE0_OFFSET)
-	status = mvsata_ide_initialize_port(
-		(struct mvsata_port_registers *)
-		(CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET));
-	if (status == MVSATA_STATUS_OK)
-		ret = MVSATA_STATUS_OK;
-#endif
-	/* Enable ATA port 1 (could be SATA port 0 or 1) if declared */
-#if defined(CONFIG_SYS_ATA_IDE1_OFFSET)
-	status = mvsata_ide_initialize_port(
-		(struct mvsata_port_registers *)
-		(CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE1_OFFSET));
-	if (status == MVSATA_STATUS_OK)
-		ret = MVSATA_STATUS_OK;
-#endif
-	/* Return success if at least one port initialization succeeded */
-	return ret;
-}
diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig
index 5f62489a90..8b480dfd69 100644
--- a/drivers/ddr/fsl/Kconfig
+++ b/drivers/ddr/fsl/Kconfig
@@ -44,7 +44,6 @@ config SYS_NUM_DDR_CTLRS
 			ARCH_MPC8572	|| \
 			ARCH_MPC8641	|| \
 			ARCH_P4080	|| \
-			ARCH_P5020	|| \
 			ARCH_P5040	|| \
 			ARCH_LX2160A	|| \
 			ARCH_LX2162A	|| \
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 1844941eb2..57a4efb88e 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -479,7 +479,7 @@ config SYS_I2C_UNIPHIER_F
 
 config SYS_I2C_VERSATILE
 	bool "Arm Ltd Versatile I2C bus driver"
-	depends on DM_I2C && (TARGET_VEXPRESS_CA15_TC2 || TARGET_VEXPRESS64_JUNO)
+	depends on DM_I2C && TARGET_VEXPRESS64_JUNO
 	help
 	  Add support for the Arm Ltd Versatile Express I2C driver. The I2C host
 	  controller is present in the development boards manufactured by Arm Ltd.
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 197aa82040..d862d1e202 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -804,7 +804,7 @@ config FSL_ESDHC_IMX
 
 config FSL_USDHC
 	bool "Freescale/NXP i.MX uSDHC controller support"
-	depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || IMXRT || TARGET_S32V234EVB
+	depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || IMXRT
 	select FSL_ESDHC_IMX
 	help
 	  This enables the Ultra Secured Digital Host Controller enhancements
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index cf062fad4d..54f7b81624 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -721,13 +721,11 @@ config SYS_DPAA_QBMAN
 		     ARCH_T1040 || \
 		     ARCH_T1042 || \
 		     ARCH_T2080 || \
-		     ARCH_T2081 || \
 		     ARCH_T4240 || \
 		     ARCH_T4160 || \
 		     ARCH_P4080 || \
 		     ARCH_P3041 || \
 		     ARCH_P5040 || \
-		     ARCH_P5020 || \
 		     ARCH_LS1043A || \
 		     ARCH_LS1046A
 	help
diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index e10db710e6..b4ede61113 100644
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -20,14 +20,12 @@ obj-$(CONFIG_ARCH_P1023)	+= p1023.o
 obj-$(CONFIG_ARCH_P2041) += p5020.o
 obj-$(CONFIG_ARCH_P3041) += p5020.o
 obj-$(CONFIG_ARCH_P4080) += p4080.o
-obj-$(CONFIG_ARCH_P5020) += p5020.o
 obj-$(CONFIG_ARCH_P5040) += p5040.o
 obj-$(CONFIG_ARCH_T1040) += t1040.o
 obj-$(CONFIG_ARCH_T1042)	+= t1040.o
 obj-$(CONFIG_ARCH_T1023) += t1024.o
 obj-$(CONFIG_ARCH_T1024) += t1024.o
 obj-$(CONFIG_ARCH_T2080) += t2080.o
-obj-$(CONFIG_ARCH_T2081) += t2080.o
 obj-$(CONFIG_ARCH_T4240) += t4240.o
 obj-$(CONFIG_ARCH_T4160) += t4240.o
 obj-$(CONFIG_ARCH_B4420) += b4860.o
diff --git a/drivers/qe/Kconfig b/drivers/qe/Kconfig
index 864b36b822..553ed5780e 100644
--- a/drivers/qe/Kconfig
+++ b/drivers/qe/Kconfig
@@ -14,7 +14,6 @@ config U_QE
 	default y if (ARCH_LS1021A && !SD_BOOT && !NAND_BOOT && !QSPI_BOOT) \
 		|| (TARGET_T1024QDS) \
 		|| (TARGET_T1024RDB) \
-		|| (TARGET_T1040QDS && !NOBQFMAN) \
 		|| (TARGET_LS1043ARDB && !SPL_NO_QE && !NAND_BOOT && !QSPI_BOOT)
 	help
 	  Choose this option to add support for U QUICC Engine.
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 24413d14f9..af83e9673a 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -635,7 +635,7 @@ config MCFUART
 
 config MXC_UART
 	bool "IMX serial port support"
-	depends on ARCH_MX25 || ARCH_MX31 || TARGET_APF27 || TARGET_FLEA3 \
+	depends on ARCH_MX25 || ARCH_MX31 || TARGET_FLEA3 \
 		|| MX5 || MX6 || MX7 || IMX8M
 	help
 	  If you have a machine based on a Motorola IMX CPU you