diff options
| author | Stefan Roese <sr@denx.de> | 2006-11-10 07:48:47 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2006-11-10 07:48:47 +0100 |
| commit | dfc8a9ee0040e53ada125a3c52f241e37f09cf28 (patch) | |
| tree | 60fd3973150a4e6b3d9d129d117ecab71b5edabe /drivers/tsec.h | |
| parent | 5c912cb1c31266c66ca59b36f9b6f87296421d75 (diff) | |
| parent | 91650b3e4de688038d4f71279c44858e3e2c6870 (diff) | |
Merge with /home/stefan/git/u-boot/denx
Diffstat (limited to 'drivers/tsec.h')
| -rw-r--r-- | drivers/tsec.h | 37 |
1 files changed, 36 insertions, 1 deletions
diff --git a/drivers/tsec.h b/drivers/tsec.h index b55b2992b2..4aa331c458 100644 --- a/drivers/tsec.h +++ b/drivers/tsec.h @@ -27,7 +27,7 @@ #define TSEC_SIZE 0x01000 /* FIXME: Should these be pushed back to 83xx and 85xx config files? */ -#if defined(CONFIG_MPC85xx) +#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) #define TSEC_BASE_ADDR (CFG_IMMR + CFG_TSEC1_OFFSET) #elif defined(CONFIG_MPC83XX) #define TSEC_BASE_ADDR (CFG_IMMRBAR + CFG_TSEC1_OFFSET) @@ -133,6 +133,24 @@ #define MIIM_GBIT_CON 0x09 #define MIIM_GBIT_CON_ADVERT 0x0e00 +/* Entry for Vitesse VSC8244 regs starts here */ +/* Vitesse VSC8244 Auxiliary Control/Status Register */ +#define MIIM_VSC8244_AUX_CONSTAT 0x1c +#define MIIM_VSC8244_AUXCONSTAT_INIT 0x0000 +#define MIIM_VSC8244_AUXCONSTAT_DUPLEX 0x0020 +#define MIIM_VSC8244_AUXCONSTAT_SPEED 0x0018 +#define MIIM_VSC8244_AUXCONSTAT_GBIT 0x0010 +#define MIIM_VSC8244_AUXCONSTAT_100 0x0008 +#define MIIM_CONTROL_INIT_LOOPBACK 0x4000 + +/* Vitesse VSC8244 Extended PHY Control Register 1 */ +#define MIIM_VSC8244_EPHY_CON 0x17 +#define MIIM_VSC8244_EPHYCON_INIT 0x0006 + +/* Vitesse VSC8244 Serial LED Control Register */ +#define MIIM_VSC8244_LED_CON 0x1b +#define MIIM_VSC8244_LEDCON_INIT 0xF011 + /* 88E1011 PHY Status Register */ #define MIIM_88E1011_PHY_STATUS 0x11 #define MIIM_88E1011_PHYSTAT_SPEED 0xc000 @@ -142,6 +160,23 @@ #define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800 #define MIIM_88E1011_PHYSTAT_LINK 0x0400 +#define MIIM_88E1011_PHY_SCR 0x10 +#define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060 + +/* 88E1111 PHY LED Control Register */ +#define MIIM_88E1111_PHY_LED_CONTROL 24 +#define MIIM_88E1111_PHY_LED_DIRECT 0x4100 +#define MIIM_88E1111_PHY_LED_COMBINE 0x411C + +/* 88E1145 Extended PHY Specific Control Register */ +#define MIIM_88E1145_PHY_EXT_CR 20 +#define MIIM_M88E1145_RGMII_RX_DELAY 0x0080 +#define MIIM_M88E1145_RGMII_TX_DELAY 0x0002 + +#define MIIM_88E1145_PHY_PAGE 29 +#define MIIM_88E1145_PHY_CAL_OV 30 + + /* DM9161 Control register values */ #define MIIM_DM9161_CR_STOP 0x0400 #define MIIM_DM9161_CR_RSTAN 0x1200 |